
module usb_tx_phy ( clk, rst, fs_ce, phy_mode, txdp, txdn, txoe, DataOut_i, 
        TxValid_i, TxReady_o );
  input [7:0] DataOut_i;
  input clk, rst, fs_ce, phy_mode, TxValid_i;
  output txdp, txdn, txoe, TxReady_o;
  wire   tx_ready_d, N29, ld_data, tx_ip, tx_ip_sync, data_done, sd_raw_o, N84,
         N85, sft_done, sft_done_r, sd_bs_o, sd_nrzi_o, txoe_r1,
         append_eop_sync2, append_eop, append_eop_sync1, append_eop_sync3,
         append_eop_sync4, txoe_r2, n30, n31, n32, n33, n34, n35, n36, n37,
         n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51,
         n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65,
         n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79,
         n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93,
         n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
         n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
         n117, n118, n119, n120, n121, n122, n123, n124, n125, n1, n2, n3, n4,
         n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19,
         n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n126, n127, n128,
         n129, n130, n131, n132;
  wire   [2:0] bit_cnt;
  wire   [7:0] hold_reg_d;
  wire   [7:0] hold_reg;
  wire   [2:0] one_cnt;
  wire   [2:0] state;

  ao2i3 U8 ( .A(n23), .B(n132), .C(sd_nrzi_o), .D(n16), .Y(n35) );
  ao4f3 U16 ( .A(n42), .B(n24), .C(n23), .D(n31), .Y(n98) );
  ao4a3 U23 ( .A(n48), .B(bit_cnt[1]), .C(n14), .D(n49), .Y(n101) );
  ao4f3 U25 ( .A(n27), .B(n51), .C(bit_cnt[0]), .D(n50), .Y(n102) );
  ao4f3 U29 ( .A(n129), .B(n54), .C(one_cnt[0]), .D(n41), .Y(n104) );
  ao4f3 U33 ( .A(n42), .B(n127), .C(n31), .D(n126), .Y(n106) );
  ao4a3 U35 ( .A(tx_ip), .B(n16), .C(n17), .D(tx_ip_sync), .Y(n108) );
  ao4f3 U38 ( .A(n31), .B(n22), .C(n60), .D(n23), .Y(n110) );
  ao4a3 U40 ( .A(append_eop_sync1), .B(n16), .C(n17), .D(append_eop_sync2), 
        .Y(n111) );
  ao4a3 U41 ( .A(n17), .B(append_eop_sync1), .C(n16), .D(append_eop), .Y(n112)
         );
  oa4f3 U58 ( .A(DataOut_i[7]), .B(n69), .C(hold_reg[7]), .D(n70), .Y(n68) );
  ao4f3 U72 ( .A(n10), .B(n131), .C(n76), .D(n74), .Y(n124) );
  ao4f3 U73 ( .A(n10), .B(n18), .C(state[0]), .D(n74), .Y(n125) );
  ao4f3 U79 ( .A(n82), .B(n25), .C(n83), .D(n76), .Y(n80) );
  and2b2 U80 ( .B(n82), .A(n84), .Y(n76) );
  ao4f3 U81 ( .A(TxValid_i), .B(n20), .C(n23), .D(n19), .Y(n79) );
  oa4f3 U85 ( .A(n86), .B(n29), .C(bit_cnt[2]), .D(n87), .Y(n85) );
  ao2i3 U86 ( .A(bit_cnt[0]), .B(n88), .C(n89), .D(n90), .Y(n87) );
  oa4f3 U89 ( .A(hold_reg_d[4]), .B(n28), .C(hold_reg_d[6]), .D(bit_cnt[1]), 
        .Y(n88) );
  ao2i3 U90 ( .A(bit_cnt[0]), .B(n91), .C(n92), .D(n93), .Y(n86) );
  oa4f3 U95 ( .A(hold_reg_d[0]), .B(n28), .C(hold_reg_d[2]), .D(bit_cnt[1]), 
        .Y(n91) );
  ao4a3 U97 ( .A(n83), .B(n84), .C(n63), .D(data_done), .Y(tx_ready_d) );
  and2b2 U98 ( .B(n83), .A(n82), .Y(n63) );
  and2b2 U102 ( .B(sft_done), .A(sft_done_r), .Y(n83) );
  fdf1a3 \hold_reg_d_reg[6]  ( .D(hold_reg[6]), .CLK(n4), .Q(hold_reg_d[6]) );
  fdf1a3 \hold_reg_d_reg[4]  ( .D(hold_reg[4]), .CLK(n5), .Q(hold_reg_d[4]) );
  fdf1a3 \hold_reg_d_reg[2]  ( .D(hold_reg[2]), .CLK(n5), .Q(hold_reg_d[2]) );
  fdf1a3 \hold_reg_d_reg[0]  ( .D(hold_reg[0]), .CLK(n5), .Q(hold_reg_d[0]) );
  fdf1a3 sft_done_r_reg ( .D(sft_done), .CLK(n6), .Q(sft_done_r) );
  fdf1a3 \hold_reg_d_reg[7]  ( .D(hold_reg[7]), .CLK(n4), .Q(hold_reg_d[7]) );
  fdf1a3 \hold_reg_d_reg[5]  ( .D(hold_reg[5]), .CLK(n4), .Q(hold_reg_d[5]) );
  fdf1a3 \hold_reg_d_reg[3]  ( .D(hold_reg[3]), .CLK(n5), .Q(hold_reg_d[3]) );
  fdf1a3 \hold_reg_d_reg[1]  ( .D(hold_reg[1]), .CLK(n5), .Q(hold_reg_d[1]) );
  fdf1a3 sd_raw_o_reg ( .D(N84), .CLK(n6), .Q(sd_raw_o) );
  fdf1a3 append_eop_sync4_reg ( .D(n98), .CLK(n7), .Q(append_eop_sync4) );
  fdf1a3 txoe_r2_reg ( .D(n106), .CLK(n7), .Q(txoe_r2) );
  fdf1a3 ld_data_reg ( .D(tx_ready_d), .CLK(n8), .Q(ld_data) );
  fdf1a3 sft_done_reg ( .D(N85), .CLK(n6), .Q(sft_done) );
  fdf1a3 \hold_reg_reg[7]  ( .D(n115), .CLK(n4), .Q(hold_reg[7]) );
  fdf1a3 \hold_reg_reg[6]  ( .D(n116), .CLK(n4), .Q(hold_reg[6]) );
  fdf1a3 \hold_reg_reg[5]  ( .D(n117), .CLK(n4), .Q(hold_reg[5]) );
  fdf1a3 \hold_reg_reg[4]  ( .D(n118), .CLK(n4), .Q(hold_reg[4]) );
  fdf1a3 \hold_reg_reg[3]  ( .D(n119), .CLK(n5), .Q(hold_reg[3]) );
  fdf1a3 \hold_reg_reg[2]  ( .D(n120), .CLK(n5), .Q(hold_reg[2]) );
  fdf1a3 \hold_reg_reg[1]  ( .D(n121), .CLK(n5), .Q(hold_reg[1]) );
  fdf1a3 \hold_reg_reg[0]  ( .D(n122), .CLK(n5), .Q(hold_reg[0]) );
  fdf1a3 append_eop_sync1_reg ( .D(n112), .CLK(n6), .Q(append_eop_sync1) );
  fdf1a3 txdp_reg ( .D(n95), .CLK(n8), .Q(txdp) );
  fdf1a3 txdn_reg ( .D(n94), .CLK(n8), .Q(txdn) );
  fdf1a3 sd_bs_o_reg ( .D(n97), .CLK(n6), .Q(sd_bs_o) );
  fdf1a3 append_eop_sync2_reg ( .D(n111), .CLK(n6), .Q(append_eop_sync2) );
  fdf1a3 data_done_reg ( .D(n99), .CLK(n7), .Q(data_done) );
  fdf1a3 append_eop_reg ( .D(n113), .CLK(n6), .Q(append_eop) );
  fdf1a3 TxReady_o_reg ( .D(N29), .CLK(n8), .Q(TxReady_o) );
  fdf1a3 \bit_cnt_reg[2]  ( .D(n100), .CLK(n7), .Q(bit_cnt[2]) );
  fdf1a3 txoe_reg ( .D(n105), .CLK(n8), .Q(txoe) );
  fdf1a3 \one_cnt_reg[1]  ( .D(n103), .CLK(n8), .Q(one_cnt[1]) );
  fdf1a3 tx_ip_sync_reg ( .D(n108), .CLK(n7), .Q(tx_ip_sync) );
  fdf1a3 \state_reg[0]  ( .D(n125), .CLK(n4), .Q(state[0]) );
  fdf1a3 tx_ip_reg ( .D(n109), .CLK(n7), .Q(tx_ip) );
  fdf1a3 sd_nrzi_o_reg ( .D(n96), .CLK(n8), .Q(sd_nrzi_o) );
  fdf1a3 \state_reg[2]  ( .D(n123), .CLK(n4), .Q(state[2]) );
  fdf1a3 \one_cnt_reg[2]  ( .D(n114), .CLK(n6), .Q(one_cnt[2]) );
  fdf1a3 txoe_r1_reg ( .D(n107), .CLK(n7), .Q(txoe_r1) );
  fdf1a3 \state_reg[1]  ( .D(n124), .CLK(n8), .Q(state[1]) );
  fdf1a3 \bit_cnt_reg[0]  ( .D(n102), .CLK(n7), .Q(bit_cnt[0]) );
  fdf1a3 \bit_cnt_reg[1]  ( .D(n101), .CLK(n7), .Q(bit_cnt[1]) );
  fdf1a3 append_eop_sync3_reg ( .D(n110), .CLK(n6), .Q(append_eop_sync3) );
  fdf1a3 \one_cnt_reg[0]  ( .D(n104), .CLK(n8), .Q(one_cnt[0]) );
  and2a3 U3 ( .A(ld_data), .B(n58), .Y(n69) );
  or2c1 U4 ( .A(n68), .B(n58), .Y(n115) );
  and2b3 U5 ( .B(n58), .A(n69), .Y(n70) );
  or3d2 U6 ( .A(n71), .B(n18), .C(TxValid_i), .Y(n58) );
  ao4a1 U7 ( .A(hold_reg[0]), .B(n70), .C(DataOut_i[0]), .D(n69), .Y(n122) );
  ao4a1 U9 ( .A(hold_reg[1]), .B(n70), .C(DataOut_i[1]), .D(n69), .Y(n121) );
  ao4a1 U10 ( .A(hold_reg[2]), .B(n70), .C(DataOut_i[2]), .D(n69), .Y(n120) );
  ao4a1 U11 ( .A(hold_reg[3]), .B(n70), .C(DataOut_i[3]), .D(n69), .Y(n119) );
  ao4a1 U12 ( .A(hold_reg[4]), .B(n70), .C(DataOut_i[4]), .D(n69), .Y(n118) );
  ao4a1 U13 ( .A(hold_reg[5]), .B(n70), .C(DataOut_i[5]), .D(n69), .Y(n117) );
  ao4a1 U14 ( .A(hold_reg[6]), .B(n70), .C(DataOut_i[6]), .D(n69), .Y(n116) );
  inv1a1 U15 ( .A(n71), .Y(n20) );
  or3d1 U17 ( .A(one_cnt[1]), .B(n129), .C(one_cnt[2]), .Y(n67) );
  or2c1 U18 ( .A(n40), .B(txoe_r1), .Y(n37) );
  inv1a1 U19 ( .A(one_cnt[0]), .Y(n129) );
  inv1a1 U20 ( .A(state[1]), .Y(n131) );
  inv1a1 U21 ( .A(state[2]), .Y(n19) );
  inv1a1 U22 ( .A(append_eop_sync4), .Y(n24) );
  inv1a1 U24 ( .A(tx_ip_sync), .Y(n26) );
  inv1a3 U26 ( .A(n42), .Y(n17) );
  inv1a3 U27 ( .A(n50), .Y(n14) );
  or2c3 U28 ( .A(n10), .B(n1), .Y(n74) );
  or2c1 U30 ( .A(n40), .B(n50), .Y(n51) );
  and2c3 U31 ( .A(n28), .B(n27), .Y(n47) );
  and2c3 U32 ( .A(n26), .B(n2), .Y(n40) );
  inv1a3 U34 ( .A(n31), .Y(n16) );
  oa1f3 U36 ( .A(n16), .B(n24), .C(n17), .Y(n60) );
  or2c3 U37 ( .A(n1), .B(n31), .Y(n42) );
  or2c3 U39 ( .A(n15), .B(n67), .Y(n50) );
  and2c3 U42 ( .A(n20), .B(n18), .Y(n84) );
  inv1a3 U43 ( .A(n41), .Y(n13) );
  ao1f2 U44 ( .A(n42), .B(n126), .C(n57), .Y(n107) );
  ao1f2 U45 ( .A(n45), .B(n29), .C(n46), .Y(n100) );
  or3d1 U46 ( .A(n14), .B(n29), .C(n47), .Y(n46) );
  oa1f3 U47 ( .A(n14), .B(n28), .C(n48), .Y(n45) );
  or2c1 U48 ( .A(n40), .B(n57), .Y(n54) );
  inv1a3 U49 ( .A(n75), .Y(n10) );
  inv1a1 U50 ( .A(n57), .Y(n15) );
  clk1b6 U51 ( .A(n2), .Y(n1) );
  clk1a3 U52 ( .A(clk), .Y(n8) );
  clk1a3 U53 ( .A(clk), .Y(n7) );
  clk1a3 U54 ( .A(clk), .Y(n6) );
  clk1a3 U55 ( .A(clk), .Y(n5) );
  clk1a3 U56 ( .A(clk), .Y(n4) );
  clk1a3 U57 ( .A(n3), .Y(n2) );
  inv1a1 U59 ( .A(rst), .Y(n3) );
  inv1a3 U60 ( .A(state[0]), .Y(n18) );
  and2c3 U61 ( .A(n27), .B(bit_cnt[1]), .Y(n49) );
  ao1f2 U62 ( .A(n2), .B(n77), .C(n78), .Y(n75) );
  oa2i2 U63 ( .A(n79), .B(n18), .C(n80), .D(n81), .Y(n77) );
  or3d1 U64 ( .A(n1), .B(n11), .C(state[2]), .Y(n78) );
  and3d2 U65 ( .A(n131), .B(append_eop_sync3), .C(n18), .Y(n81) );
  or2c3 U66 ( .A(fs_ce), .B(n1), .Y(n31) );
  ao1f2 U67 ( .A(bit_cnt[0]), .B(n50), .C(n51), .Y(n48) );
  ao1f2 U68 ( .A(one_cnt[0]), .B(n41), .C(n54), .Y(n52) );
  and2c3 U69 ( .A(state[1]), .B(state[2]), .Y(n71) );
  or2c3 U70 ( .A(sd_raw_o), .B(n14), .Y(n41) );
  or2c3 U71 ( .A(tx_ip_sync), .B(n16), .Y(n57) );
  inv1a3 U74 ( .A(append_eop_sync3), .Y(n23) );
  ao1f2 U75 ( .A(fs_ce), .B(n37), .C(n39), .Y(n38) );
  or3d1 U76 ( .A(sd_bs_o), .B(n15), .C(txoe_r1), .Y(n39) );
  inv1a3 U77 ( .A(bit_cnt[1]), .Y(n28) );
  ao1f2 U78 ( .A(n30), .B(n31), .C(n32), .Y(n94) );
  or2c1 U82 ( .A(txdn), .B(n17), .Y(n32) );
  oa1f3 U83 ( .A(append_eop_sync3), .B(n132), .C(n33), .Y(n30) );
  and3d2 U84 ( .A(n132), .B(sd_nrzi_o), .C(append_eop_sync3), .Y(n33) );
  inv1a3 U87 ( .A(one_cnt[1]), .Y(n130) );
  inv1a3 U88 ( .A(bit_cnt[0]), .Y(n27) );
  ao1f2 U91 ( .A(n25), .B(n43), .C(n44), .Y(n99) );
  or3d1 U92 ( .A(n43), .B(n1), .C(TxValid_i), .Y(n44) );
  or3d1 U93 ( .A(TxValid_i), .B(n1), .C(tx_ip), .Y(n43) );
  ao1f2 U94 ( .A(n72), .B(n19), .C(n73), .Y(n123) );
  or3d1 U96 ( .A(state[1]), .B(state[0]), .C(n9), .Y(n73) );
  oa1f3 U99 ( .A(n1), .B(n18), .C(n75), .Y(n72) );
  inv1a1 U100 ( .A(n74), .Y(n9) );
  and2c1 U101 ( .A(one_cnt[2]), .B(n130), .Y(n66) );
  inv1a3 U103 ( .A(bit_cnt[2]), .Y(n29) );
  ao1f2 U104 ( .A(n64), .B(n21), .C(n65), .Y(n114) );
  inv1a1 U105 ( .A(one_cnt[2]), .Y(n21) );
  or3d1 U106 ( .A(one_cnt[0]), .B(n13), .C(n66), .Y(n65) );
  oa1f3 U107 ( .A(n13), .B(n130), .C(n52), .Y(n64) );
  ao1f2 U108 ( .A(n12), .B(n128), .C(n36), .Y(n96) );
  ao1f2 U109 ( .A(n128), .B(n37), .C(n12), .Y(n36) );
  inv1a1 U110 ( .A(n38), .Y(n12) );
  inv1a1 U111 ( .A(sd_nrzi_o), .Y(n128) );
  inv1a3 U112 ( .A(data_done), .Y(n25) );
  or2c3 U113 ( .A(state[1]), .B(n18), .Y(n82) );
  inv1a3 U114 ( .A(txoe_r1), .Y(n126) );
  inv1a3 U115 ( .A(phy_mode), .Y(n132) );
  oa1f3 U116 ( .A(n58), .B(n59), .C(n2), .Y(n109) );
  or2c1 U117 ( .A(tx_ip), .B(n23), .Y(n59) );
  and2c1 U118 ( .A(n85), .B(n26), .Y(N84) );
  ao1d2 U119 ( .A(n17), .B(sd_bs_o), .C(n41), .Y(n97) );
  or3d1 U120 ( .A(n34), .B(n35), .C(n1), .Y(n95) );
  or2c1 U121 ( .A(txdp), .B(n17), .Y(n34) );
  inv1a1 U122 ( .A(append_eop_sync2), .Y(n22) );
  inv1a1 U123 ( .A(txoe_r2), .Y(n127) );
  or2c1 U124 ( .A(hold_reg_d[7]), .B(n47), .Y(n90) );
  or2c1 U125 ( .A(hold_reg_d[3]), .B(n47), .Y(n93) );
  and3a2 U126 ( .A(bit_cnt[2]), .B(n67), .C(n47), .Y(N85) );
  ao1d2 U127 ( .A(n52), .B(one_cnt[1]), .C(n53), .Y(n103) );
  or3d1 U128 ( .A(n13), .B(n130), .C(one_cnt[0]), .Y(n53) );
  and3a2 U129 ( .A(TxValid_i), .B(tx_ready_d), .C(n1), .Y(N29) );
  inv1a1 U130 ( .A(fs_ce), .Y(n11) );
  or3d1 U131 ( .A(n55), .B(n56), .C(n1), .Y(n105) );
  or2c1 U132 ( .A(txoe), .B(n17), .Y(n55) );
  or3d1 U133 ( .A(n126), .B(n127), .C(n16), .Y(n56) );
  or2c1 U134 ( .A(hold_reg_d[5]), .B(n49), .Y(n89) );
  or2c1 U135 ( .A(hold_reg_d[1]), .B(n49), .Y(n92) );
  or2c1 U136 ( .A(n61), .B(n62), .Y(n113) );
  or3d1 U137 ( .A(n1), .B(n22), .C(append_eop), .Y(n61) );
  or3d1 U138 ( .A(n1), .B(n25), .C(n63), .Y(n62) );
endmodule


module usb_rx_phy ( clk, rst, fs_ce, rxd, rxdp, rxdn, RxValid_o, RxActive_o, 
        RxError_o, DataIn_o, RxEn_i, LineState );
  output [7:0] DataIn_o;
  output [1:0] LineState;
  input clk, rst, rxd, rxdp, rxdn, RxEn_i;
  output fs_ce, RxValid_o, RxActive_o, RxError_o;
  wire   sync_err, bit_stuff_err, byte_err, rx_en, N25, rxd_s0, rxd_s1, rxd_s,
         rxdp_s0, N29, rxdp_s_r, N30, rxdp_s, rxdn_s0, N31, rxdn_s_r, N32,
         rxdn_s, se0, se0_s, rxd_r, N34, N35, fs_ce_r1, fs_ce_r2, N50, N80,
         N81, N84, N87, N89, N90, rx_valid_r, sd_r, sd_nrzi, shift_en, N127,
         N129, rx_valid1, se0_r, N150, n1, n2, n3, n4, n5, n6, n7, n8, n36,
         n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
         n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
         n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
         n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
         n93, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
         n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
         n94, n95, n96, n97, n98, n99, n100, n101;
  wire   [1:0] dpll_state;
  wire   [2:0] fs_state;
  wire   [2:0] one_cnt;
  wire   [2:0] bit_cnt;

  xor2a2 U3 ( .A(fs_state[2]), .B(fs_state[1]), .Y(n1) );
  and2b2 U4 ( .B(N87), .A(fs_state[1]), .Y(n2) );
  mx2d2 U8 ( .D0(n22), .D1(n2), .S(fs_state[2]), .Y(n4) );
  or2b2 U10 ( .B(fs_state[1]), .A(N81), .Y(n5) );
  or2b2 U11 ( .B(n22), .A(n1), .Y(n6) );
  or2b2 U12 ( .B(fs_state[2]), .A(N80), .Y(n7) );
  or2b2 U13 ( .B(fs_state[1]), .A(N50), .Y(n8) );
  ao4a3 U24 ( .A(n44), .B(bit_cnt[1]), .C(n99), .D(n42), .Y(n83) );
  ao4f3 U27 ( .A(n98), .B(n45), .C(bit_cnt[0]), .D(n43), .Y(n84) );
  ao4f3 U37 ( .A(n96), .B(n53), .C(one_cnt[0]), .D(n52), .Y(n87) );
  xor2b2 U54 ( .A(rxd_s), .B(sd_r), .Y(n64) );
  ao2i3 U57 ( .A(n23), .B(n67), .C(n68), .D(n11), .Y(n65) );
  or3a3 U63 ( .A(sync_err), .B(byte_err), .C(bit_stuff_err), .Y(RxError_o) );
  ao2i3 U71 ( .A(n74), .B(n10), .C(n75), .D(n11), .Y(N34) );
  xor2a2 U75 ( .A(rxd_s), .B(rxd_r), .Y(n76) );
  and2c6 U86 ( .A(n79), .B(n95), .Y(N129) );
  fac2a1 U116 ( .A(rxd_s0), .B(rxd_s), .CI(rxd_s1), .CO(n72) );
  fdef1a3 sd_r_reg ( .D(rxd_s), .E(fs_ce), .CLK(n15), .Q(sd_r) );
  fdef1a3 se0_s_reg ( .D(se0), .E(fs_ce), .CLK(n15), .Q(se0_s) );
  fdf1a3 rxd_s1_reg ( .D(rxd_s0), .CLK(n13), .Q(rxd_s1) );
  fdf1a3 rxdp_s_r_reg ( .D(N29), .CLK(n13), .Q(rxdp_s_r) );
  fdf1a3 rxdn_s_r_reg ( .D(N31), .CLK(n14), .Q(rxdn_s_r) );
  fdf1a3 rxd_r_reg ( .D(rxd_s), .CLK(n14), .Q(rxd_r) );
  fdf1a3 bit_stuff_err_reg ( .D(N127), .CLK(n17), .Q(bit_stuff_err) );
  fdf1a3 sync_err_reg ( .D(N25), .CLK(n17), .Q(sync_err) );
  fdf1a3 byte_err_reg ( .D(N150), .CLK(n18), .Q(byte_err) );
  fdf1a3 \dpll_state_reg[0]  ( .D(N34), .CLK(n14), .Q(dpll_state[0]) );
  fdf1a3 rxdp_s0_reg ( .D(rxdp), .CLK(n13), .Q(rxdp_s0) );
  fdf1a3 rxdn_s0_reg ( .D(rxdn), .CLK(n13), .Q(rxdn_s0) );
  fdf1c3 se0_r_reg ( .D(n27), .CLK(n18), .QN(se0_r) );
  fdf1a3 rxd_s0_reg ( .D(rxd), .CLK(n13), .Q(rxd_s0) );
  fdf1a3 rxdp_s_reg ( .D(N30), .CLK(n13), .Q(rxdp_s) );
  fdf1a3 \bit_cnt_reg[2]  ( .D(n82), .CLK(n16), .Q(bit_cnt[2]) );
  fdf1a3 rx_valid1_reg ( .D(n81), .CLK(n16), .Q(rx_valid1) );
  fdf1a3 \dpll_state_reg[1]  ( .D(N35), .CLK(n14), .Q(dpll_state[1]) );
  fdf1c3 rx_valid_r_reg ( .D(n71), .CLK(n15), .QN(rx_valid_r) );
  fdf1a3 \one_cnt_reg[1]  ( .D(n86), .CLK(n16), .Q(one_cnt[1]) );
  fdf1c3 rx_valid_reg ( .D(n39), .CLK(n15), .QN(RxValid_o) );
  fdf1a3 rx_en_reg ( .D(RxEn_i), .CLK(n13), .Q(rx_en) );
  fdf1a3 \one_cnt_reg[2]  ( .D(n85), .CLK(n16), .Q(one_cnt[2]) );
  fdf1a3 rxdp_s1_reg ( .D(rxdp_s0), .CLK(n13), .Q(LineState[0]) );
  fdf1a3 rxdn_s1_reg ( .D(rxdn_s0), .CLK(n14), .Q(LineState[1]) );
  fdf1a3 rxdn_s_reg ( .D(N32), .CLK(n14), .Q(rxdn_s) );
  fdf1a3 \bit_cnt_reg[0]  ( .D(n84), .CLK(n16), .Q(bit_cnt[0]) );
  fdf1a3 shift_en_reg ( .D(n88), .CLK(n16), .Q(shift_en) );
  fdf1a3 sd_nrzi_reg ( .D(n92), .CLK(n15), .Q(sd_nrzi) );
  fdf1a3 \fs_state_reg[0]  ( .D(n91), .CLK(n15), .Q(fs_state[0]) );
  fdf1a3 \bit_cnt_reg[1]  ( .D(n83), .CLK(n16), .Q(bit_cnt[1]) );
  fdf1a3 \one_cnt_reg[0]  ( .D(n87), .CLK(n16), .Q(one_cnt[0]) );
  fdf1a3 \fs_state_reg[2]  ( .D(n89), .CLK(n15), .Q(fs_state[2]) );
  fdf1c3 rxd_s_reg ( .D(n72), .CLK(n13), .QN(rxd_s) );
  fdf1a9 fs_ce_reg ( .D(fs_ce_r2), .CLK(n14), .Q(fs_ce) );
  fdf1c3 fs_ce_r1_reg ( .D(n10), .CLK(n14), .QN(fs_ce_r1) );
  fdef1a3 \hold_reg_reg[0]  ( .D(DataIn_o[1]), .E(N129), .CLK(n17), .Q(
        DataIn_o[0]) );
  fdef1a3 \hold_reg_reg[7]  ( .D(sd_nrzi), .E(N129), .CLK(n16), .Q(DataIn_o[7]) );
  fdef1a3 \hold_reg_reg[6]  ( .D(DataIn_o[7]), .E(N129), .CLK(n17), .Q(
        DataIn_o[6]) );
  fdef1a3 \hold_reg_reg[5]  ( .D(DataIn_o[6]), .E(N129), .CLK(n17), .Q(
        DataIn_o[5]) );
  fdef1a3 \hold_reg_reg[4]  ( .D(DataIn_o[5]), .E(N129), .CLK(n17), .Q(
        DataIn_o[4]) );
  fdef1a3 \hold_reg_reg[3]  ( .D(DataIn_o[4]), .E(N129), .CLK(n17), .Q(
        DataIn_o[3]) );
  fdef1a3 \hold_reg_reg[2]  ( .D(DataIn_o[3]), .E(N129), .CLK(n17), .Q(
        DataIn_o[2]) );
  fdef1a3 \hold_reg_reg[1]  ( .D(DataIn_o[2]), .E(N129), .CLK(n17), .Q(
        DataIn_o[1]) );
  fdf1a3 fs_ce_r2_reg ( .D(fs_ce_r1), .CLK(n14), .Q(fs_ce_r2) );
  fdf1a3 rx_active_reg ( .D(n93), .CLK(n15), .Q(RxActive_o) );
  fdf1a3 \fs_state_reg[1]  ( .D(n90), .CLK(n15), .Q(fs_state[1]) );
  and3d3 U5 ( .A(n23), .B(rxdn_s), .C(n26), .Y(N50) );
  ao1d2 U6 ( .A(n34), .B(n35), .C(N84), .Y(n3) );
  inv1a1 U7 ( .A(n54), .Y(n32) );
  or3d1 U9 ( .A(n11), .B(fs_ce), .C(shift_en), .Y(n54) );
  or3d1 U14 ( .A(n11), .B(n54), .C(shift_en), .Y(n53) );
  or3d1 U15 ( .A(n11), .B(n43), .C(shift_en), .Y(n45) );
  or3d1 U16 ( .A(fs_state[2]), .B(fs_state[0]), .C(n69), .Y(n67) );
  inv1a1 U17 ( .A(one_cnt[0]), .Y(n96) );
  inv1a1 U18 ( .A(bit_cnt[0]), .Y(n98) );
  or2c1 U19 ( .A(rx_valid1), .B(n30), .Y(n39) );
  inv1a1 U20 ( .A(fs_ce), .Y(n29) );
  and2a3 U21 ( .A(n56), .B(n11), .Y(n58) );
  clk1b6 U22 ( .A(n12), .Y(n11) );
  clk1a3 U23 ( .A(n19), .Y(n17) );
  clk1a3 U25 ( .A(n20), .Y(n16) );
  clk1a3 U26 ( .A(n20), .Y(n15) );
  clk1a3 U28 ( .A(n21), .Y(n14) );
  clk1a3 U29 ( .A(n21), .Y(n13) );
  clk1a3 U30 ( .A(n19), .Y(n18) );
  or2c3 U31 ( .A(n32), .B(n46), .Y(n43) );
  inv1a3 U32 ( .A(N84), .Y(n24) );
  or2c3 U33 ( .A(n11), .B(n61), .Y(n56) );
  and2c3 U34 ( .A(n43), .B(n98), .Y(n42) );
  or2c1 U35 ( .A(n74), .B(n28), .Y(n75) );
  inv1a3 U36 ( .A(n52), .Y(n31) );
  inv1a3 U38 ( .A(se0), .Y(n27) );
  inv1a1 U39 ( .A(n67), .Y(n25) );
  inv1a1 U40 ( .A(n79), .Y(n30) );
  inv1a1 U41 ( .A(N50), .Y(n22) );
  inv1a3 U42 ( .A(rst), .Y(n12) );
  clk1a3 U43 ( .A(clk), .Y(n19) );
  clk1a3 U44 ( .A(clk), .Y(n20) );
  clk1a3 U45 ( .A(clk), .Y(n21) );
  and2c3 U46 ( .A(rxdn_s), .B(rxdp_s), .Y(se0) );
  or3d3 U47 ( .A(rx_en), .B(n26), .C(rxdn_s), .Y(N84) );
  or3d3 U48 ( .A(one_cnt[1]), .B(n96), .C(one_cnt[2]), .Y(n46) );
  ao1f2 U49 ( .A(one_cnt[0]), .B(n52), .C(n53), .Y(n50) );
  and2c3 U50 ( .A(n24), .B(n35), .Y(N80) );
  and2c3 U51 ( .A(n24), .B(n34), .Y(N81) );
  or3d3 U52 ( .A(fs_ce), .B(n27), .C(n77), .Y(n61) );
  and2c3 U53 ( .A(se0_s), .B(RxActive_o), .Y(n77) );
  ao1f2 U55 ( .A(bit_cnt[0]), .B(n43), .C(n45), .Y(n44) );
  or3d3 U56 ( .A(n32), .B(n46), .C(sd_nrzi), .Y(n52) );
  and2c1 U58 ( .A(N50), .B(n24), .Y(N87) );
  and3d2 U59 ( .A(n80), .B(n33), .C(n46), .Y(N127) );
  or3d1 U60 ( .A(fs_ce), .B(n27), .C(sd_nrzi), .Y(n80) );
  inv1a3 U61 ( .A(RxActive_o), .Y(n33) );
  or2c3 U62 ( .A(fs_ce), .B(n46), .Y(n79) );
  or2c3 U64 ( .A(rx_en), .B(n76), .Y(n74) );
  ao1f2 U65 ( .A(n33), .B(n65), .C(n66), .Y(n93) );
  or3d1 U66 ( .A(n11), .B(n65), .C(n25), .Y(n66) );
  or2c1 U67 ( .A(rx_valid_r), .B(se0), .Y(n68) );
  oa1f3 U68 ( .A(n70), .B(N84), .C(n61), .Y(n69) );
  or2c1 U69 ( .A(fs_state[1]), .B(n26), .Y(n70) );
  and2c1 U70 ( .A(n9), .B(n61), .Y(N25) );
  mx2a1 U72 ( .D0(n3), .D1(n4), .S(fs_state[0]), .Y(n9) );
  inv1a3 U73 ( .A(rxdp_s), .Y(n26) );
  inv1a3 U74 ( .A(dpll_state[0]), .Y(n28) );
  inv1a3 U76 ( .A(one_cnt[1]), .Y(n97) );
  inv1a3 U77 ( .A(fs_state[1]), .Y(n35) );
  inv1a3 U78 ( .A(fs_state[2]), .Y(n34) );
  ao1f2 U79 ( .A(n94), .B(n56), .C(n60), .Y(n91) );
  or3d1 U80 ( .A(n24), .B(n94), .C(n58), .Y(n60) );
  inv1a1 U81 ( .A(fs_state[0]), .Y(n94) );
  ao1f2 U82 ( .A(n35), .B(n56), .C(n59), .Y(n90) );
  or2c1 U83 ( .A(N89), .B(n58), .Y(n59) );
  mx3d2 U84 ( .D0(n7), .D1(N84), .D2(n8), .S0(fs_state[1]), .S1(fs_state[0]), 
        .Y(N89) );
  ao1f2 U85 ( .A(n34), .B(n56), .C(n57), .Y(n89) );
  or2c1 U87 ( .A(N90), .B(n58), .Y(n57) );
  mx3d2 U88 ( .D0(n5), .D1(N84), .D2(n6), .S0(fs_state[2]), .S1(fs_state[0]), 
        .Y(N90) );
  ao1f2 U89 ( .A(fs_ce), .B(n95), .C(n55), .Y(n88) );
  ao1f2 U90 ( .A(n25), .B(RxActive_o), .C(fs_ce), .Y(n55) );
  ao1f2 U91 ( .A(n36), .B(n37), .C(n38), .Y(n81) );
  or2c1 U92 ( .A(n11), .B(bit_cnt[2]), .Y(n37) );
  or3d1 U93 ( .A(n11), .B(n39), .C(rx_valid1), .Y(n38) );
  or3d1 U94 ( .A(bit_cnt[0]), .B(n30), .C(bit_cnt[1]), .Y(n36) );
  ao1f2 U95 ( .A(n62), .B(n12), .C(n63), .Y(n92) );
  or3d1 U96 ( .A(n11), .B(n29), .C(sd_nrzi), .Y(n63) );
  oa1f3 U97 ( .A(n64), .B(fs_ce), .C(n33), .Y(n62) );
  ao1f2 U98 ( .A(n40), .B(n100), .C(n41), .Y(n82) );
  or3d1 U99 ( .A(bit_cnt[1]), .B(n100), .C(n42), .Y(n41) );
  oa1d2 U100 ( .A(n43), .B(bit_cnt[1]), .C(n44), .Y(n40) );
  and2c1 U101 ( .A(one_cnt[2]), .B(n97), .Y(n49) );
  ao1f2 U102 ( .A(n47), .B(n101), .C(n48), .Y(n85) );
  inv1a1 U103 ( .A(one_cnt[2]), .Y(n101) );
  or3d1 U104 ( .A(one_cnt[0]), .B(n31), .C(n49), .Y(n48) );
  oa1f3 U105 ( .A(n31), .B(n97), .C(n50), .Y(n47) );
  inv1a3 U106 ( .A(bit_cnt[2]), .Y(n100) );
  oa1f3 U107 ( .A(n29), .B(rx_valid_r), .C(RxValid_o), .Y(n71) );
  inv1a3 U108 ( .A(shift_en), .Y(n95) );
  oa1f3 U109 ( .A(n10), .B(n73), .C(n12), .Y(N35) );
  or3d1 U110 ( .A(n74), .B(n28), .C(dpll_state[1]), .Y(n73) );
  or2a2 U111 ( .A(n28), .B(dpll_state[1]), .Y(n10) );
  inv1a3 U112 ( .A(rx_en), .Y(n23) );
  inv1a1 U113 ( .A(bit_cnt[1]), .Y(n99) );
  ao1d2 U114 ( .A(n50), .B(one_cnt[1]), .C(n51), .Y(n86) );
  or3d1 U115 ( .A(n31), .B(n97), .C(one_cnt[0]), .Y(n51) );
  and2a3 U117 ( .A(rxdn_s0), .B(LineState[1]), .Y(N31) );
  and2a3 U118 ( .A(rxdp_s0), .B(LineState[0]), .Y(N29) );
  or2a2 U119 ( .A(rxdn_s_r), .B(N31), .Y(N32) );
  or2a2 U120 ( .A(rxdp_s_r), .B(N29), .Y(N30) );
  oa2i2 U121 ( .A(n100), .B(n99), .C(n78), .D(se0_r), .Y(N150) );
  or2c1 U122 ( .A(se0), .B(RxActive_o), .Y(n78) );
endmodule


module usb_phy ( clk, rst, phy_tx_mode, usb_rst, txdp, txdn, txoe, rxd, rxdp, 
        rxdn, DataOut_i, TxValid_i, TxReady_o, RxValid_o, RxActive_o, 
        RxError_o, DataIn_o, LineState_o );
  input [7:0] DataOut_i;
  output [7:0] DataIn_o;
  output [1:0] LineState_o;
  input clk, rst, phy_tx_mode, rxd, rxdp, rxdn, TxValid_i;
  output usb_rst, txdp, txdn, txoe, TxReady_o, RxValid_o, RxActive_o,
         RxError_o;
  wire   fs_ce, N4, N5, N6, N7, N8, N23, n7, n8, n9, n10, n11, n12, n13, n14,
         n15, n16, n17, n18, n19, n20, n21, \add_185_S2/carry[4] ,
         \add_185_S2/carry[3] , \add_185_S2/carry[2] , n1, n2, n3, n4, n5, n6,
         n22, n23;
  wire   [4:0] rst_cnt;

  usb_tx_phy i_tx_phy ( .clk(n2), .rst(n1), .fs_ce(fs_ce), .phy_mode(
        phy_tx_mode), .txdp(txdp), .txdn(txdn), .txoe(txoe), .DataOut_i(
        DataOut_i), .TxValid_i(TxValid_i), .TxReady_o(TxReady_o) );
  usb_rx_phy i_rx_phy ( .clk(n2), .rst(n1), .fs_ce(fs_ce), .rxd(rxd), .rxdp(
        rxdp), .rxdn(rxdn), .RxValid_o(RxValid_o), .RxActive_o(RxActive_o), 
        .RxError_o(RxError_o), .DataIn_o(DataIn_o), .RxEn_i(txoe), .LineState(
        LineState_o) );
  ha1a2 \add_185_S2/U1_1_1  ( .A(rst_cnt[1]), .B(rst_cnt[0]), .CO(
        \add_185_S2/carry[2] ), .S(N5) );
  ha1a2 \add_185_S2/U1_1_2  ( .A(rst_cnt[2]), .B(\add_185_S2/carry[2] ), .CO(
        \add_185_S2/carry[3] ), .S(N6) );
  ha1a2 \add_185_S2/U1_1_3  ( .A(rst_cnt[3]), .B(\add_185_S2/carry[3] ), .CO(
        \add_185_S2/carry[4] ), .S(N7) );
  fdf1a3 \rst_cnt_reg[1]  ( .D(n20), .CLK(n2), .Q(rst_cnt[1]) );
  fdf1a3 \rst_cnt_reg[3]  ( .D(n18), .CLK(n2), .Q(rst_cnt[3]) );
  fdf1a3 \rst_cnt_reg[0]  ( .D(n21), .CLK(n2), .Q(rst_cnt[0]) );
  fdf1a3 \rst_cnt_reg[2]  ( .D(n19), .CLK(n2), .Q(rst_cnt[2]) );
  fdf1a3 \rst_cnt_reg[4]  ( .D(n17), .CLK(n2), .Q(rst_cnt[4]) );
  fdf1a3 usb_rst_reg ( .D(N23), .CLK(n2), .Q(usb_rst) );
  or3d1 U3 ( .A(n1), .B(fs_ce), .C(n15), .Y(n13) );
  inv1a1 U4 ( .A(rst_cnt[0]), .Y(n4) );
  inv1a1 U5 ( .A(rst_cnt[1]), .Y(n5) );
  inv1a3 U6 ( .A(n13), .Y(n3) );
  ao1f2 U7 ( .A(n7), .B(n5), .C(n11), .Y(n20) );
  or2c1 U8 ( .A(N5), .B(n3), .Y(n11) );
  or3d3 U9 ( .A(n1), .B(n13), .C(n14), .Y(n7) );
  and2c3 U10 ( .A(LineState_o[1]), .B(LineState_o[0]), .Y(n14) );
  ao1f2 U11 ( .A(n7), .B(n23), .C(n8), .Y(n17) );
  inv1a1 U12 ( .A(rst_cnt[4]), .Y(n23) );
  or2c1 U13 ( .A(N8), .B(n3), .Y(n8) );
  ao1f2 U14 ( .A(n7), .B(n22), .C(n9), .Y(n18) );
  inv1a1 U15 ( .A(rst_cnt[3]), .Y(n22) );
  or2c1 U16 ( .A(N7), .B(n3), .Y(n9) );
  ao1f2 U17 ( .A(n7), .B(n6), .C(n10), .Y(n19) );
  inv1a1 U18 ( .A(rst_cnt[2]), .Y(n6) );
  or2c1 U19 ( .A(N6), .B(n3), .Y(n10) );
  ao1f2 U20 ( .A(n7), .B(n4), .C(n12), .Y(n21) );
  or2c1 U21 ( .A(N4), .B(n3), .Y(n12) );
  inv1a1 U22 ( .A(rst_cnt[0]), .Y(N4) );
  and3d2 U23 ( .A(LineState_o[0]), .B(usb_rst), .C(LineState_o[1]), .Y(n15) );
  and3d2 U24 ( .A(n16), .B(n5), .C(n4), .Y(N23) );
  or3d1 U25 ( .A(rst_cnt[3]), .B(rst_cnt[4]), .C(rst_cnt[2]), .Y(n16) );
  clk1a6 U26 ( .A(clk), .Y(n2) );
  clk1a3 U27 ( .A(rst), .Y(n1) );
  xor2a1 U28 ( .A(\add_185_S2/carry[4] ), .B(rst_cnt[4]), .Y(N8) );
endmodule


module usb1_utmi_if ( phy_clk, rst, DataOut, TxValid, TxReady, RxValid, 
        RxActive, RxError, DataIn, rx_data, rx_valid, rx_active, rx_err, 
        tx_data, tx_valid, tx_valid_last, tx_ready, tx_first );
  output [7:0] DataOut;
  input [7:0] DataIn;
  output [7:0] rx_data;
  input [7:0] tx_data;
  input phy_clk, rst, TxReady, RxValid, RxActive, RxError, tx_valid,
         tx_valid_last, tx_first;
  output TxValid, rx_valid, rx_active, rx_err, tx_ready;
  wire   N1, N2, n1, n2, n3, n4, n5;

  fdf1a6 \rx_data_reg[7]  ( .D(DataIn[7]), .CLK(n2), .Q(rx_data[7]) );
  fdf1a6 \rx_data_reg[6]  ( .D(DataIn[6]), .CLK(n2), .Q(rx_data[6]) );
  fdf1a6 \rx_data_reg[5]  ( .D(DataIn[5]), .CLK(n2), .Q(rx_data[5]) );
  fdf1a6 \rx_data_reg[4]  ( .D(DataIn[4]), .CLK(n2), .Q(rx_data[4]) );
  fdf1a6 \rx_data_reg[3]  ( .D(DataIn[3]), .CLK(n2), .Q(rx_data[3]) );
  fdf1a6 \rx_data_reg[2]  ( .D(DataIn[2]), .CLK(n2), .Q(rx_data[2]) );
  fdf1a6 \rx_data_reg[1]  ( .D(DataIn[1]), .CLK(n3), .Q(rx_data[1]) );
  fdf1a6 \rx_data_reg[0]  ( .D(DataIn[0]), .CLK(n3), .Q(rx_data[0]) );
  fdef1a3 \DataOut_reg[0]  ( .D(tx_data[0]), .E(N1), .CLK(n4), .Q(DataOut[0])
         );
  fdef1a3 \DataOut_reg[7]  ( .D(tx_data[7]), .E(N1), .CLK(n3), .Q(DataOut[7])
         );
  fdef1a3 \DataOut_reg[6]  ( .D(tx_data[6]), .E(N1), .CLK(n3), .Q(DataOut[6])
         );
  fdef1a3 \DataOut_reg[5]  ( .D(tx_data[5]), .E(N1), .CLK(n3), .Q(DataOut[5])
         );
  fdef1a3 \DataOut_reg[4]  ( .D(tx_data[4]), .E(N1), .CLK(n3), .Q(DataOut[4])
         );
  fdef1a3 \DataOut_reg[3]  ( .D(tx_data[3]), .E(N1), .CLK(n3), .Q(DataOut[3])
         );
  fdef1a3 \DataOut_reg[2]  ( .D(tx_data[2]), .E(N1), .CLK(n3), .Q(DataOut[2])
         );
  fdef1a3 \DataOut_reg[1]  ( .D(tx_data[1]), .E(N1), .CLK(n3), .Q(DataOut[1])
         );
  fdf2a3 rx_valid_reg ( .D(RxValid), .CLK(n2), .CLR(n1), .Q(rx_valid) );
  fdf2a3 rx_err_reg ( .D(RxError), .CLK(n2), .CLR(n1), .Q(rx_err) );
  fdf2a3 TxValid_reg ( .D(N2), .CLK(n4), .CLR(n1), .Q(TxValid) );
  fdf2a6 rx_active_reg ( .D(RxActive), .CLK(n2), .CLR(n1), .Q(rx_active) );
  fdf1c3 tx_ready_reg ( .D(n5), .CLK(n4), .QN(tx_ready) );
  or2a6 U3 ( .A(tx_first), .B(TxReady), .Y(N1) );
  clk1a3 U4 ( .A(phy_clk), .Y(n3) );
  clk1a3 U5 ( .A(phy_clk), .Y(n2) );
  clk1a3 U6 ( .A(phy_clk), .Y(n4) );
  ao2a2 U7 ( .A(TxValid), .B(n5), .C(tx_valid_last), .D(tx_valid), .Y(N2) );
  inv1a1 U8 ( .A(TxReady), .Y(n5) );
  clk1a3 U9 ( .A(rst), .Y(n1) );
endmodule


module usb1_crc5 ( crc_in, din, crc_out );
  input [4:0] crc_in;
  input [10:0] din;
  output [4:0] crc_out;
  wire   n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n1, n2;

  xor3b3 U1 ( .A(n3), .B(n4), .C(n5), .Y(crc_out[4]) );
  xor3b3 U2 ( .A(n1), .B(din[4]), .C(din[2]), .Y(n4) );
  xor3b3 U3 ( .A(din[3]), .B(n6), .C(n7), .Y(crc_out[3]) );
  xor3b3 U4 ( .A(n2), .B(n8), .C(n7), .Y(crc_out[2]) );
  xor3b3 U5 ( .A(n9), .B(n3), .C(n5), .Y(n7) );
  xor2a2 U6 ( .A(din[8]), .B(crc_in[2]), .Y(n3) );
  xor3b3 U7 ( .A(n6), .B(n10), .C(n11), .Y(crc_out[1]) );
  xor2a2 U8 ( .A(n9), .B(n12), .Y(n11) );
  xor2b2 U9 ( .A(din[7]), .B(crc_in[1]), .Y(n9) );
  xor2a2 U10 ( .A(din[4]), .B(din[1]), .Y(n6) );
  xor3b3 U11 ( .A(n1), .B(n5), .C(n8), .Y(crc_out[0]) );
  xor3b3 U12 ( .A(din[3]), .B(din[0]), .C(n10), .Y(n8) );
  xor2a2 U13 ( .A(din[6]), .B(crc_in[0]), .Y(n10) );
  xor3b3 U14 ( .A(din[9]), .B(crc_in[3]), .C(n12), .Y(n5) );
  xor2a2 U15 ( .A(din[10]), .B(crc_in[4]), .Y(n12) );
  inv1a1 U16 ( .A(din[2]), .Y(n2) );
  inv1a3 U17 ( .A(din[5]), .Y(n1) );
endmodule


module usb1_crc16_0 ( crc_in, din, crc_out );
  input [15:0] crc_in;
  input [7:0] din;
  output [15:0] crc_out;
  wire   crc_in_1, crc_in_0, \crc_in[6] , \crc_in[5] , \crc_in[4] ,
         \crc_in[3] , \crc_in[2] , n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
         n2;
  assign crc_in_1 = crc_in[1];
  assign crc_in_0 = crc_in[0];
  assign crc_out[14] = \crc_in[6] ;
  assign \crc_in[6]  = crc_in[6];
  assign crc_out[13] = \crc_in[5] ;
  assign \crc_in[5]  = crc_in[5];
  assign crc_out[12] = \crc_in[4] ;
  assign \crc_in[4]  = crc_in[4];
  assign crc_out[11] = \crc_in[3] ;
  assign \crc_in[3]  = crc_in[3];
  assign crc_out[10] = \crc_in[2] ;
  assign \crc_in[2]  = crc_in[2];

  xor2a2 U1 ( .A(crc_in_1), .B(n3), .Y(crc_out[9]) );
  xor2a2 U2 ( .A(crc_in_0), .B(n4), .Y(crc_out[8]) );
  xor2b2 U3 ( .A(n5), .B(n6), .Y(crc_out[7]) );
  xor2b2 U4 ( .A(n7), .B(n8), .Y(crc_out[5]) );
  xor2b2 U5 ( .A(n9), .B(n10), .Y(crc_out[3]) );
  xor3b3 U6 ( .A(n2), .B(n10), .C(n11), .Y(crc_out[1]) );
  xor2a2 U7 ( .A(crc_in[7]), .B(crc_out[0]), .Y(crc_out[15]) );
  xor3b3 U8 ( .A(n2), .B(crc_out[2]), .C(n11), .Y(crc_out[0]) );
  xor2a2 U9 ( .A(crc_out[6]), .B(n4), .Y(n11) );
  xor2b2 U10 ( .A(n5), .B(n3), .Y(n4) );
  xor2a2 U11 ( .A(din[7]), .B(crc_in[15]), .Y(n3) );
  xor2b2 U12 ( .A(din[6]), .B(crc_in[14]), .Y(n5) );
  xor2b2 U13 ( .A(n7), .B(n6), .Y(crc_out[6]) );
  xor2a2 U14 ( .A(din[5]), .B(crc_in[13]), .Y(n6) );
  xor2b2 U15 ( .A(din[4]), .B(crc_in[12]), .Y(n7) );
  xor3b3 U16 ( .A(din[0]), .B(crc_in[8]), .C(n10), .Y(n12) );
  xor2a2 U17 ( .A(din[1]), .B(crc_in[9]), .Y(n10) );
  xor2b2 U18 ( .A(n9), .B(n8), .Y(crc_out[4]) );
  xor2a2 U19 ( .A(din[3]), .B(crc_in[11]), .Y(n8) );
  xor2b2 U20 ( .A(din[2]), .B(crc_in[10]), .Y(n9) );
  inv1a1 U21 ( .A(n12), .Y(crc_out[2]) );
  inv1a3 U22 ( .A(crc_out[4]), .Y(n2) );
endmodule


module usb1_pd ( clk, rst, rx_data, rx_valid, rx_active, rx_err, pid_OUT, 
        pid_IN, pid_SOF, pid_SETUP, pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, 
        pid_ACK, pid_NACK, pid_STALL, pid_NYET, pid_PRE, pid_ERR, pid_SPLIT, 
        pid_PING, pid_cks_err, token_fadr, token_endp, token_valid, crc5_err, 
        frame_no, rx_data_st, rx_data_valid, rx_data_done, crc16_err, seq_err, 
        rx_busy );
  input [7:0] rx_data;
  output [6:0] token_fadr;
  output [3:0] token_endp;
  output [10:0] frame_no;
  output [7:0] rx_data_st;
  input clk, rst, rx_valid, rx_active, rx_err;
  output pid_OUT, pid_IN, pid_SOF, pid_SETUP, pid_DATA0, pid_DATA1, pid_DATA2,
         pid_MDATA, pid_ACK, pid_NACK, pid_STALL, pid_NYET, pid_PRE, pid_ERR,
         pid_SPLIT, pid_PING, pid_cks_err, token_valid, crc5_err,
         rx_data_valid, rx_data_done, crc16_err, seq_err, rx_busy;
  wire   \token_endp[3] , \token_endp[2] , \token_endp[1] , \token_endp[0] ,
         \token_fadr[6] , \token_fadr[5] , \token_fadr[4] , \token_fadr[3] ,
         \token_fadr[2] , \token_fadr[1] , \token_fadr[0] , rx_busy_d,
         pid_ld_en, token_le_2, token_valid_r1, rxv1, rxv2, N39, rx_active_r,
         N179, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
         n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
         n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
         n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
         n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
         n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
         n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
         n126, n127, n128, n129, n130, n131, pid_PRE, n1, n2, n3, n4, n5, n6,
         n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
         n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n35,
         n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
         n143, n144, n145, n146, n147;
  wire   [3:0] state;
  wire   [7:0] pid;
  wire   [7:3] token1;
  wire   [4:0] crc5_out;
  wire   [7:0] d0;
  wire   [7:0] d1;
  wire   [15:0] crc16_sum;
  wire   [15:0] crc16_out;
  assign frame_no[10] = \token_endp[3] ;
  assign token_endp[3] = \token_endp[3] ;
  assign frame_no[9] = \token_endp[2] ;
  assign token_endp[2] = \token_endp[2] ;
  assign frame_no[8] = \token_endp[1] ;
  assign token_endp[1] = \token_endp[1] ;
  assign frame_no[7] = \token_endp[0] ;
  assign token_endp[0] = \token_endp[0] ;
  assign frame_no[6] = \token_fadr[6] ;
  assign token_fadr[6] = \token_fadr[6] ;
  assign frame_no[5] = \token_fadr[5] ;
  assign token_fadr[5] = \token_fadr[5] ;
  assign frame_no[4] = \token_fadr[4] ;
  assign token_fadr[4] = \token_fadr[4] ;
  assign frame_no[3] = \token_fadr[3] ;
  assign token_fadr[3] = \token_fadr[3] ;
  assign frame_no[2] = \token_fadr[2] ;
  assign token_fadr[2] = \token_fadr[2] ;
  assign frame_no[1] = \token_fadr[1] ;
  assign token_fadr[1] = \token_fadr[1] ;
  assign frame_no[0] = \token_fadr[0] ;
  assign token_fadr[0] = \token_fadr[0] ;
  assign pid_MDATA = N179;
  assign pid_ERR = pid_PRE;

  xor2b2 U12 ( .A(pid[3]), .B(pid[7]), .Y(n43) );
  xor2b2 U13 ( .A(pid[0]), .B(pid[4]), .Y(n42) );
  xor2b2 U14 ( .A(pid[5]), .B(n29), .Y(n40) );
  xor2b2 U15 ( .A(pid[6]), .B(n30), .Y(n39) );
  ao2i3 U22 ( .A(n2), .B(n138), .C(n50), .D(n51), .Y(n113) );
  ao2i3 U24 ( .A(n2), .B(n137), .C(n52), .D(n51), .Y(n114) );
  ao2i3 U30 ( .A(n2), .B(n136), .C(n55), .D(n51), .Y(n117) );
  ao2i3 U32 ( .A(n2), .B(n135), .C(n56), .D(n51), .Y(n118) );
  ao2i3 U38 ( .A(n2), .B(n134), .C(n59), .D(n51), .Y(n121) );
  ao2i3 U40 ( .A(n2), .B(n133), .C(n60), .D(n51), .Y(n122) );
  ao2i3 U46 ( .A(n3), .B(n132), .C(n63), .D(n51), .Y(n125) );
  ao2i3 U50 ( .A(n3), .B(n35), .C(n65), .D(n51), .Y(n127) );
  ao4f3 U55 ( .A(n67), .B(n68), .C(n69), .D(n33), .Y(n129) );
  or2b2 U56 ( .B(n70), .A(state[1]), .Y(n67) );
  ao2i3 U57 ( .A(n21), .B(n68), .C(n71), .D(n72), .Y(n130) );
  ao4b3 U59 ( .C(n73), .D(state[1]), .B(state[3]), .A(n69), .Y(n131) );
  and2b2 U60 ( .B(n72), .A(n68), .Y(n69) );
  ao4f3 U62 ( .A(n73), .B(n75), .C(n143), .D(n37), .Y(n74) );
  oa4f3 U70 ( .A(state[2]), .B(n87), .C(state[3]), .D(rx_active), .Y(n86) );
  ao4f3 U71 ( .A(n38), .B(n143), .C(n82), .D(n142), .Y(n87) );
  and2b2 U91 ( .B(token_valid), .A(n93), .Y(crc5_err) );
  xor2b2 U93 ( .A(token1[3]), .B(crc5_out[4]), .Y(n96) );
  xor2b2 U94 ( .A(token1[5]), .B(crc5_out[2]), .Y(n95) );
  xor2a2 U96 ( .A(token1[6]), .B(crc5_out[1]), .Y(n99) );
  xor2a2 U97 ( .A(token1[4]), .B(crc5_out[3]), .Y(n98) );
  xor2a2 U98 ( .A(token1[7]), .B(crc5_out[0]), .Y(n97) );
  oa4f3 U112 ( .A(n82), .B(state[3]), .C(state[1]), .D(n73), .Y(n48) );
  and2b2 U117 ( .B(pid_ACK), .A(rx_err), .Y(n79) );
  usb1_crc5 u0 ( .crc_in({1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .din({
        \token_fadr[0] , \token_fadr[1] , \token_fadr[2] , \token_fadr[3] , 
        \token_fadr[4] , \token_fadr[5] , \token_fadr[6] , \token_endp[0] , 
        \token_endp[1] , \token_endp[2] , \token_endp[3] }), .crc_out(crc5_out) );
  usb1_crc16_0 u1 ( .crc_in(crc16_sum), .din({rx_data[0], rx_data[1], 
        rx_data[2], rx_data[3], rx_data[4], rx_data[5], rx_data[6], rx_data[7]}), .crc_out(crc16_out) );
  fdef2c3 \pid_reg[4]  ( .D(n147), .E(pid_ld_en), .CLK(n7), .CLR(n5), .QN(
        pid[4]) );
  fdef2c3 \pid_reg[7]  ( .D(n144), .E(pid_ld_en), .CLK(n8), .CLR(n5), .QN(
        pid[7]) );
  fdef1a3 \token1_reg[3]  ( .D(rx_data[3]), .E(token_le_2), .CLK(n9), .Q(
        token1[3]) );
  fdef1a3 \token1_reg[4]  ( .D(rx_data[4]), .E(token_le_2), .CLK(n9), .Q(
        token1[4]) );
  fdef1a3 \token1_reg[5]  ( .D(rx_data[5]), .E(token_le_2), .CLK(n10), .Q(
        token1[5]) );
  fdef1a3 \token1_reg[6]  ( .D(rx_data[6]), .E(token_le_2), .CLK(n10), .Q(
        token1[6]) );
  fdef1a3 \token1_reg[7]  ( .D(rx_data[7]), .E(token_le_2), .CLK(n10), .Q(
        token1[7]) );
  fdef2c3 \pid_reg[5]  ( .D(n146), .E(pid_ld_en), .CLK(n7), .CLR(n5), .QN(
        pid[5]) );
  fdef2c3 \pid_reg[6]  ( .D(n145), .E(pid_ld_en), .CLK(n7), .CLR(n5), .QN(
        pid[6]) );
  fdef2a3 rxv2_reg ( .D(n1), .E(n27), .CLK(n12), .CLR(n5), .Q(rxv2) );
  fdf1a3 rx_busy_reg ( .D(rx_busy_d), .CLK(n10), .Q(rx_busy) );
  fdf1a3 token_valid_r1_reg ( .D(token_le_2), .CLK(n9), .Q(token_valid_r1) );
  fdf2a3 rx_busy_d_reg ( .D(n111), .CLK(n10), .CLR(n6), .Q(rx_busy_d) );
  fdf2a3 rxv1_reg ( .D(n112), .CLK(n12), .CLR(n6), .Q(rxv1) );
  fdef2c3 \state_reg[0]  ( .D(n76), .E(n22), .CLK(n7), .CLR(n5), .QN(state[0])
         );
  fdf1a3 data_valid0_reg ( .D(N39), .CLK(n15), .Q(rx_data_valid) );
  fdef1a3 \token0_reg[5]  ( .D(rx_data[5]), .E(n24), .CLK(n8), .Q(
        \token_fadr[5] ) );
  fdef1a3 \token0_reg[4]  ( .D(rx_data[4]), .E(n24), .CLK(n8), .Q(
        \token_fadr[4] ) );
  fdef1a3 \token0_reg[3]  ( .D(rx_data[3]), .E(n24), .CLK(n8), .Q(
        \token_fadr[3] ) );
  fdef1a3 \token0_reg[2]  ( .D(rx_data[2]), .E(n24), .CLK(n8), .Q(
        \token_fadr[2] ) );
  fdef1a3 \token0_reg[0]  ( .D(rx_data[0]), .E(n24), .CLK(n9), .Q(
        \token_fadr[0] ) );
  fdef2a3 \pid_reg[0]  ( .D(rx_data[0]), .E(pid_ld_en), .CLK(n7), .CLR(n5), 
        .Q(pid[0]) );
  fdef2a3 \pid_reg[2]  ( .D(rx_data[2]), .E(pid_ld_en), .CLK(n7), .CLR(n5), 
        .Q(pid[2]) );
  fdef1a3 \token0_reg[1]  ( .D(rx_data[1]), .E(n24), .CLK(n8), .Q(
        \token_fadr[1] ) );
  fdf1c3 rx_active_r_reg ( .D(n143), .CLK(n7), .QN(rx_active_r) );
  fdef1a3 \token0_reg[6]  ( .D(rx_data[6]), .E(n24), .CLK(n8), .Q(
        \token_fadr[6] ) );
  fdf1a3 \crc16_sum_reg[10]  ( .D(n118), .CLK(n11), .Q(crc16_sum[10]) );
  fdf1a3 \crc16_sum_reg[11]  ( .D(n117), .CLK(n11), .Q(crc16_sum[11]) );
  fdf1a3 \crc16_sum_reg[14]  ( .D(n114), .CLK(n12), .Q(crc16_sum[14]) );
  fdf1a3 \crc16_sum_reg[15]  ( .D(n113), .CLK(n12), .Q(crc16_sum[15]) );
  fdef2a3 \pid_reg[3]  ( .D(rx_data[3]), .E(pid_ld_en), .CLK(n7), .CLR(n5), 
        .Q(pid[3]) );
  fdf1a3 \crc16_sum_reg[3]  ( .D(n125), .CLK(n11), .Q(crc16_sum[3]) );
  fdf1a3 \crc16_sum_reg[6]  ( .D(n122), .CLK(n11), .Q(crc16_sum[6]) );
  fdf1a3 \crc16_sum_reg[1]  ( .D(n127), .CLK(n10), .Q(crc16_sum[1]) );
  fdf1a3 \crc16_sum_reg[7]  ( .D(n121), .CLK(n11), .Q(crc16_sum[7]) );
  fdf2a3 \state_reg[2]  ( .D(n129), .CLK(n9), .CLR(n5), .Q(state[2]) );
  fdf1a3 \crc16_sum_reg[9]  ( .D(n119), .CLK(n11), .Q(crc16_sum[9]) );
  fdf1a3 \crc16_sum_reg[12]  ( .D(n116), .CLK(n12), .Q(crc16_sum[12]) );
  fdf1a3 \crc16_sum_reg[13]  ( .D(n115), .CLK(n12), .Q(crc16_sum[13]) );
  fdf1a3 \crc16_sum_reg[8]  ( .D(n120), .CLK(n11), .Q(crc16_sum[8]) );
  fdf1a3 \crc16_sum_reg[0]  ( .D(n128), .CLK(n10), .Q(crc16_sum[0]) );
  fdf1a3 \crc16_sum_reg[2]  ( .D(n126), .CLK(n10), .Q(crc16_sum[2]) );
  fdf1a3 \crc16_sum_reg[4]  ( .D(n124), .CLK(n11), .Q(crc16_sum[4]) );
  fdf1a3 \crc16_sum_reg[5]  ( .D(n123), .CLK(n11), .Q(crc16_sum[5]) );
  fdef1a6 \token1_reg[2]  ( .D(rx_data[2]), .E(token_le_2), .CLK(n9), .Q(
        \token_endp[3] ) );
  fdf2a6 \state_reg[1]  ( .D(n130), .CLK(n8), .CLR(n5), .Q(state[1]) );
  fdf1c3 token_valid_str1_reg ( .D(n110), .CLK(n9), .QN(token_valid) );
  fdf2a3 \state_reg[3]  ( .D(n131), .CLK(n10), .CLR(n6), .Q(state[3]) );
  fdef2a3 \pid_reg[1]  ( .D(rx_data[1]), .E(pid_ld_en), .CLK(n7), .CLR(n5), 
        .Q(pid[1]) );
  fdef1a3 \d2_reg[0]  ( .D(d1[0]), .E(n3), .CLK(n15), .Q(rx_data_st[0]) );
  fdef1a3 \d2_reg[7]  ( .D(d1[7]), .E(n4), .CLK(n12), .Q(rx_data_st[7]) );
  fdef1a3 \d2_reg[6]  ( .D(d1[6]), .E(n4), .CLK(n13), .Q(rx_data_st[6]) );
  fdef1a3 \d2_reg[5]  ( .D(d1[5]), .E(n4), .CLK(n13), .Q(rx_data_st[5]) );
  fdef1a3 \d2_reg[4]  ( .D(d1[4]), .E(n3), .CLK(n13), .Q(rx_data_st[4]) );
  fdef1a3 \d2_reg[3]  ( .D(d1[3]), .E(n3), .CLK(n14), .Q(rx_data_st[3]) );
  fdef1a3 \d2_reg[2]  ( .D(d1[2]), .E(n3), .CLK(n14), .Q(rx_data_st[2]) );
  fdef1a3 \d2_reg[1]  ( .D(d1[1]), .E(n3), .CLK(n14), .Q(rx_data_st[1]) );
  fdef1a3 \d0_reg[0]  ( .D(rx_data[0]), .E(n3), .CLK(n15), .Q(d0[0]) );
  fdef1a3 \d1_reg[0]  ( .D(d0[0]), .E(n3), .CLK(n15), .Q(d1[0]) );
  fdef1a3 \d0_reg[7]  ( .D(rx_data[7]), .E(n2), .CLK(n12), .Q(d0[7]) );
  fdef1a3 \d1_reg[7]  ( .D(d0[7]), .E(n4), .CLK(n12), .Q(d1[7]) );
  fdef1a3 \d0_reg[6]  ( .D(rx_data[6]), .E(n4), .CLK(n13), .Q(d0[6]) );
  fdef1a3 \d1_reg[6]  ( .D(d0[6]), .E(n4), .CLK(n13), .Q(d1[6]) );
  fdef1a3 \d0_reg[5]  ( .D(rx_data[5]), .E(n4), .CLK(n13), .Q(d0[5]) );
  fdef1a3 \d1_reg[5]  ( .D(d0[5]), .E(n4), .CLK(n13), .Q(d1[5]) );
  fdef1a3 \d0_reg[4]  ( .D(rx_data[4]), .E(n3), .CLK(n13), .Q(d0[4]) );
  fdef1a3 \d1_reg[4]  ( .D(d0[4]), .E(n3), .CLK(n13), .Q(d1[4]) );
  fdef1a3 \d0_reg[3]  ( .D(rx_data[3]), .E(n3), .CLK(n14), .Q(d0[3]) );
  fdef1a3 \d1_reg[3]  ( .D(d0[3]), .E(n3), .CLK(n14), .Q(d1[3]) );
  fdef1a3 \d0_reg[2]  ( .D(rx_data[2]), .E(n3), .CLK(n14), .Q(d0[2]) );
  fdef1a3 \d1_reg[2]  ( .D(d0[2]), .E(n3), .CLK(n14), .Q(d1[2]) );
  fdef1a3 \d0_reg[1]  ( .D(rx_data[1]), .E(n3), .CLK(n14), .Q(d0[1]) );
  fdef1a3 \d1_reg[1]  ( .D(d0[1]), .E(n3), .CLK(n14), .Q(d1[1]) );
  fdef1a9 \token0_reg[7]  ( .D(rx_data[7]), .E(n24), .CLK(n8), .Q(
        \token_endp[0] ) );
  fdef1a9 \token1_reg[0]  ( .D(rx_data[0]), .E(token_le_2), .CLK(n9), .Q(
        \token_endp[1] ) );
  fdef1a9 \token1_reg[1]  ( .D(rx_data[1]), .E(token_le_2), .CLK(n9), .Q(
        \token_endp[2] ) );
  or2c3 U3 ( .A(pid[0]), .B(pid[1]), .Y(n78) );
  and3d9 U4 ( .A(n21), .B(n143), .C(n141), .Y(pid_ld_en) );
  inv1a1 U5 ( .A(pid[1]), .Y(n29) );
  inv1a1 U6 ( .A(pid[3]), .Y(n31) );
  and2c1 U7 ( .A(n42), .B(n43), .Y(n41) );
  and2c1 U8 ( .A(crc16_sum[13]), .B(crc16_sum[12]), .Y(n109) );
  inv1a1 U9 ( .A(crc16_sum[1]), .Y(n35) );
  inv1a1 U10 ( .A(crc16_sum[7]), .Y(n134) );
  inv1a1 U11 ( .A(crc16_sum[15]), .Y(n138) );
  inv1a1 U16 ( .A(crc16_sum[14]), .Y(n137) );
  inv1a1 U17 ( .A(crc16_sum[11]), .Y(n136) );
  inv1a1 U18 ( .A(crc16_sum[10]), .Y(n135) );
  inv1a1 U19 ( .A(crc16_sum[3]), .Y(n132) );
  inv1a1 U20 ( .A(crc16_sum[6]), .Y(n133) );
  clk1a3 U21 ( .A(n16), .Y(n14) );
  clk1a3 U23 ( .A(n17), .Y(n13) );
  clk1a3 U25 ( .A(n17), .Y(n12) );
  clk1a3 U26 ( .A(n18), .Y(n11) );
  clk1a3 U27 ( .A(n18), .Y(n10) );
  clk1a3 U28 ( .A(n19), .Y(n9) );
  clk1a3 U29 ( .A(n19), .Y(n8) );
  clk1a3 U31 ( .A(n16), .Y(n15) );
  and2c3 U33 ( .A(n89), .B(n23), .Y(pid_OUT) );
  inv1a3 U34 ( .A(n82), .Y(n140) );
  clk1a6 U35 ( .A(n28), .Y(n1) );
  buf1a9 U36 ( .A(n28), .Y(n3) );
  buf1a9 U37 ( .A(n28), .Y(n2) );
  clk1a6 U39 ( .A(n28), .Y(n4) );
  clk1a3 U41 ( .A(n20), .Y(n7) );
  clk1a3 U42 ( .A(clk), .Y(n20) );
  clk1a3 U43 ( .A(clk), .Y(n16) );
  clk1a3 U44 ( .A(clk), .Y(n17) );
  clk1a3 U45 ( .A(clk), .Y(n18) );
  clk1a3 U47 ( .A(clk), .Y(n19) );
  and2c3 U48 ( .A(n141), .B(n142), .Y(n82) );
  and2c3 U49 ( .A(n23), .B(n91), .Y(pid_SETUP) );
  and2c3 U51 ( .A(n23), .B(n92), .Y(pid_IN) );
  and2c6 U52 ( .A(n140), .B(n33), .Y(token_le_2) );
  and2c3 U53 ( .A(n90), .B(n89), .Y(pid_ACK) );
  and2c3 U54 ( .A(n91), .B(n88), .Y(pid_PRE) );
  and2c3 U58 ( .A(n78), .B(n140), .Y(n73) );
  and2c3 U61 ( .A(n78), .B(n92), .Y(pid_DATA1) );
  and2c3 U63 ( .A(n90), .B(n92), .Y(pid_NACK) );
  and2c3 U64 ( .A(n88), .B(n92), .Y(pid_SPLIT) );
  and2c3 U65 ( .A(n90), .B(n91), .Y(pid_STALL) );
  and2c3 U66 ( .A(n83), .B(n88), .Y(pid_PING) );
  inv1a3 U67 ( .A(n49), .Y(rx_data_done) );
  and2c3 U68 ( .A(n89), .B(n78), .Y(pid_DATA0) );
  inv1a3 U69 ( .A(n81), .Y(n23) );
  oa1f3 U72 ( .A(n100), .B(n101), .C(n49), .Y(crc16_err) );
  and2c3 U73 ( .A(n106), .B(n107), .Y(n100) );
  and2c3 U74 ( .A(n102), .B(n103), .Y(n101) );
  or3d1 U75 ( .A(n135), .B(n136), .C(n109), .Y(n106) );
  or2c1 U76 ( .A(crc16_out[3]), .B(n1), .Y(n63) );
  or2c1 U77 ( .A(crc16_out[1]), .B(n1), .Y(n65) );
  or2c1 U78 ( .A(crc16_out[7]), .B(n2), .Y(n59) );
  or2c1 U79 ( .A(crc16_out[6]), .B(n2), .Y(n60) );
  or3d3 U80 ( .A(n70), .B(n25), .C(n75), .Y(n37) );
  inv1a1 U81 ( .A(n79), .Y(n25) );
  and2c3 U82 ( .A(n83), .B(n78), .Y(pid_DATA2) );
  inv1a3 U83 ( .A(n48), .Y(n28) );
  or2c3 U84 ( .A(n30), .B(n31), .Y(n89) );
  or2c3 U85 ( .A(n26), .B(n29), .Y(n88) );
  and2c3 U86 ( .A(n83), .B(n23), .Y(pid_SOF) );
  and2c1 U87 ( .A(n90), .B(n83), .Y(pid_NYET) );
  inv1a3 U88 ( .A(n38), .Y(n142) );
  and2c3 U89 ( .A(n78), .B(n91), .Y(N179) );
  inv1a1 U90 ( .A(n68), .Y(n22) );
  buf1a9 U92 ( .A(rst), .Y(n5) );
  or3d1 U95 ( .A(n39), .B(n40), .C(n41), .Y(pid_cks_err) );
  and2c1 U99 ( .A(rx_err), .B(n36), .Y(seq_err) );
  clk1a3 U100 ( .A(rst), .Y(n6) );
  and2c3 U101 ( .A(n143), .B(rx_err), .Y(n38) );
  or3d3 U102 ( .A(n84), .B(n85), .C(n86), .Y(n68) );
  or3d1 U103 ( .A(state[1]), .B(rx_active), .C(n79), .Y(n85) );
  ao1f2 U104 ( .A(n143), .B(n141), .C(state[0]), .Y(n84) );
  or2c1 U105 ( .A(state[1]), .B(n68), .Y(n71) );
  or2c3 U106 ( .A(pid[2]), .B(n31), .Y(n83) );
  and2c3 U107 ( .A(n26), .B(pid[1]), .Y(n81) );
  or2c3 U108 ( .A(pid[1]), .B(n26), .Y(n90) );
  or2c3 U109 ( .A(pid[3]), .B(n30), .Y(n92) );
  ao2h2 U110 ( .B(crc16_sum[5]), .A(n2), .C(n61), .D(n51), .Y(n123) );
  or2c1 U111 ( .A(crc16_out[5]), .B(n2), .Y(n61) );
  ao2h2 U113 ( .B(crc16_sum[4]), .A(n2), .C(n62), .D(n51), .Y(n124) );
  or2c1 U114 ( .A(crc16_out[4]), .B(n2), .Y(n62) );
  ao2h2 U115 ( .B(crc16_sum[2]), .A(n3), .C(n64), .D(n51), .Y(n126) );
  or2c1 U116 ( .A(crc16_out[2]), .B(n1), .Y(n64) );
  ao2h2 U118 ( .B(crc16_sum[0]), .A(n3), .C(n66), .D(n51), .Y(n128) );
  or2c1 U119 ( .A(crc16_out[0]), .B(n1), .Y(n66) );
  ao2h2 U120 ( .B(crc16_sum[8]), .A(n3), .C(n58), .D(n51), .Y(n120) );
  or2c1 U121 ( .A(crc16_out[8]), .B(n1), .Y(n58) );
  ao2h2 U122 ( .B(crc16_sum[13]), .A(n2), .C(n53), .D(n51), .Y(n115) );
  or2c1 U123 ( .A(crc16_out[13]), .B(n1), .Y(n53) );
  ao2h2 U124 ( .B(crc16_sum[12]), .A(n2), .C(n54), .D(n51), .Y(n116) );
  or2c1 U125 ( .A(crc16_out[12]), .B(n1), .Y(n54) );
  ao2h2 U126 ( .B(crc16_sum[9]), .A(n2), .C(n57), .D(n51), .Y(n119) );
  or2c1 U127 ( .A(crc16_out[9]), .B(n1), .Y(n57) );
  or2c3 U128 ( .A(pid[3]), .B(pid[2]), .Y(n91) );
  or2a9 U129 ( .A(rx_active_r), .B(n143), .Y(n51) );
  ao1f2 U130 ( .A(n80), .B(n81), .C(n82), .Y(n70) );
  and2c3 U131 ( .A(pid[1]), .B(n83), .Y(n80) );
  or2c1 U132 ( .A(crc16_out[15]), .B(n1), .Y(n50) );
  or2c1 U133 ( .A(crc16_out[14]), .B(n1), .Y(n52) );
  or2c1 U134 ( .A(crc16_out[11]), .B(n1), .Y(n55) );
  or2c1 U135 ( .A(crc16_out[10]), .B(n1), .Y(n56) );
  ao1d2 U136 ( .A(n78), .B(rx_valid), .C(n38), .Y(n75) );
  inv1a3 U137 ( .A(state[2]), .Y(n33) );
  or2c3 U138 ( .A(state[3]), .B(n142), .Y(n49) );
  ao1d1 U139 ( .A(n49), .B(rxv1), .C(n48), .Y(n112) );
  inv1a3 U140 ( .A(rx_valid), .Y(n141) );
  inv1a3 U141 ( .A(pid[0]), .Y(n26) );
  inv1a3 U142 ( .A(state[0]), .Y(n21) );
  inv1a3 U143 ( .A(pid[2]), .Y(n30) );
  oa1f3 U144 ( .A(state[1]), .B(n79), .C(token_valid_r1), .Y(n110) );
  and2c1 U145 ( .A(n48), .B(n139), .Y(N39) );
  inv1a1 U146 ( .A(rxv2), .Y(n139) );
  oa4a2 U147 ( .A(n32), .B(n37), .C(n33), .D(n38), .Y(n36) );
  inv1a1 U148 ( .A(state[1]), .Y(n32) );
  or3d1 U149 ( .A(crc16_sum[0]), .B(crc16_sum[2]), .C(n108), .Y(n107) );
  and2c1 U150 ( .A(n138), .B(n132), .Y(n108) );
  and3d2 U151 ( .A(n94), .B(n95), .C(n96), .Y(n93) );
  or3d1 U152 ( .A(n97), .B(n98), .C(n99), .Y(n94) );
  or3d1 U153 ( .A(n137), .B(n35), .C(n104), .Y(n103) );
  and2c1 U154 ( .A(crc16_sum[5]), .B(crc16_sum[4]), .Y(n104) );
  or3d1 U155 ( .A(n133), .B(n134), .C(n105), .Y(n102) );
  and2c1 U156 ( .A(crc16_sum[9]), .B(crc16_sum[8]), .Y(n105) );
  or2c1 U157 ( .A(state[1]), .B(n74), .Y(n72) );
  inv1a1 U158 ( .A(rx_data[7]), .Y(n144) );
  inv1a1 U159 ( .A(rx_data[6]), .Y(n145) );
  inv1a1 U160 ( .A(rx_data[5]), .Y(n146) );
  inv1a1 U161 ( .A(rx_data[4]), .Y(n147) );
  or2c1 U162 ( .A(n44), .B(n45), .Y(n111) );
  or3d1 U163 ( .A(state[3]), .B(rx_valid), .C(n46), .Y(n44) );
  or3d1 U164 ( .A(rx_busy_d), .B(state[3]), .C(n46), .Y(n45) );
  and3d2 U165 ( .A(state[0]), .B(state[2]), .C(state[1]), .Y(n46) );
  oa2i2 U166 ( .A(state[1]), .B(n77), .C(state[3]), .D(state[2]), .Y(n76) );
  ao1f2 U167 ( .A(n37), .B(n21), .C(rx_active), .Y(n77) );
  inv1a1 U168 ( .A(n47), .Y(n27) );
  oa1f3 U169 ( .A(n2), .B(rxv1), .C(rx_data_done), .Y(n47) );
  clk1b6 U170 ( .A(n67), .Y(n24) );
  clk1b6 U171 ( .A(rx_active), .Y(n143) );
endmodule


module usb1_crc16_1 ( crc_in, din, crc_out );
  input [15:0] crc_in;
  input [7:0] din;
  output [15:0] crc_out;
  wire   crc_in_1, crc_in_0, \crc_in[6] , \crc_in[5] , \crc_in[4] ,
         \crc_in[3] , \crc_in[2] , n2, n13, n14, n15, n16, n17, n18, n19, n20,
         n21, n22;
  assign crc_in_1 = crc_in[1];
  assign crc_in_0 = crc_in[0];
  assign crc_out[14] = \crc_in[6] ;
  assign \crc_in[6]  = crc_in[6];
  assign crc_out[13] = \crc_in[5] ;
  assign \crc_in[5]  = crc_in[5];
  assign crc_out[12] = \crc_in[4] ;
  assign \crc_in[4]  = crc_in[4];
  assign crc_out[11] = \crc_in[3] ;
  assign \crc_in[3]  = crc_in[3];
  assign crc_out[10] = \crc_in[2] ;
  assign \crc_in[2]  = crc_in[2];

  xor2a2 U1 ( .A(crc_in_1), .B(n22), .Y(crc_out[9]) );
  xor2a2 U2 ( .A(crc_in_0), .B(n21), .Y(crc_out[8]) );
  xor2b2 U3 ( .A(n20), .B(n19), .Y(crc_out[7]) );
  xor2b2 U4 ( .A(n18), .B(n17), .Y(crc_out[5]) );
  xor2b2 U5 ( .A(n16), .B(n15), .Y(crc_out[3]) );
  xor3b3 U6 ( .A(n2), .B(n15), .C(n14), .Y(crc_out[1]) );
  xor2a2 U7 ( .A(crc_in[7]), .B(crc_out[0]), .Y(crc_out[15]) );
  xor3b3 U8 ( .A(n2), .B(crc_out[2]), .C(n14), .Y(crc_out[0]) );
  xor2a2 U9 ( .A(crc_out[6]), .B(n21), .Y(n14) );
  xor2b2 U10 ( .A(n20), .B(n22), .Y(n21) );
  xor2a2 U11 ( .A(din[7]), .B(crc_in[15]), .Y(n22) );
  xor2b2 U12 ( .A(din[6]), .B(crc_in[14]), .Y(n20) );
  xor2b2 U13 ( .A(n18), .B(n19), .Y(crc_out[6]) );
  xor2a2 U14 ( .A(din[5]), .B(crc_in[13]), .Y(n19) );
  xor2b2 U15 ( .A(din[4]), .B(crc_in[12]), .Y(n18) );
  xor3b3 U16 ( .A(din[0]), .B(crc_in[8]), .C(n15), .Y(n13) );
  xor2a2 U17 ( .A(din[1]), .B(crc_in[9]), .Y(n15) );
  xor2b2 U18 ( .A(n16), .B(n17), .Y(crc_out[4]) );
  xor2a2 U19 ( .A(din[3]), .B(crc_in[11]), .Y(n17) );
  xor2b2 U20 ( .A(din[2]), .B(crc_in[10]), .Y(n16) );
  inv1a1 U21 ( .A(n13), .Y(crc_out[2]) );
  inv1a3 U22 ( .A(crc_out[4]), .Y(n2) );
endmodule


module usb1_pa ( clk, rst, tx_data, tx_valid, tx_valid_last, tx_ready, 
        tx_first, send_token, token_pid_sel, send_data, data_pid_sel, 
        tx_data_st, rd_next, ep_empty );
  output [7:0] tx_data;
  input [1:0] token_pid_sel;
  input [1:0] data_pid_sel;
  input [7:0] tx_data_st;
  input clk, rst, tx_ready, send_token, send_data, ep_empty;
  output tx_valid, tx_valid_last, tx_first, rd_next;
  wire   zero_length_r, tx_valid_r1, tx_valid_r, send_token_r, N48, tx_first_r,
         send_data_r, send_data_r2, N49, crc16_add, n24, n25, n26, n27, n28,
         n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42,
         n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56,
         n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
         n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84,
         n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98,
         n99, n100, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
         n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n101, n102, n103,
         n104, n105, n106, n107;
  wire   [15:0] crc16;
  wire   [15:0] crc16_next;
  wire   [3:0] state;

  or2b2 U4 ( .B(n24), .A(n8), .Y(tx_valid_last) );
  and2b2 U6 ( .B(N48), .A(tx_first_r), .Y(tx_first) );
  oa4f3 U8 ( .A(tx_data_st[7]), .B(n29), .C(n30), .D(n31), .Y(n28) );
  oa4f3 U12 ( .A(tx_data_st[6]), .B(n29), .C(n30), .D(n35), .Y(n34) );
  oa4f3 U17 ( .A(n39), .B(n22), .C(n40), .D(n102), .Y(n37) );
  ao2i3 U18 ( .A(crc16[3]), .B(n13), .C(n41), .D(n42), .Y(tx_data[4]) );
  oa4f3 U22 ( .A(tx_data_st[3]), .B(n29), .C(n30), .D(n44), .Y(n43) );
  oa4f3 U24 ( .A(n39), .B(n23), .C(data_pid_sel[0]), .D(n14), .Y(n45) );
  xor2a2 U25 ( .A(token_pid_sel[1]), .B(token_pid_sel[0]), .Y(n27) );
  oa4f3 U27 ( .A(tx_data_st[2]), .B(n29), .C(n30), .D(n47), .Y(n46) );
  oa4f3 U29 ( .A(n39), .B(n101), .C(data_pid_sel[1]), .D(n14), .Y(n48) );
  ao2i3 U30 ( .A(n16), .B(n49), .C(n50), .D(n26), .Y(tx_data[1]) );
  and2c6 U36 ( .A(n10), .B(n54), .Y(n29) );
  ao2i3 U38 ( .A(n55), .B(n19), .C(n21), .D(n25), .Y(n54) );
  ao2i3 U45 ( .A(n2), .B(n105), .C(n58), .D(n11), .Y(n82) );
  ao2i3 U47 ( .A(n2), .B(n104), .C(n59), .D(n11), .Y(n83) );
  ao2i3 U53 ( .A(n2), .B(n103), .C(n62), .D(n11), .Y(n86) );
  ao2i3 U55 ( .A(n2), .B(n102), .C(n63), .D(n11), .Y(n87) );
  ao2i3 U65 ( .A(n3), .B(n101), .C(n68), .D(n11), .Y(n92) );
  ao2i3 U67 ( .A(n3), .B(n23), .C(n69), .D(n11), .Y(n93) );
  ao2i3 U71 ( .A(n3), .B(n22), .C(n71), .D(n11), .Y(n95) );
  oa4f3 U80 ( .A(zero_length_r), .B(n11), .C(ep_empty), .D(n75), .Y(n74) );
  oa4e3 U90 ( .C(n15), .D(rd_next), .B(send_data_r2), .A(send_data_r), .Y(n81)
         );
  usb1_crc16_1 u1 ( .crc_in(crc16), .din({tx_data_st[0], tx_data_st[1], 
        tx_data_st[2], tx_data_st[3], tx_data_st[4], tx_data_st[5], 
        tx_data_st[6], tx_data_st[7]}), .crc_out(crc16_next) );
  fdf1a3 tx_first_r_reg ( .D(N48), .CLK(n5), .Q(tx_first_r) );
  fdf1a3 send_data_r2_reg ( .D(send_data_r), .CLK(n5), .Q(send_data_r2) );
  fdef2a3 \state_reg[3]  ( .D(state[2]), .E(n12), .CLK(n5), .CLR(n4), .Q(
        state[3]) );
  fdf2a3 send_token_r_reg ( .D(n100), .CLK(n5), .CLR(n4), .Q(send_token_r) );
  fdf2a3 zero_length_r_reg ( .D(n98), .CLK(n6), .CLR(n4), .Q(zero_length_r) );
  fdf2a3 \state_reg[1]  ( .D(n99), .CLK(n5), .CLR(n4), .Q(state[1]) );
  fdef2c3 \state_reg[0]  ( .D(n21), .E(n12), .CLK(n5), .CLR(n4), .QN(state[0])
         );
  fdf1a3 tx_valid_r_reg ( .D(tx_valid_r1), .CLK(n6), .Q(tx_valid_r) );
  fdf1a3 \crc16_reg[10]  ( .D(n87), .CLK(n7), .Q(crc16[10]) );
  fdf1a3 \crc16_reg[11]  ( .D(n86), .CLK(n7), .Q(crc16[11]) );
  fdf1a3 \crc16_reg[14]  ( .D(n83), .CLK(n7), .Q(crc16[14]) );
  fdf1a3 \crc16_reg[15]  ( .D(n82), .CLK(n7), .Q(crc16[15]) );
  fdf1a3 crc16_add_reg ( .D(N49), .CLK(n6), .Q(crc16_add) );
  fdf1a3 \crc16_reg[2]  ( .D(n95), .CLK(n6), .Q(crc16[2]) );
  fdf1a3 \crc16_reg[4]  ( .D(n93), .CLK(n6), .Q(crc16[4]) );
  fdf1a3 \crc16_reg[5]  ( .D(n92), .CLK(n6), .Q(crc16[5]) );
  fdf1a3 \crc16_reg[3]  ( .D(n94), .CLK(n6), .Q(crc16[3]) );
  fdf1a3 \crc16_reg[0]  ( .D(n97), .CLK(n6), .Q(crc16[0]) );
  fdf1a3 \crc16_reg[1]  ( .D(n96), .CLK(n6), .Q(crc16[1]) );
  fdf1a3 \crc16_reg[9]  ( .D(n88), .CLK(n7), .Q(crc16[9]) );
  fdf1a3 \crc16_reg[12]  ( .D(n85), .CLK(n7), .Q(crc16[12]) );
  fdf1a3 \crc16_reg[13]  ( .D(n84), .CLK(n7), .Q(crc16[13]) );
  fdf1a3 \crc16_reg[8]  ( .D(n89), .CLK(n7), .Q(crc16[8]) );
  fdf1a3 \crc16_reg[6]  ( .D(n91), .CLK(n7), .Q(crc16[6]) );
  fdf1a3 \crc16_reg[7]  ( .D(n90), .CLK(n7), .Q(crc16[7]) );
  fdf1c3 send_data_r_reg ( .D(n17), .CLK(n5), .QN(send_data_r) );
  fdef2a3 \state_reg[2]  ( .D(n18), .E(n12), .CLK(n5), .CLR(n4), .Q(state[2])
         );
  fdf1a3 tx_valid_r1_reg ( .D(tx_valid), .CLK(n5), .Q(tx_valid_r1) );
  and3c2 U3 ( .C(tx_valid_r), .A(n106), .B(n19), .Y(rd_next) );
  and2c3 U5 ( .A(n10), .B(n16), .Y(n30) );
  ao4f6 U7 ( .A(tx_ready), .B(n20), .C(n55), .D(n19), .Y(n40) );
  clk1a6 U9 ( .A(crc16_add), .Y(n2) );
  clk1a6 U10 ( .A(crc16_add), .Y(n1) );
  or2c1 U11 ( .A(tx_ready), .B(state[2]), .Y(n57) );
  inv1a1 U13 ( .A(crc16[11]), .Y(n103) );
  inv1a1 U14 ( .A(n30), .Y(n9) );
  inv1a3 U15 ( .A(n39), .Y(n13) );
  inv1a3 U16 ( .A(n54), .Y(n16) );
  inv1a3 U19 ( .A(n33), .Y(n14) );
  clk1a3 U20 ( .A(clk), .Y(n7) );
  clk1a3 U21 ( .A(clk), .Y(n6) );
  clk1a3 U23 ( .A(clk), .Y(n5) );
  inv1a3 U26 ( .A(n40), .Y(n15) );
  and2c3 U28 ( .A(n40), .B(n14), .Y(n39) );
  inv1a3 U31 ( .A(send_data), .Y(n17) );
  ao1f2 U32 ( .A(n37), .B(n9), .C(n38), .Y(tx_data[5]) );
  or2c1 U33 ( .A(tx_data_st[5]), .B(n29), .Y(n38) );
  inv1a3 U34 ( .A(n26), .Y(n10) );
  or3d3 U35 ( .A(n57), .B(n21), .C(n15), .Y(n33) );
  or2c1 U37 ( .A(crc16_next[5]), .B(n1), .Y(n68) );
  or2c1 U39 ( .A(crc16_next[4]), .B(n1), .Y(n69) );
  or2c1 U40 ( .A(crc16_next[2]), .B(n1), .Y(n71) );
  or2c3 U41 ( .A(n25), .B(n19), .Y(tx_valid) );
  or2c1 U42 ( .A(n8), .B(n17), .Y(N48) );
  clk1a6 U43 ( .A(rst), .Y(n4) );
  inv1a1 U44 ( .A(state[2]), .Y(n20) );
  and2c3 U46 ( .A(send_token_r), .B(send_token), .Y(n26) );
  oa2i2 U48 ( .A(n40), .B(n104), .C(n14), .D(n51), .Y(n49) );
  or2c1 U49 ( .A(tx_data_st[1]), .B(n16), .Y(n50) );
  and2c3 U50 ( .A(crc16[6]), .B(n13), .Y(n51) );
  oa1f3 U51 ( .A(tx_data_st[4]), .B(n16), .C(n10), .Y(n42) );
  or2c1 U52 ( .A(n40), .B(n103), .Y(n41) );
  ao1f2 U54 ( .A(tx_ready), .B(n21), .C(n57), .Y(n24) );
  and2c3 U56 ( .A(n17), .B(send_data_r), .Y(n75) );
  ao2h2 U57 ( .B(crc16[7]), .A(n2), .C(n66), .D(n11), .Y(n90) );
  or2c1 U58 ( .A(crc16_next[7]), .B(n1), .Y(n66) );
  ao2h2 U59 ( .B(crc16[6]), .A(n3), .C(n67), .D(n11), .Y(n91) );
  or2c1 U60 ( .A(crc16_next[6]), .B(n1), .Y(n67) );
  ao2h2 U61 ( .B(crc16[8]), .A(n2), .C(n65), .D(n11), .Y(n89) );
  or2c1 U62 ( .A(crc16_next[8]), .B(n2), .Y(n65) );
  ao2h2 U63 ( .B(crc16[13]), .A(n2), .C(n60), .D(n11), .Y(n84) );
  or2c1 U64 ( .A(crc16_next[13]), .B(n1), .Y(n60) );
  ao2h2 U66 ( .B(crc16[12]), .A(n2), .C(n61), .D(n11), .Y(n85) );
  or2c1 U68 ( .A(crc16_next[12]), .B(n2), .Y(n61) );
  ao2h2 U69 ( .B(crc16[9]), .A(n2), .C(n64), .D(n11), .Y(n88) );
  or2c1 U70 ( .A(crc16_next[9]), .B(n2), .Y(n64) );
  ao2h2 U72 ( .B(crc16[1]), .A(n3), .C(n72), .D(n11), .Y(n96) );
  or2c1 U73 ( .A(crc16_next[1]), .B(n1), .Y(n72) );
  ao2h2 U74 ( .B(crc16[0]), .A(n2), .C(n73), .D(n11), .Y(n97) );
  or2c1 U75 ( .A(crc16_next[0]), .B(n1), .Y(n73) );
  ao2h2 U76 ( .B(crc16[3]), .A(n3), .C(n70), .D(n11), .Y(n94) );
  or2c1 U77 ( .A(crc16_next[3]), .B(n1), .Y(n70) );
  inv1a3 U78 ( .A(state[1]), .Y(n19) );
  inv1a3 U79 ( .A(n76), .Y(n12) );
  ao2h2 U81 ( .B(n55), .A(n19), .C(n79), .D(n80), .Y(n76) );
  or2c1 U82 ( .A(state[0]), .B(n17), .Y(n80) );
  ao1f2 U83 ( .A(state[3]), .B(state[2]), .C(n106), .Y(n79) );
  oa1f3 U84 ( .A(send_data), .B(state[0]), .C(state[2]), .Y(n25) );
  or2c1 U85 ( .A(crc16_next[15]), .B(n1), .Y(n58) );
  or2c1 U86 ( .A(crc16_next[14]), .B(n1), .Y(n59) );
  or2c1 U87 ( .A(crc16_next[11]), .B(n2), .Y(n62) );
  or2c1 U88 ( .A(crc16_next[10]), .B(n2), .Y(n63) );
  ao1f2 U89 ( .A(n26), .B(n27), .C(n28), .Y(tx_data[7]) );
  ao1f2 U91 ( .A(crc16[8]), .B(n15), .C(n32), .Y(n31) );
  oa4a2 U92 ( .A(n13), .B(crc16[0]), .C(n33), .D(data_pid_sel[0]), .Y(n32) );
  ao1f2 U93 ( .A(token_pid_sel[1]), .B(n26), .C(n34), .Y(tx_data[6]) );
  ao1f2 U94 ( .A(crc16[9]), .B(n15), .C(n36), .Y(n35) );
  oa4a2 U95 ( .A(n13), .B(crc16[1]), .C(n33), .D(data_pid_sel[1]), .Y(n36) );
  ao1f2 U96 ( .A(n52), .B(n9), .C(n53), .Y(tx_data[0]) );
  oa2i1 U97 ( .A(n40), .B(n105), .C(n14), .D(n56), .Y(n52) );
  or2c1 U98 ( .A(tx_data_st[0]), .B(n29), .Y(n53) );
  and2c1 U99 ( .A(crc16[7]), .B(n13), .Y(n56) );
  inv1a3 U100 ( .A(state[3]), .Y(n21) );
  or3d3 U101 ( .A(tx_ready), .B(n17), .C(tx_valid_r), .Y(n55) );
  ao1f2 U102 ( .A(n12), .B(n19), .C(n78), .Y(n99) );
  or3d1 U103 ( .A(state[0]), .B(n107), .C(n12), .Y(n78) );
  inv1a1 U104 ( .A(ep_empty), .Y(n107) );
  ao1d2 U105 ( .A(n10), .B(token_pid_sel[1]), .C(n46), .Y(tx_data[2]) );
  ao1f2 U106 ( .A(crc16[13]), .B(n15), .C(n48), .Y(n47) );
  ao1d2 U107 ( .A(n10), .B(n27), .C(n43), .Y(tx_data[3]) );
  ao1f2 U108 ( .A(crc16[12]), .B(n15), .C(n45), .Y(n44) );
  and2c3 U109 ( .A(n74), .B(n24), .Y(n98) );
  inv1a3 U110 ( .A(tx_ready), .Y(n106) );
  inv1a3 U111 ( .A(send_token), .Y(n8) );
  ao1d2 U112 ( .A(n106), .B(send_token_r), .C(n8), .Y(n100) );
  and2c1 U113 ( .A(zero_length_r), .B(n81), .Y(N49) );
  inv1a1 U114 ( .A(n77), .Y(n18) );
  oa1f3 U115 ( .A(ep_empty), .B(state[0]), .C(state[1]), .Y(n77) );
  inv1a1 U116 ( .A(crc16[5]), .Y(n101) );
  inv1a1 U117 ( .A(crc16[4]), .Y(n23) );
  inv1a1 U118 ( .A(crc16[2]), .Y(n22) );
  inv1a1 U119 ( .A(crc16[14]), .Y(n104) );
  inv1a1 U120 ( .A(crc16[10]), .Y(n102) );
  inv1a1 U121 ( .A(crc16[15]), .Y(n105) );
  clk1a3 U122 ( .A(crc16_add), .Y(n3) );
  inv1a9 U123 ( .A(n75), .Y(n11) );
endmodule


module usb1_fifo2 ( clk, rst, clr, din, we, dout, re );
  input [7:0] din;
  output [7:0] dout;
  input clk, rst, clr, we, re;
  wire   N3, wp, \mem[0][7] , \mem[0][6] , \mem[0][5] , \mem[0][4] ,
         \mem[0][3] , \mem[0][2] , \mem[0][1] , \mem[0][0] , \mem[1][7] ,
         \mem[1][6] , \mem[1][5] , \mem[1][4] , \mem[1][3] , \mem[1][2] ,
         \mem[1][1] , \mem[1][0] , n4, n5, n6, n7, n8, n1, n2, n3, n9;

  xor2b2 U6 ( .A(N3), .B(re), .Y(n5) );
  or2b2 U8 ( .B(we), .A(wp), .Y(n6) );
  or2b2 U9 ( .B(wp), .A(we), .Y(n4) );
  fdef1a3 \mem_reg[0][7]  ( .D(din[7]), .E(n9), .CLK(n2), .Q(\mem[0][7] ) );
  fdef1a3 \mem_reg[0][6]  ( .D(din[6]), .E(n9), .CLK(n2), .Q(\mem[0][6] ) );
  fdef1a3 \mem_reg[0][5]  ( .D(din[5]), .E(n9), .CLK(n2), .Q(\mem[0][5] ) );
  fdef1a3 \mem_reg[0][4]  ( .D(din[4]), .E(n9), .CLK(n2), .Q(\mem[0][4] ) );
  fdef1a3 \mem_reg[0][3]  ( .D(din[3]), .E(n9), .CLK(n2), .Q(\mem[0][3] ) );
  fdef1a3 \mem_reg[0][2]  ( .D(din[2]), .E(n9), .CLK(n2), .Q(\mem[0][2] ) );
  fdef1a3 \mem_reg[0][1]  ( .D(din[1]), .E(n9), .CLK(n2), .Q(\mem[0][1] ) );
  fdef1a3 \mem_reg[0][0]  ( .D(din[0]), .E(n9), .CLK(n3), .Q(\mem[0][0] ) );
  fdef1a3 \mem_reg[1][7]  ( .D(din[7]), .E(n1), .CLK(n3), .Q(\mem[1][7] ) );
  fdef1a3 \mem_reg[1][6]  ( .D(din[6]), .E(n1), .CLK(n3), .Q(\mem[1][6] ) );
  fdef1a3 \mem_reg[1][5]  ( .D(din[5]), .E(n1), .CLK(n3), .Q(\mem[1][5] ) );
  fdef1a3 \mem_reg[1][4]  ( .D(din[4]), .E(n1), .CLK(n3), .Q(\mem[1][4] ) );
  fdef1a3 \mem_reg[1][3]  ( .D(din[3]), .E(n1), .CLK(n3), .Q(\mem[1][3] ) );
  fdef1a3 \mem_reg[1][2]  ( .D(din[2]), .E(n1), .CLK(n3), .Q(\mem[1][2] ) );
  fdef1a3 \mem_reg[1][1]  ( .D(din[1]), .E(n1), .CLK(n3), .Q(\mem[1][1] ) );
  fdef1a3 \mem_reg[1][0]  ( .D(din[0]), .E(n1), .CLK(n3), .Q(\mem[1][0] ) );
  fdf2a3 wp_reg ( .D(n8), .CLK(n2), .CLR(rst), .Q(wp) );
  fdf2a6 rp_reg ( .D(n7), .CLK(n2), .CLR(rst), .Q(N3) );
  and2a6 U2 ( .A(wp), .B(we), .Y(n1) );
  clk1a3 U3 ( .A(clk), .Y(n3) );
  clk1a3 U4 ( .A(clk), .Y(n2) );
  oa1f3 U5 ( .A(n4), .B(n6), .C(clr), .Y(n8) );
  and2c3 U7 ( .A(clr), .B(n5), .Y(n7) );
  mx2a3 U10 ( .D0(\mem[0][5] ), .D1(\mem[1][5] ), .S(N3), .Y(dout[5]) );
  mx2a3 U11 ( .D0(\mem[0][4] ), .D1(\mem[1][4] ), .S(N3), .Y(dout[4]) );
  mx2a3 U12 ( .D0(\mem[0][0] ), .D1(\mem[1][0] ), .S(N3), .Y(dout[0]) );
  mx2a3 U13 ( .D0(\mem[0][1] ), .D1(\mem[1][1] ), .S(N3), .Y(dout[1]) );
  mx2a3 U14 ( .D0(\mem[0][7] ), .D1(\mem[1][7] ), .S(N3), .Y(dout[7]) );
  mx2a3 U15 ( .D0(\mem[0][3] ), .D1(\mem[1][3] ), .S(N3), .Y(dout[3]) );
  mx2a3 U16 ( .D0(\mem[0][2] ), .D1(\mem[1][2] ), .S(N3), .Y(dout[2]) );
  mx2a3 U17 ( .D0(\mem[0][6] ), .D1(\mem[1][6] ), .S(N3), .Y(dout[6]) );
  clk1b6 U18 ( .A(n4), .Y(n9) );
endmodule


module usb1_idma_DW01_inc_0 ( A, SUM );
  input [7:0] A;
  output [7:0] SUM;

  wire   [7:2] carry;

  ha1a2 U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[7]), .B(A[7]), .Y(SUM[7]) );
endmodule


module usb1_idma ( clk, rst, rx_data_valid, rx_data_done, send_data, rd_next, 
        tx_valid, tx_data_st_i, tx_data_st_o, tx_dma_en, rx_dma_en, idma_done, 
        ep_sel, size, rx_cnt, rx_done, tx_busy, ep_bf_en, ep_bf_size, 
        dropped_frame, misaligned_frame, mwe, mre, ep_empty, ep_empty_int, 
        ep_full );
  input [7:0] tx_data_st_i;
  output [7:0] tx_data_st_o;
  input [3:0] ep_sel;
  input [8:0] size;
  output [7:0] rx_cnt;
  input [6:0] ep_bf_size;
  input clk, rst, rx_data_valid, rx_data_done, rd_next, tx_valid, tx_dma_en,
         rx_dma_en, ep_bf_en, ep_empty, ep_full;
  output send_data, idma_done, rx_done, tx_busy, dropped_frame,
         misaligned_frame, mwe, mre, ep_empty_int;
  wire   ep_empty, mwe_r, tx_dma_en_r, tx_dma_en_r1, tx_dma_en_r2, N3, N8, N9,
         N10, N11, N12, N13, N14, N15, N32, N33, N34, N35, N36, N37, N38, N39,
         N40, sizd_is_zero, ep_empty_r, send_data_r, ff_we1, ff_we, n19, n20,
         n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
         n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
         n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
         n63, n64, n65, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
         n14, n15, n16, n18, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
         n76, n77, n78;
  wire   [7:0] rx_cnt_r;
  wire   [8:0] sizd_c;
  assign dropped_frame = 1'b0;
  assign misaligned_frame = 1'b0;
  assign ep_empty_int = ep_empty;

  oa4e3 U9 ( .C(tx_dma_en_r2), .D(ep_empty), .B(tx_dma_en_r2), .A(ep_empty_r), 
        .Y(n21) );
  oa4f3 U11 ( .A(N39), .B(n15), .C(size[7]), .D(n3), .Y(n23) );
  oa4f3 U13 ( .A(N38), .B(n15), .C(size[6]), .D(n3), .Y(n24) );
  oa4f3 U15 ( .A(N37), .B(n15), .C(size[5]), .D(n3), .Y(n25) );
  oa4f3 U17 ( .A(N36), .B(n15), .C(size[4]), .D(n3), .Y(n26) );
  oa4f3 U19 ( .A(N35), .B(n15), .C(size[3]), .D(n3), .Y(n27) );
  oa4f3 U21 ( .A(N34), .B(n15), .C(size[2]), .D(n3), .Y(n28) );
  oa4f3 U23 ( .A(N33), .B(n15), .C(size[1]), .D(n3), .Y(n29) );
  oa4f3 U25 ( .A(N40), .B(n15), .C(size[8]), .D(n3), .Y(n30) );
  oa4f3 U27 ( .A(N32), .B(n15), .C(n3), .D(size[0]), .Y(n31) );
  or2c6 U28 ( .A(n16), .B(n32), .Y(n22) );
  ao4a3 U30 ( .A(rx_cnt_r[7]), .B(n35), .C(N15), .D(n36), .Y(n58) );
  ao4a3 U31 ( .A(rx_cnt_r[6]), .B(n35), .C(N14), .D(n36), .Y(n59) );
  ao4a3 U32 ( .A(rx_cnt_r[5]), .B(n35), .C(N13), .D(n36), .Y(n60) );
  ao4a3 U33 ( .A(rx_cnt_r[4]), .B(n35), .C(N12), .D(n36), .Y(n61) );
  ao4a3 U34 ( .A(rx_cnt_r[3]), .B(n35), .C(N11), .D(n36), .Y(n62) );
  ao4a3 U35 ( .A(rx_cnt_r[2]), .B(n35), .C(N10), .D(n36), .Y(n63) );
  ao4a3 U36 ( .A(rx_cnt_r[1]), .B(n35), .C(N9), .D(n36), .Y(n64) );
  ao4a3 U37 ( .A(rx_cnt_r[0]), .B(n35), .C(N8), .D(n36), .Y(n65) );
  and2c6 U38 ( .A(rx_done), .B(n36), .Y(n35) );
  and2b2 U40 ( .B(mwe_r), .A(ep_full), .Y(mwe) );
  ao2i3 U41 ( .A(send_data), .B(tx_dma_en_r), .C(n20), .D(n34), .Y(n37) );
  ao2e3 U44 ( .B(n39), .A(n40), .D(ep_empty_r), .C(send_data_r), .Y(n38) );
  and3c3 U47 ( .C(n42), .A(size[4]), .B(size[5]), .Y(n39) );
  or2b2 U49 ( .B(rx_done), .A(n20), .Y(N3) );
  usb1_fifo2 ff ( .clk(n6), .rst(n4), .clr(n66), .din(tx_data_st_i), .we(ff_we), .dout(tx_data_st_o), .re(rd_next) );
  usb1_idma_DW01_inc_0 add_293_S2 ( .A(rx_cnt_r), .SUM({N15, N14, N13, N12, 
        N11, N10, N9, N8}) );
  fdf1a3 mwe_r_reg ( .D(rx_data_valid), .CLK(n6), .Q(mwe_r) );
  fdf1a3 idma_done_reg ( .D(N3), .CLK(n6), .Q(idma_done) );
  fdf2a3 ep_empty_r_reg ( .D(n48), .CLK(n6), .CLR(n5), .Q(ep_empty_r) );
  fdf2a3 send_data_r_reg ( .D(n47), .CLK(n6), .CLR(n4), .Q(send_data_r) );
  fdf3a3 \sizd_c_reg[8]  ( .D(n56), .CLK(n6), .PRE(n4), .Q(sizd_c[8]) );
  fdf3a3 \sizd_c_reg[6]  ( .D(n50), .CLK(n6), .PRE(n4), .Q(sizd_c[6]) );
  fdf1c3 tx_dma_en_r1_reg ( .D(n18), .CLK(n6), .QN(tx_dma_en_r1) );
  fdf3a3 \sizd_c_reg[7]  ( .D(n49), .CLK(n6), .PRE(n4), .Q(sizd_c[7]) );
  fdf1c3 sizd_is_zero_reg ( .D(n33), .CLK(n6), .QN(sizd_is_zero) );
  fdf2a3 \rx_cnt_r_reg[1]  ( .D(n64), .CLK(n6), .CLR(n5), .Q(rx_cnt_r[1]) );
  fdf2a3 \rx_cnt_r_reg[2]  ( .D(n63), .CLK(n6), .CLR(n4), .Q(rx_cnt_r[2]) );
  fdf2a3 \rx_cnt_r_reg[3]  ( .D(n62), .CLK(n6), .CLR(n4), .Q(rx_cnt_r[3]) );
  fdf2a3 \rx_cnt_r_reg[4]  ( .D(n61), .CLK(n6), .CLR(n4), .Q(rx_cnt_r[4]) );
  fdf2a3 \rx_cnt_r_reg[5]  ( .D(n60), .CLK(n6), .CLR(n4), .Q(rx_cnt_r[5]) );
  fdf2a3 \rx_cnt_r_reg[6]  ( .D(n59), .CLK(n6), .CLR(n4), .Q(rx_cnt_r[6]) );
  fdf2a3 \rx_cnt_r_reg[7]  ( .D(n58), .CLK(n6), .CLR(n4), .Q(rx_cnt_r[7]) );
  fdf1c3 tx_dma_en_r2_reg ( .D(n68), .CLK(n6), .QN(tx_dma_en_r2) );
  fdf3a3 \sizd_c_reg[1]  ( .D(n55), .CLK(n6), .PRE(n4), .Q(sizd_c[1]) );
  fdf3a3 \sizd_c_reg[2]  ( .D(n54), .CLK(n6), .PRE(n4), .Q(sizd_c[2]) );
  fdf3a3 \sizd_c_reg[3]  ( .D(n53), .CLK(n6), .PRE(n4), .Q(sizd_c[3]) );
  fdf3a3 \sizd_c_reg[4]  ( .D(n52), .CLK(n6), .PRE(n4), .Q(sizd_c[4]) );
  fdf3a3 \sizd_c_reg[5]  ( .D(n51), .CLK(n6), .PRE(n4), .Q(sizd_c[5]) );
  fdf1c3 tx_dma_en_r_reg ( .D(n16), .CLK(n6), .QN(tx_dma_en_r) );
  fdf1a3 ff_we_reg ( .D(ff_we1), .CLK(n6), .Q(ff_we) );
  fdf3a3 \sizd_c_reg[0]  ( .D(n57), .CLK(n6), .PRE(n4), .Q(sizd_c[0]) );
  fdf2a3 \rx_cnt_r_reg[0]  ( .D(n65), .CLK(n6), .CLR(n5), .Q(rx_cnt_r[0]) );
  fdf1a9 rx_data_done_r_reg ( .D(rx_data_done), .CLK(n6), .Q(rx_done) );
  fdf1c3 ff_we1_reg ( .D(n37), .CLK(n6), .QN(ff_we1) );
  fdef2a3 \rx_cnt_reg[7]  ( .D(rx_cnt_r[7]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[7]) );
  fdef2a3 \rx_cnt_reg[6]  ( .D(rx_cnt_r[6]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[6]) );
  fdef2a3 \rx_cnt_reg[5]  ( .D(rx_cnt_r[5]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[5]) );
  fdef2a3 \rx_cnt_reg[4]  ( .D(rx_cnt_r[4]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[4]) );
  fdef2a3 \rx_cnt_reg[3]  ( .D(rx_cnt_r[3]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[3]) );
  fdef2a3 \rx_cnt_reg[2]  ( .D(rx_cnt_r[2]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[2]) );
  fdef2a3 \rx_cnt_reg[1]  ( .D(rx_cnt_r[1]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[1]) );
  fdef2a3 \rx_cnt_reg[0]  ( .D(rx_cnt_r[0]), .E(rx_done), .CLK(n6), .CLR(n4), 
        .Q(rx_cnt[0]) );
  and2c1 U5 ( .A(n9), .B(sizd_c[4]), .Y(n1) );
  inv1a2 U6 ( .A(n1), .Y(n2) );
  and2c3 U7 ( .A(sizd_c[7]), .B(n12), .Y(n13) );
  or2c3 U8 ( .A(n11), .B(n14), .Y(n12) );
  and2c2 U10 ( .A(n2), .B(sizd_c[5]), .Y(n11) );
  or3d1 U12 ( .A(n18), .B(n68), .C(n78), .Y(n34) );
  inv1a1 U14 ( .A(rd_next), .Y(n78) );
  inv1a1 U16 ( .A(sizd_c[7]), .Y(n77) );
  inv1a1 U18 ( .A(sizd_c[8]), .Y(n71) );
  inv1a3 U20 ( .A(n3), .Y(n16) );
  inv1a3 U22 ( .A(tx_valid), .Y(n66) );
  clk1b6 U24 ( .A(n32), .Y(n15) );
  clk1a15 U26 ( .A(clk), .Y(n6) );
  inv1a1 U29 ( .A(n37), .Y(mre) );
  or3d3 U39 ( .A(n33), .B(n16), .C(n34), .Y(n32) );
  and3d2 U42 ( .A(size[1]), .B(size[3]), .C(size[2]), .Y(n41) );
  ao1f2 U43 ( .A(n22), .B(n14), .C(n24), .Y(n50) );
  and3d2 U45 ( .A(size[6]), .B(size[8]), .C(size[7]), .Y(n42) );
  clk1a15 U46 ( .A(rst), .Y(n4) );
  or3d1 U48 ( .A(n77), .B(n71), .C(n14), .Y(n46) );
  clk1a6 U50 ( .A(tx_dma_en), .Y(n3) );
  clk1a3 U51 ( .A(rst), .Y(n5) );
  and2c3 U52 ( .A(ep_empty), .B(n70), .Y(n20) );
  inv1a1 U53 ( .A(n33), .Y(n70) );
  or2c3 U54 ( .A(n68), .B(n38), .Y(send_data) );
  or3d1 U55 ( .A(size[0]), .B(sizd_is_zero), .C(n41), .Y(n40) );
  ao1f2 U56 ( .A(n22), .B(n77), .C(n23), .Y(n49) );
  ao1f2 U57 ( .A(n22), .B(n76), .C(n25), .Y(n51) );
  inv1a1 U58 ( .A(sizd_c[5]), .Y(n76) );
  inv1a1 U59 ( .A(n10), .Y(N37) );
  ao1f2 U60 ( .A(n22), .B(n75), .C(n26), .Y(n52) );
  inv1a1 U61 ( .A(sizd_c[4]), .Y(n75) );
  ao1f2 U62 ( .A(n22), .B(n74), .C(n27), .Y(n53) );
  inv1a1 U63 ( .A(sizd_c[3]), .Y(n74) );
  ao1f2 U64 ( .A(n22), .B(n73), .C(n28), .Y(n54) );
  inv1a1 U65 ( .A(sizd_c[2]), .Y(n73) );
  ao1f2 U66 ( .A(n22), .B(n72), .C(n29), .Y(n55) );
  inv1a1 U67 ( .A(sizd_c[1]), .Y(n72) );
  ao1f2 U68 ( .A(n22), .B(n71), .C(n30), .Y(n56) );
  ao1f2 U69 ( .A(n22), .B(n69), .C(n31), .Y(n57) );
  inv1a1 U70 ( .A(sizd_c[0]), .Y(n69) );
  or3d3 U71 ( .A(n43), .B(n44), .C(n45), .Y(n33) );
  and2c3 U72 ( .A(sizd_c[1]), .B(sizd_c[0]), .Y(n43) );
  and2c3 U73 ( .A(sizd_c[3]), .B(sizd_c[2]), .Y(n44) );
  and3d2 U74 ( .A(n46), .B(sizd_c[5]), .C(sizd_c[4]), .Y(n45) );
  inv1a3 U75 ( .A(tx_dma_en_r), .Y(n18) );
  ao1f2 U76 ( .A(ep_empty), .B(n18), .C(n19), .Y(n47) );
  ao1f2 U77 ( .A(n20), .B(n78), .C(send_data_r), .Y(n19) );
  and2b6 U78 ( .B(rx_data_valid), .A(rx_done), .Y(n36) );
  inv1a3 U79 ( .A(tx_dma_en_r1), .Y(n68) );
  and2c3 U80 ( .A(n66), .B(n21), .Y(n48) );
  inv1a1 U81 ( .A(sizd_c[0]), .Y(N32) );
  inv1a3 U82 ( .A(sizd_c[6]), .Y(n14) );
  or3d1 U83 ( .A(n16), .B(n18), .C(n67), .Y(tx_busy) );
  inv1a1 U84 ( .A(send_data), .Y(n67) );
  or2b1 U85 ( .B(sizd_c[1]), .A(N32), .Y(n7) );
  ao1d1 U86 ( .A(sizd_c[0]), .B(sizd_c[1]), .C(n7), .Y(N33) );
  or2a1 U87 ( .A(n7), .B(sizd_c[2]), .Y(n8) );
  ao1d1 U88 ( .A(n7), .B(sizd_c[2]), .C(n8), .Y(N34) );
  or2a1 U89 ( .A(n8), .B(sizd_c[3]), .Y(n9) );
  ao1d1 U90 ( .A(n8), .B(sizd_c[3]), .C(n9), .Y(N35) );
  ao1d1 U91 ( .A(n9), .B(sizd_c[4]), .C(n2), .Y(N36) );
  oa1f1 U92 ( .A(n2), .B(sizd_c[5]), .C(n11), .Y(n10) );
  ao1f1 U93 ( .A(n11), .B(n14), .C(n12), .Y(N38) );
  xor2b1 U94 ( .A(sizd_c[7]), .B(n12), .Y(N39) );
  xor2a1 U95 ( .A(sizd_c[8]), .B(n13), .Y(N40) );
endmodule


module usb1_pe_DW01_inc_0 ( A, SUM );
  input [7:0] A;
  output [7:0] SUM;

  wire   [7:2] carry;

  ha1a2 U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[7]), .B(A[7]), .Y(SUM[7]) );
endmodule


module usb1_pe_DW01_inc_1 ( A, SUM );
  input [7:0] A;
  output [7:0] SUM;

  wire   [7:2] carry;

  ha1a2 U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[7]), .B(A[7]), .Y(SUM[7]) );
endmodule


module usb1_pe ( clk, rst, tx_valid, rx_active, pid_OUT, pid_IN, pid_SOF, 
        pid_SETUP, pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, pid_ACK, 
        pid_PING, token_valid, rx_data_done, crc16_err, send_token, 
        token_pid_sel, data_pid_sel, rx_dma_en, tx_dma_en, abort, idma_done, 
        fsel, ep_sel, match, nse_err, ep_full, ep_empty, int_upid_set, 
        int_crc16_set, int_to_set, int_seqerr_set, csr, send_stall );
  output [1:0] token_pid_sel;
  output [1:0] data_pid_sel;
  input [3:0] ep_sel;
  input [13:0] csr;
  input clk, rst, tx_valid, rx_active, pid_OUT, pid_IN, pid_SOF, pid_SETUP,
         pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, pid_ACK, pid_PING,
         token_valid, rx_data_done, crc16_err, idma_done, fsel, match, ep_full,
         ep_empty, send_stall;
  output send_token, rx_dma_en, tx_dma_en, abort, nse_err, int_upid_set,
         int_crc16_set, int_to_set, int_seqerr_set;
  wire   match_r, N58, send_token_d, uc_dpd_set, N60, N61, N62, N63, N64, N65,
         N66, N67, N89, N90, setup_token, N126, N127, N158, N159, pid_seq_err,
         in_token, N169, N170, rx_ack_to_clr, N172, N173, N174, N175, N176,
         N177, N178, N179, N180, N181, N182, N183, N184, N185, N186, N187,
         rx_ack_to, N189, N190, N191, N192, N193, N194, N195, N196, N197, N198,
         N199, N200, N201, N202, N203, N204, tx_data_to, pid_OUT_r, pid_IN_r,
         pid_PING_r, pid_SETUP_r, N205, int_seqerr_set_d, send_stall_r, n43,
         n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
         n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
         n72, n73, n74, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
         n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
         n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
         n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
         n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
         n134, n135, n136, n137, n138, n139, n140, n141, n142, n1, n2, n3, n4,
         n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19,
         n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
         n34, n35, n36, n37, n38, n39, n40, n41, n42, n75, n143, n144, n145,
         n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
         n157;
  wire   [1:0] token_pid_sel_d;
  wire   [1:0] ep0_dpid;
  wire   [1:0] next_dpid;
  wire   [1:0] ep1_dpid;
  wire   [1:0] ep2_dpid;
  wire   [1:0] ep3_dpid;
  wire   [1:0] ep4_dpid;
  wire   [1:0] ep5_dpid;
  wire   [1:0] ep6_dpid;
  wire   [1:0] ep7_dpid;
  wire   [1:0] uc_dpd;
  wire   [9:0] state;
  wire   [7:0] rx_ack_to_cnt;
  wire   [7:0] tx_data_to_cnt;

  and3c3 U20 ( .C(ep_empty), .A(csr[12]), .B(csr[13]), .Y(n45) );
  ao4f3 U34 ( .A(rx_ack_to), .B(n29), .C(n28), .D(n149), .Y(n65) );
  and2b2 U35 ( .B(n66), .A(n18), .Y(n52) );
  ao4f3 U38 ( .A(n72), .B(n30), .C(n25), .D(n67), .Y(n71) );
  ao2i3 U42 ( .A(n64), .B(n34), .C(n37), .D(n74), .Y(n70) );
  ao2i3 U48 ( .A(idma_done), .B(n28), .C(n77), .D(n78), .Y(n76) );
  or2b2 U53 ( .B(pid_SETUP), .A(n81), .Y(n138) );
  ao4e3 U56 ( .B(data_pid_sel[1]), .A(n82), .C(data_pid_sel[1]), .D(n83), .Y(
        n140) );
  and2b2 U73 ( .B(crc16_err), .A(n154), .Y(int_crc16_set) );
  oa4f3 U76 ( .A(ep4_dpid[1]), .B(n96), .C(ep5_dpid[1]), .D(n97), .Y(n95) );
  oa4f3 U77 ( .A(ep6_dpid[1]), .B(n75), .C(ep7_dpid[1]), .D(n146), .Y(n94) );
  oa4f3 U79 ( .A(ep0_dpid[1]), .B(n96), .C(ep1_dpid[1]), .D(n97), .Y(n99) );
  oa4f3 U80 ( .A(ep2_dpid[1]), .B(n75), .C(ep3_dpid[1]), .D(n146), .Y(n98) );
  oa4f3 U83 ( .A(ep4_dpid[0]), .B(n96), .C(ep5_dpid[0]), .D(n97), .Y(n103) );
  oa4f3 U84 ( .A(ep6_dpid[0]), .B(n75), .C(ep7_dpid[0]), .D(n146), .Y(n102) );
  oa4f3 U86 ( .A(ep0_dpid[0]), .B(n96), .C(ep1_dpid[0]), .D(n97), .Y(n105) );
  oa4f3 U87 ( .A(ep2_dpid[0]), .B(n75), .C(ep3_dpid[0]), .D(n146), .Y(n104) );
  and2b2 U101 ( .B(uc_dpd_set), .A(ep_sel[3]), .Y(n109) );
  or2b2 U106 ( .B(pid_SOF), .A(match_r), .Y(n44) );
  and2b2 U110 ( .B(N196), .A(rx_active), .Y(N204) );
  and2b2 U111 ( .B(N195), .A(rx_active), .Y(N203) );
  and2b2 U112 ( .B(N194), .A(rx_active), .Y(N202) );
  and2b2 U113 ( .B(N193), .A(rx_active), .Y(N201) );
  and2b2 U114 ( .B(N192), .A(rx_active), .Y(N200) );
  and2b2 U115 ( .B(N191), .A(rx_active), .Y(N199) );
  and2b2 U116 ( .B(N190), .A(rx_active), .Y(N198) );
  and2b2 U117 ( .B(N189), .A(rx_active), .Y(N197) );
  and2b2 U118 ( .B(N179), .A(rx_ack_to_clr), .Y(N187) );
  and2b2 U119 ( .B(N178), .A(rx_ack_to_clr), .Y(N186) );
  and2b2 U120 ( .B(N177), .A(rx_ack_to_clr), .Y(N185) );
  and2b2 U121 ( .B(N176), .A(rx_ack_to_clr), .Y(N184) );
  and2b2 U122 ( .B(N175), .A(rx_ack_to_clr), .Y(N183) );
  and2b2 U123 ( .B(N174), .A(rx_ack_to_clr), .Y(N182) );
  and2b2 U124 ( .B(N173), .A(rx_ack_to_clr), .Y(N181) );
  and2b2 U125 ( .B(N172), .A(rx_ack_to_clr), .Y(N180) );
  or2b2 U126 ( .B(n115), .A(n116), .Y(N170) );
  ao2i3 U136 ( .A(pid_DATA2), .B(n121), .C(n122), .D(n123), .Y(N158) );
  or3a3 U137 ( .A(n124), .B(setup_token), .C(n125), .Y(n123) );
  oa4f3 U138 ( .A(n20), .B(uc_dpd[1]), .C(n126), .D(uc_dpd[0]), .Y(n124) );
  ao4f3 U143 ( .A(uc_dpd[0]), .B(n127), .C(n129), .D(n125), .Y(N126) );
  or2b2 U144 ( .B(csr[9]), .A(n147), .Y(n125) );
  fdf1a6 rx_ack_to_clr_reg ( .D(N170), .CLK(n7), .Q(rx_ack_to_clr) );
  fdf1a6 \next_dpid_reg[0]  ( .D(N126), .CLK(n9), .Q(next_dpid[0]) );
  fdf1a6 \next_dpid_reg[1]  ( .D(N127), .CLK(n10), .Q(next_dpid[1]) );
  usb1_pe_DW01_inc_0 add_547 ( .A(tx_data_to_cnt), .SUM({N196, N195, N194, 
        N193, N192, N191, N190, N189}) );
  usb1_pe_DW01_inc_1 add_530 ( .A(rx_ack_to_cnt), .SUM({N179, N178, N177, N176, 
        N175, N174, N173, N172}) );
  fdef2a3 \ep0_dpid_reg[0]  ( .D(next_dpid[0]), .E(N60), .CLK(n9), .CLR(n3), 
        .Q(ep0_dpid[0]) );
  fdef2a3 \ep1_dpid_reg[0]  ( .D(next_dpid[0]), .E(N61), .CLK(n9), .CLR(n3), 
        .Q(ep1_dpid[0]) );
  fdef2a3 \ep2_dpid_reg[0]  ( .D(next_dpid[0]), .E(N62), .CLK(n9), .CLR(n3), 
        .Q(ep2_dpid[0]) );
  fdef2a3 \ep3_dpid_reg[0]  ( .D(next_dpid[0]), .E(N63), .CLK(n9), .CLR(n3), 
        .Q(ep3_dpid[0]) );
  fdef2a3 \ep4_dpid_reg[0]  ( .D(next_dpid[0]), .E(N64), .CLK(n9), .CLR(n2), 
        .Q(ep4_dpid[0]) );
  fdef2a3 \ep5_dpid_reg[0]  ( .D(next_dpid[0]), .E(N65), .CLK(n9), .CLR(n3), 
        .Q(ep5_dpid[0]) );
  fdef2a3 \ep6_dpid_reg[0]  ( .D(next_dpid[0]), .E(N66), .CLK(n9), .CLR(n2), 
        .Q(ep6_dpid[0]) );
  fdef2a3 \ep7_dpid_reg[0]  ( .D(next_dpid[0]), .E(N67), .CLK(n10), .CLR(n2), 
        .Q(ep7_dpid[0]) );
  fdef2a3 \ep0_dpid_reg[1]  ( .D(next_dpid[1]), .E(N60), .CLK(n10), .CLR(n2), 
        .Q(ep0_dpid[1]) );
  fdef2a3 \ep1_dpid_reg[1]  ( .D(next_dpid[1]), .E(N61), .CLK(n10), .CLR(n2), 
        .Q(ep1_dpid[1]) );
  fdef2a3 \ep2_dpid_reg[1]  ( .D(next_dpid[1]), .E(N62), .CLK(n10), .CLR(n2), 
        .Q(ep2_dpid[1]) );
  fdef2a3 \ep3_dpid_reg[1]  ( .D(next_dpid[1]), .E(N63), .CLK(n10), .CLR(n2), 
        .Q(ep3_dpid[1]) );
  fdef2a3 \ep4_dpid_reg[1]  ( .D(next_dpid[1]), .E(N64), .CLK(n11), .CLR(n2), 
        .Q(ep4_dpid[1]) );
  fdef2a3 \ep5_dpid_reg[1]  ( .D(next_dpid[1]), .E(N65), .CLK(n11), .CLR(n2), 
        .Q(ep5_dpid[1]) );
  fdef2a3 \ep6_dpid_reg[1]  ( .D(next_dpid[1]), .E(N66), .CLK(n11), .CLR(n2), 
        .Q(ep6_dpid[1]) );
  fdef2a3 \ep7_dpid_reg[1]  ( .D(next_dpid[1]), .E(N67), .CLK(n11), .CLR(n2), 
        .Q(ep7_dpid[1]) );
  fdef1a3 \uc_dpd_reg[1]  ( .D(N90), .E(n153), .CLK(n10), .Q(uc_dpd[1]) );
  fdf1a3 \token_pid_sel_reg[0]  ( .D(token_pid_sel_d[0]), .CLK(n12), .Q(
        token_pid_sel[0]) );
  fdf1a3 pid_PING_r_reg ( .D(pid_PING), .CLK(n6), .Q(pid_PING_r) );
  fdf1a3 pid_SETUP_r_reg ( .D(pid_SETUP), .CLK(n6), .Q(pid_SETUP_r) );
  fdf2a3 in_token_reg ( .D(n139), .CLK(n5), .CLR(n4), .Q(in_token) );
  fdef1a3 \uc_dpd_reg[0]  ( .D(N89), .E(n153), .CLK(n9), .Q(uc_dpd[0]) );
  fdf1c3 uc_dpd_set_reg ( .D(n31), .CLK(n8), .QN(uc_dpd_set) );
  fdf1a3 \tx_data_to_cnt_reg[3]  ( .D(N200), .CLK(n5), .Q(tx_data_to_cnt[3])
         );
  fdf1a3 \tx_data_to_cnt_reg[6]  ( .D(N203), .CLK(n6), .Q(tx_data_to_cnt[6])
         );
  fdf1a3 \tx_data_to_cnt_reg[7]  ( .D(N204), .CLK(n6), .Q(tx_data_to_cnt[7])
         );
  fdf1a3 \rx_ack_to_cnt_reg[3]  ( .D(N183), .CLK(n7), .Q(rx_ack_to_cnt[3]) );
  fdf1a3 \rx_ack_to_cnt_reg[6]  ( .D(N186), .CLK(n8), .Q(rx_ack_to_cnt[6]) );
  fdf1a3 \rx_ack_to_cnt_reg[7]  ( .D(N187), .CLK(n8), .Q(rx_ack_to_cnt[7]) );
  fdf2a3 \state_reg[2]  ( .D(n132), .CLK(n8), .CLR(n3), .Q(state[2]) );
  fdf1c3 match_r_reg ( .D(n111), .CLK(n5), .QN(match_r) );
  fdf1c3 pid_OUT_r_reg ( .D(n38), .CLK(n6), .QN(pid_OUT_r) );
  fdf2a3 \state_reg[1]  ( .D(n131), .CLK(n8), .CLR(n3), .Q(state[1]) );
  fdf2a3 send_stall_r_reg ( .D(n130), .CLK(n11), .CLR(n4), .Q(send_stall_r) );
  fdf1c3 pid_IN_r_reg ( .D(n41), .CLK(n6), .QN(pid_IN_r) );
  fdf1a3 pid_seq_err_reg ( .D(n140), .CLK(n10), .Q(pid_seq_err) );
  fdf1a3 \tx_data_to_cnt_reg[1]  ( .D(N198), .CLK(n5), .Q(tx_data_to_cnt[1])
         );
  fdf1a3 \tx_data_to_cnt_reg[2]  ( .D(N199), .CLK(n5), .Q(tx_data_to_cnt[2])
         );
  fdf1a3 \tx_data_to_cnt_reg[4]  ( .D(N201), .CLK(n6), .Q(tx_data_to_cnt[4])
         );
  fdf1a3 \tx_data_to_cnt_reg[5]  ( .D(N202), .CLK(n6), .Q(tx_data_to_cnt[5])
         );
  fdf1a3 \rx_ack_to_cnt_reg[1]  ( .D(N181), .CLK(n7), .Q(rx_ack_to_cnt[1]) );
  fdf1a3 \rx_ack_to_cnt_reg[2]  ( .D(N182), .CLK(n7), .Q(rx_ack_to_cnt[2]) );
  fdf1a3 \rx_ack_to_cnt_reg[4]  ( .D(N184), .CLK(n7), .Q(rx_ack_to_cnt[4]) );
  fdf1a3 \rx_ack_to_cnt_reg[5]  ( .D(N185), .CLK(n7), .Q(rx_ack_to_cnt[5]) );
  fdef2c3 \state_reg[0]  ( .D(n68), .E(n63), .CLK(n7), .CLR(n2), .QN(state[0])
         );
  fdf2a3 \state_reg[5]  ( .D(n135), .CLK(n11), .CLR(n4), .Q(state[5]) );
  fdf2a3 \state_reg[7]  ( .D(n136), .CLK(n12), .CLR(n3), .Q(state[7]) );
  fdf2a3 \state_reg[3]  ( .D(n133), .CLK(n8), .CLR(n3), .Q(state[3]) );
  fdf1a3 tx_data_to_reg ( .D(n142), .CLK(n6), .Q(tx_data_to) );
  fdf2a3 \state_reg[8]  ( .D(n137), .CLK(n8), .CLR(n3), .Q(state[8]) );
  fdf2a3 setup_token_reg ( .D(n138), .CLK(n5), .CLR(n3), .Q(setup_token) );
  fdf1a3 abort_reg ( .D(N169), .CLK(n11), .Q(abort) );
  fdf1a3 \this_dpid_reg[1]  ( .D(N159), .CLK(n5), .Q(data_pid_sel[1]) );
  fdf1a3 \tx_data_to_cnt_reg[0]  ( .D(N197), .CLK(n5), .Q(tx_data_to_cnt[0])
         );
  fdf1a3 \rx_ack_to_cnt_reg[0]  ( .D(N180), .CLK(n7), .Q(rx_ack_to_cnt[0]) );
  fdf1a3 \token_pid_sel_reg[1]  ( .D(token_pid_sel_d[1]), .CLK(n11), .Q(
        token_pid_sel[1]) );
  fdf1a3 send_token_reg ( .D(send_token_d), .CLK(n11), .Q(send_token) );
  fdf1a3 rx_ack_to_reg ( .D(n141), .CLK(n8), .Q(rx_ack_to) );
  fdf2a3 \state_reg[4]  ( .D(n134), .CLK(n8), .CLR(n3), .Q(state[4]) );
  fdf1a3 \this_dpid_reg[0]  ( .D(N158), .CLK(n10), .Q(data_pid_sel[0]) );
  fdf1a3 int_seqerr_set_reg ( .D(int_seqerr_set_d), .CLK(n12), .Q(
        int_seqerr_set) );
  fdf1a3 nse_err_reg ( .D(N58), .CLK(n5), .Q(nse_err) );
  fdf1a3 int_upid_set_reg ( .D(N205), .CLK(n7), .Q(int_upid_set) );
  inv1a1 U3 ( .A(ep_sel[0]), .Y(n144) );
  and3d3 U4 ( .A(crc16_err), .B(tx_data_to), .C(abort), .Y(n72) );
  inv1a1 U5 ( .A(state[1]), .Y(n27) );
  and2c3 U6 ( .A(n144), .B(ep_sel[1]), .Y(n97) );
  and2c3 U7 ( .A(ep_sel[0]), .B(ep_sel[1]), .Y(n96) );
  ao4f1 U8 ( .A(n52), .B(n31), .C(n62), .D(n60), .Y(n137) );
  ao4f1 U9 ( .A(n52), .B(n36), .C(n60), .D(n61), .Y(n136) );
  or3d1 U10 ( .A(n17), .B(n43), .C(n45), .Y(n46) );
  inv1a1 U11 ( .A(n97), .Y(n143) );
  inv1a1 U12 ( .A(n96), .Y(n145) );
  inv1a1 U13 ( .A(n72), .Y(n22) );
  inv1a1 U14 ( .A(n48), .Y(n33) );
  or3d1 U15 ( .A(n119), .B(n27), .C(n120), .Y(n115) );
  and2c1 U16 ( .A(state[5]), .B(state[4]), .Y(n119) );
  and2c1 U17 ( .A(state[8]), .B(state[7]), .Y(n120) );
  inv1a1 U18 ( .A(state[7]), .Y(n36) );
  inv1a1 U19 ( .A(pid_IN_r), .Y(n23) );
  inv1a1 U21 ( .A(pid_OUT), .Y(n38) );
  clk1a3 U22 ( .A(n13), .Y(n11) );
  clk1a3 U23 ( .A(n14), .Y(n10) );
  clk1a3 U24 ( .A(n14), .Y(n9) );
  clk1a3 U25 ( .A(n15), .Y(n8) );
  clk1a3 U26 ( .A(n15), .Y(n7) );
  clk1a3 U27 ( .A(n16), .Y(n6) );
  clk1a3 U28 ( .A(n16), .Y(n5) );
  clk1a3 U29 ( .A(n13), .Y(n12) );
  and2c3 U30 ( .A(pid_SETUP), .B(pid_OUT), .Y(n73) );
  inv1a3 U31 ( .A(n60), .Y(n19) );
  and2c3 U32 ( .A(n143), .B(n110), .Y(N61) );
  and2c3 U33 ( .A(n145), .B(n110), .Y(N60) );
  inv1a3 U36 ( .A(pid_IN), .Y(n41) );
  or2c1 U37 ( .A(n51), .B(n49), .Y(n67) );
  and2c1 U39 ( .A(pid_DATA1), .B(n121), .Y(N159) );
  inv1a1 U40 ( .A(rx_data_done), .Y(n154) );
  or2c1 U41 ( .A(n46), .B(n33), .Y(send_token_d) );
  inv1a1 U43 ( .A(n127), .Y(n148) );
  clk1a3 U44 ( .A(clk), .Y(n13) );
  clk1a3 U45 ( .A(clk), .Y(n14) );
  clk1a3 U46 ( .A(clk), .Y(n15) );
  clk1a3 U47 ( .A(clk), .Y(n16) );
  oa1f3 U49 ( .A(csr[11]), .B(pid_IN), .C(csr[9]), .Y(n49) );
  and2c3 U50 ( .A(n25), .B(n49), .Y(n43) );
  oa1f3 U51 ( .A(n40), .B(csr[11]), .C(csr[10]), .Y(n51) );
  inv1a1 U52 ( .A(n73), .Y(n40) );
  or2c3 U54 ( .A(n109), .B(n152), .Y(n110) );
  ao1f1 U55 ( .A(n52), .B(n30), .C(n56), .Y(n134) );
  or3d1 U57 ( .A(n19), .B(n49), .C(n57), .Y(n56) );
  and2c1 U58 ( .A(n51), .B(n25), .Y(n57) );
  ao1f1 U59 ( .A(n52), .B(n28), .C(n54), .Y(n132) );
  or3d1 U60 ( .A(n43), .B(n150), .C(n19), .Y(n54) );
  inv1a1 U61 ( .A(n45), .Y(n150) );
  ao1f1 U62 ( .A(n52), .B(n27), .C(n53), .Y(n131) );
  or3d1 U63 ( .A(n45), .B(n43), .C(n19), .Y(n53) );
  and3d2 U64 ( .A(n30), .B(rx_data_done), .C(n22), .Y(n79) );
  and2c3 U65 ( .A(n149), .B(csr[13]), .Y(n127) );
  inv1a3 U66 ( .A(csr[12]), .Y(n149) );
  inv1a1 U67 ( .A(n44), .Y(n17) );
  inv1a3 U68 ( .A(match), .Y(n37) );
  and2c3 U69 ( .A(n106), .B(n108), .Y(N67) );
  and2c3 U70 ( .A(n107), .B(n108), .Y(N66) );
  and2c3 U71 ( .A(n143), .B(n108), .Y(N65) );
  and2c3 U72 ( .A(n145), .B(n108), .Y(N64) );
  and2c3 U74 ( .A(n106), .B(n110), .Y(N63) );
  and2c3 U75 ( .A(n107), .B(n110), .Y(N62) );
  or3d3 U78 ( .A(csr[12]), .B(n42), .C(csr[10]), .Y(n121) );
  inv1a1 U81 ( .A(pid_DATA0), .Y(n42) );
  inv1a3 U82 ( .A(n106), .Y(n146) );
  inv1a3 U85 ( .A(n107), .Y(n75) );
  or2c3 U88 ( .A(n63), .B(n37), .Y(n60) );
  or2c1 U89 ( .A(match), .B(fsel), .Y(n111) );
  inv1a1 U90 ( .A(csr[10]), .Y(n147) );
  and2c1 U91 ( .A(n117), .B(n111), .Y(N169) );
  and3d2 U92 ( .A(n118), .B(n25), .C(n115), .Y(n117) );
  or2c1 U93 ( .A(n29), .B(n28), .Y(n118) );
  and2c1 U94 ( .A(n33), .B(n35), .Y(token_pid_sel_d[1]) );
  inv1a1 U95 ( .A(n126), .Y(n20) );
  buf1a9 U96 ( .A(rst), .Y(n2) );
  or2c1 U97 ( .A(n31), .B(n36), .Y(n157) );
  buf1a9 U98 ( .A(rst), .Y(n3) );
  or2c1 U99 ( .A(n46), .B(n47), .Y(token_pid_sel_d[0]) );
  or3d1 U100 ( .A(n48), .B(n35), .C(ep_full), .Y(n47) );
  or2a2 U102 ( .A(n51), .B(n25), .Y(n50) );
  and3c1 U103 ( .C(n43), .A(n44), .B(n45), .Y(tx_dma_en) );
  and2c1 U104 ( .A(n156), .B(n157), .Y(int_to_set) );
  and3c1 U105 ( .C(n49), .A(n50), .B(n44), .Y(rx_dma_en) );
  clk1a3 U107 ( .A(rst), .Y(n4) );
  inv1a1 U108 ( .A(n63), .Y(n18) );
  or3d1 U109 ( .A(state[0]), .B(n37), .C(n39), .Y(n66) );
  inv1a1 U127 ( .A(n67), .Y(n39) );
  oa2i2 U128 ( .A(n64), .B(state[5]), .C(n65), .D(state[7]), .Y(n62) );
  or2c3 U129 ( .A(n109), .B(ep_sel[2]), .Y(n108) );
  and3c1 U130 ( .C(uc_dpd[0]), .A(setup_token), .B(n20), .Y(n129) );
  oa4a2 U131 ( .A(pid_DATA2), .B(data_pid_sel[0]), .C(pid_MDATA), .D(n32), .Y(
        n82) );
  oa4a2 U132 ( .A(data_pid_sel[0]), .B(pid_DATA0), .C(n32), .D(pid_DATA1), .Y(
        n83) );
  inv1a1 U133 ( .A(data_pid_sel[0]), .Y(n32) );
  ao1f1 U134 ( .A(n52), .B(n34), .C(n58), .Y(n135) );
  or3d1 U135 ( .A(n19), .B(state[4]), .C(n59), .Y(n58) );
  and2c1 U139 ( .A(csr[12]), .B(n22), .Y(n59) );
  ao1f1 U140 ( .A(n29), .B(n52), .C(n55), .Y(n133) );
  or3d1 U141 ( .A(state[2]), .B(n149), .C(n19), .Y(n55) );
  and2c3 U142 ( .A(n34), .B(abort), .Y(n48) );
  inv1a3 U145 ( .A(state[0]), .Y(n25) );
  inv1a3 U146 ( .A(state[2]), .Y(n28) );
  inv1a3 U147 ( .A(state[3]), .Y(n29) );
  or3d1 U148 ( .A(n125), .B(n148), .C(uc_dpd[0]), .Y(n122) );
  or2c3 U149 ( .A(in_token), .B(csr[11]), .Y(n126) );
  or2c3 U150 ( .A(ep_sel[1]), .B(ep_sel[0]), .Y(n106) );
  or2c3 U151 ( .A(ep_sel[1]), .B(n144), .Y(n107) );
  inv1a3 U152 ( .A(state[4]), .Y(n30) );
  inv1a3 U153 ( .A(state[5]), .Y(n34) );
  inv1a3 U154 ( .A(ep_sel[2]), .Y(n152) );
  ao1f2 U155 ( .A(send_token), .B(n35), .C(n155), .Y(n130) );
  inv1a1 U156 ( .A(send_stall), .Y(n155) );
  or2c3 U157 ( .A(n37), .B(n76), .Y(n63) );
  and2c3 U158 ( .A(n79), .B(n80), .Y(n78) );
  or2c1 U159 ( .A(state[0]), .B(n44), .Y(n77) );
  or3d1 U160 ( .A(n41), .B(n38), .C(setup_token), .Y(n81) );
  inv1a3 U161 ( .A(send_stall_r), .Y(n35) );
  or3d1 U162 ( .A(state[4]), .B(n72), .C(csr[12]), .Y(n61) );
  and3d2 U163 ( .A(n1), .B(abort), .C(ep_full), .Y(n64) );
  or2a2 U164 ( .A(send_stall_r), .B(pid_seq_err), .Y(n1) );
  oa1f3 U165 ( .A(n128), .B(uc_dpd[1]), .C(n125), .Y(N127) );
  and2c3 U166 ( .A(setup_token), .B(n126), .Y(n128) );
  and3c1 U167 ( .C(n69), .A(n70), .B(n71), .Y(n68) );
  or2c1 U168 ( .A(state[3]), .B(rx_ack_to), .Y(n69) );
  and2c1 U169 ( .A(n112), .B(n44), .Y(N205) );
  oa1f3 U170 ( .A(csr[9]), .B(n23), .C(n113), .Y(n112) );
  oa2i2 U171 ( .A(n147), .B(n114), .C(pid_PING_r), .D(pid_OUT_r), .Y(n113) );
  or3d1 U172 ( .A(n23), .B(n24), .C(csr[11]), .Y(n114) );
  ao1d2 U173 ( .A(n73), .B(in_token), .C(n41), .Y(n139) );
  and6a3 U174 ( .A(rx_ack_to_cnt[7]), .B(rx_ack_to_cnt[6]), .C(
        rx_ack_to_cnt[3]), .D(n26), .E(n84), .F(n85), .Y(n141) );
  inv1a1 U175 ( .A(rx_ack_to_cnt[0]), .Y(n26) );
  and2c3 U176 ( .A(rx_ack_to_cnt[2]), .B(rx_ack_to_cnt[1]), .Y(n84) );
  and2c3 U177 ( .A(rx_ack_to_cnt[5]), .B(rx_ack_to_cnt[4]), .Y(n85) );
  and6a3 U178 ( .A(tx_data_to_cnt[7]), .B(tx_data_to_cnt[6]), .C(
        tx_data_to_cnt[3]), .D(n21), .E(n86), .F(n87), .Y(n142) );
  inv1a1 U179 ( .A(tx_data_to_cnt[0]), .Y(n21) );
  and2c3 U180 ( .A(tx_data_to_cnt[2]), .B(tx_data_to_cnt[1]), .Y(n86) );
  and2c3 U181 ( .A(tx_data_to_cnt[5]), .B(tx_data_to_cnt[4]), .Y(n87) );
  inv1a3 U182 ( .A(state[8]), .Y(n31) );
  or2a2 U183 ( .A(n92), .B(n93), .Y(N90) );
  oa1f3 U184 ( .A(n94), .B(n95), .C(n152), .Y(n93) );
  oa1f3 U185 ( .A(n98), .B(n99), .C(ep_sel[2]), .Y(n92) );
  or2a2 U186 ( .A(n100), .B(n101), .Y(N89) );
  oa1f3 U187 ( .A(n102), .B(n103), .C(n152), .Y(n101) );
  oa1f3 U188 ( .A(n104), .B(n105), .C(ep_sel[2]), .Y(n100) );
  and2c3 U189 ( .A(tx_valid), .B(state[0]), .Y(n116) );
  and2c3 U190 ( .A(state[8]), .B(state[1]), .Y(n74) );
  or3d1 U191 ( .A(state[4]), .B(n29), .C(tx_data_to), .Y(n89) );
  and3c1 U192 ( .C(pid_seq_err), .A(n154), .B(n61), .Y(int_seqerr_set_d) );
  or2c1 U193 ( .A(n34), .B(n88), .Y(n156) );
  oa2i2 U194 ( .A(n89), .B(n90), .C(n91), .D(state[0]), .Y(n88) );
  or2c1 U195 ( .A(n27), .B(n28), .Y(n91) );
  or3d1 U196 ( .A(state[3]), .B(n30), .C(rx_ack_to), .Y(n90) );
  inv1a1 U197 ( .A(ep_sel[3]), .Y(n153) );
  inv1a1 U198 ( .A(pid_SETUP_r), .Y(n24) );
  oa2i2 U199 ( .A(token_valid), .B(pid_ACK), .C(n29), .D(rx_ack_to), .Y(n80)
         );
  oa2i2 U200 ( .A(n73), .B(n41), .C(n151), .D(match), .Y(N58) );
  inv1a1 U201 ( .A(token_valid), .Y(n151) );
endmodule


module usb1_pl_DW01_inc_1 ( A, SUM );
  input [11:0] A;
  output [11:0] SUM;

  wire   [11:2] carry;

  ha1a2 U1_1_10 ( .A(A[10]), .B(carry[10]), .CO(carry[11]), .S(SUM[10]) );
  ha1a2 U1_1_9 ( .A(A[9]), .B(carry[9]), .CO(carry[10]), .S(SUM[9]) );
  ha1a2 U1_1_8 ( .A(A[8]), .B(carry[8]), .CO(carry[9]), .S(SUM[8]) );
  ha1a2 U1_1_7 ( .A(A[7]), .B(carry[7]), .CO(carry[8]), .S(SUM[7]) );
  ha1a2 U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[11]), .B(A[11]), .Y(SUM[11]) );
endmodule


module usb1_pl ( clk, rst, rx_data, rx_valid, rx_active, rx_err, tx_data, 
        tx_valid, tx_valid_last, tx_ready, tx_first, tx_valid_out, token_valid, 
        fa, ep_sel, x_busy, int_crc16_set, int_to_set, int_seqerr_set, frm_nat, 
        pid_cs_err, nse_err, crc5_err, rx_size, rx_done, ctrl_setup, ctrl_in, 
        ctrl_out, ep_bf_en, ep_bf_size, dropped_frame, misaligned_frame, csr, 
        tx_data_st, rx_ctrl_data, rx_ctrl_data_d, rx_ctrl_dvalid, 
        rx_ctrl_ddone, idma_re, idma_we, ep_empty, ep_full, send_stall );
  input [7:0] rx_data;
  output [7:0] tx_data;
  input [6:0] fa;
  output [3:0] ep_sel;
  output [31:0] frm_nat;
  output [7:0] rx_size;
  input [6:0] ep_bf_size;
  input [13:0] csr;
  input [7:0] tx_data_st;
  output [7:0] rx_ctrl_data;
  output [7:0] rx_ctrl_data_d;
  input clk, rst, rx_valid, rx_active, rx_err, tx_ready, tx_valid_out,
         ep_bf_en, ep_empty, ep_full, send_stall;
  output tx_valid, tx_valid_last, tx_first, token_valid, x_busy, int_crc16_set,
         int_to_set, int_seqerr_set, pid_cs_err, nse_err, crc5_err, rx_done,
         ctrl_setup, ctrl_in, ctrl_out, dropped_frame, misaligned_frame,
         rx_ctrl_dvalid, rx_ctrl_ddone, idma_re, idma_we;
  wire   frm_nat_26, frm_nat_25, frm_nat_24, frm_nat_23, frm_nat_22,
         frm_nat_21, frm_nat_20, frm_nat_19, frm_nat_18, frm_nat_17,
         frm_nat_16, tx_busy, rx_busy, pid_ACK, pid_NACK, pid_STALL, pid_NYET,
         pid_PRE, pid_ERR, pid_SPLIT, pid_PING, match_o, pid_SETUP, N2, pid_IN,
         N3, pid_OUT, N4, pid_SOF, frame_no_we, frame_no_we_r, clr_sof_time,
         hms_clk, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N40,
         N41, N42, N43, N44, N45, N46, N47, N48, fsel, idma_we_d, pid_DATA0,
         pid_DATA1, pid_DATA2, pid_MDATA, crc16_err, send_token, send_data,
         rd_next, ep_empty_int, tx_dma_en, rx_dma_en, idma_done, n7, n8, n9,
         n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
         n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
         n38, n39, n40, \add_266/carry[4] , \add_266/carry[3] ,
         \add_266/carry[2] , n1, n2, n3, n4, n5;
  wire   [10:0] frame_no;
  wire   [4:0] hms_cnt;
  wire   [6:0] token_fadr;
  wire   [1:0] token_pid_sel;
  wire   [1:0] data_pid_sel;
  wire   [7:0] tx_data_st_o;
  assign frm_nat[12] = 1'b0;
  assign frm_nat[13] = 1'b0;
  assign frm_nat[14] = 1'b0;
  assign frm_nat[15] = 1'b0;
  assign frm_nat[27] = 1'b0;
  assign frm_nat[28] = 1'b0;
  assign frm_nat[29] = 1'b0;
  assign frm_nat[30] = 1'b0;
  assign frm_nat[31] = 1'b0;
  assign frm_nat[26] = frm_nat_26;
  assign frm_nat[25] = frm_nat_25;
  assign frm_nat[24] = frm_nat_24;
  assign frm_nat[23] = frm_nat_23;
  assign frm_nat[22] = frm_nat_22;
  assign frm_nat[21] = frm_nat_21;
  assign frm_nat[20] = frm_nat_20;
  assign frm_nat[19] = frm_nat_19;
  assign frm_nat[18] = frm_nat_18;
  assign frm_nat[17] = frm_nat_17;
  assign frm_nat[16] = frm_nat_16;
  assign dropped_frame = 1'b0;
  assign misaligned_frame = 1'b0;

  ao4a3 U15 ( .A(frm_nat[0]), .B(n7), .C(N7), .D(n8), .Y(n39) );
  xor2a2 U29 ( .A(token_fadr[5]), .B(fa[5]), .Y(n20) );
  xor2a2 U30 ( .A(token_fadr[1]), .B(fa[1]), .Y(n19) );
  xor2a2 U31 ( .A(token_fadr[0]), .B(fa[0]), .Y(n18) );
  xor2a2 U33 ( .A(token_fadr[2]), .B(fa[2]), .Y(n22) );
  xor2a2 U34 ( .A(token_fadr[3]), .B(fa[3]), .Y(n21) );
  xor2a2 U36 ( .A(token_fadr[6]), .B(fa[6]), .Y(n24) );
  xor2a2 U37 ( .A(token_fadr[4]), .B(fa[4]), .Y(n23) );
  and2b2 U39 ( .B(N43), .A(n25), .Y(N48) );
  and2b2 U40 ( .B(N42), .A(n25), .Y(N47) );
  and2b2 U41 ( .B(N41), .A(n25), .Y(N46) );
  and2b2 U42 ( .B(N40), .A(n25), .Y(N45) );
  and2b2 U45 ( .B(pid_OUT), .A(n26), .Y(N4) );
  and2b2 U46 ( .B(pid_IN), .A(n26), .Y(N3) );
  and2b2 U47 ( .B(pid_SETUP), .A(n26), .Y(N2) );
  usb1_pd u0 ( .clk(n3), .rst(n2), .rx_data(rx_data), .rx_valid(rx_valid), 
        .rx_active(rx_active), .rx_err(rx_err), .pid_OUT(pid_OUT), .pid_IN(
        pid_IN), .pid_SOF(pid_SOF), .pid_SETUP(pid_SETUP), .pid_DATA0(
        pid_DATA0), .pid_DATA1(pid_DATA1), .pid_DATA2(pid_DATA2), .pid_MDATA(
        pid_MDATA), .pid_ACK(pid_ACK), .pid_NACK(pid_NACK), .pid_STALL(
        pid_STALL), .pid_NYET(pid_NYET), .pid_PRE(pid_PRE), .pid_ERR(pid_ERR), 
        .pid_SPLIT(pid_SPLIT), .pid_PING(pid_PING), .pid_cks_err(pid_cs_err), 
        .token_fadr(token_fadr), .token_endp(ep_sel), .token_valid(token_valid), .crc5_err(crc5_err), .frame_no(frame_no), .rx_data_st(rx_ctrl_data), 
        .rx_data_valid(rx_ctrl_dvalid), .rx_data_done(rx_ctrl_ddone), 
        .crc16_err(crc16_err), .rx_busy(rx_busy) );
  usb1_pa u1 ( .clk(n3), .rst(n2), .tx_data(tx_data), .tx_valid(tx_valid), 
        .tx_valid_last(tx_valid_last), .tx_ready(tx_ready), .tx_first(tx_first), .send_token(send_token), .token_pid_sel(token_pid_sel), .send_data(send_data), .data_pid_sel(data_pid_sel), .tx_data_st(tx_data_st_o), .rd_next(rd_next), 
        .ep_empty(ep_empty_int) );
  usb1_idma u2 ( .clk(n3), .rst(n2), .rx_data_valid(rx_ctrl_dvalid), 
        .rx_data_done(rx_ctrl_ddone), .send_data(send_data), .rd_next(rd_next), 
        .tx_valid(tx_valid), .tx_data_st_i(tx_data_st), .tx_data_st_o(
        tx_data_st_o), .tx_dma_en(tx_dma_en), .rx_dma_en(rx_dma_en), 
        .idma_done(idma_done), .ep_sel(ep_sel), .size(csr[8:0]), .rx_cnt(
        rx_size), .rx_done(rx_done), .tx_busy(tx_busy), .ep_bf_en(ep_bf_en), 
        .ep_bf_size(ep_bf_size), .mwe(idma_we_d), .mre(idma_re), .ep_empty(
        ep_empty), .ep_empty_int(ep_empty_int), .ep_full(ep_full) );
  usb1_pe u3 ( .clk(n3), .rst(n2), .tx_valid(tx_valid_out), .rx_active(
        rx_active), .pid_OUT(pid_OUT), .pid_IN(pid_IN), .pid_SOF(pid_SOF), 
        .pid_SETUP(pid_SETUP), .pid_DATA0(pid_DATA0), .pid_DATA1(pid_DATA1), 
        .pid_DATA2(pid_DATA2), .pid_MDATA(pid_MDATA), .pid_ACK(pid_ACK), 
        .pid_PING(pid_PING), .token_valid(token_valid), .rx_data_done(
        rx_ctrl_ddone), .crc16_err(crc16_err), .send_token(send_token), 
        .token_pid_sel(token_pid_sel), .data_pid_sel(data_pid_sel), 
        .rx_dma_en(rx_dma_en), .tx_dma_en(tx_dma_en), .idma_done(idma_done), 
        .fsel(fsel), .ep_sel(ep_sel), .match(match_o), .nse_err(nse_err), 
        .ep_full(ep_full), .ep_empty(ep_empty), .int_crc16_set(int_crc16_set), 
        .int_to_set(int_to_set), .int_seqerr_set(int_seqerr_set), .csr(csr), 
        .send_stall(send_stall) );
  usb1_pl_DW01_inc_1 add_257_S2 ( .A(frm_nat[11:0]), .SUM({N18, N17, N16, N15, 
        N14, N13, N12, N11, N10, N9, N8, N7}) );
  ha1a2 \add_266/U1_1_1  ( .A(hms_cnt[1]), .B(hms_cnt[0]), .CO(
        \add_266/carry[2] ), .S(N40) );
  ha1a2 \add_266/U1_1_2  ( .A(hms_cnt[2]), .B(\add_266/carry[2] ), .CO(
        \add_266/carry[3] ), .S(N41) );
  ha1a2 \add_266/U1_1_3  ( .A(hms_cnt[3]), .B(\add_266/carry[3] ), .CO(
        \add_266/carry[4] ), .S(N42) );
  fdef2a3 \frame_no_r_reg[8]  ( .D(frame_no[8]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_24) );
  fdef2a3 \frame_no_r_reg[2]  ( .D(frame_no[2]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_18) );
  fdef2a3 \frame_no_r_reg[1]  ( .D(frame_no[1]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_17) );
  fdef2a3 \frame_no_r_reg[0]  ( .D(frame_no[0]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_16) );
  fdef2a3 \frame_no_r_reg[7]  ( .D(frame_no[7]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_23) );
  fdef2a3 \frame_no_r_reg[6]  ( .D(frame_no[6]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_22) );
  fdef2a3 \frame_no_r_reg[5]  ( .D(frame_no[5]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_21) );
  fdef2a3 \frame_no_r_reg[4]  ( .D(frame_no[4]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_20) );
  fdef2a3 \frame_no_r_reg[3]  ( .D(frame_no[3]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_19) );
  fdef2a3 \frame_no_r_reg[10]  ( .D(frame_no[10]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_26) );
  fdef2a3 \frame_no_r_reg[9]  ( .D(frame_no[9]), .E(frame_no_we_r), .CLK(n3), 
        .CLR(n2), .Q(frm_nat_25) );
  fdf2a3 \hms_cnt_reg[3]  ( .D(N47), .CLK(n3), .CLR(n2), .Q(hms_cnt[3]) );
  fdf2a3 \hms_cnt_reg[1]  ( .D(N45), .CLK(n3), .CLR(n2), .Q(hms_cnt[1]) );
  fdf2a3 \hms_cnt_reg[4]  ( .D(N48), .CLK(n3), .CLR(n2), .Q(hms_cnt[4]) );
  fdf2a3 \hms_cnt_reg[2]  ( .D(N46), .CLK(n3), .CLR(n2), .Q(hms_cnt[2]) );
  fdf1a3 ctrl_out_reg ( .D(N4), .CLK(n3), .Q(ctrl_out) );
  fdf1a3 hms_clk_reg ( .D(n40), .CLK(n3), .Q(hms_clk) );
  fdf1a3 \sof_time_reg[1]  ( .D(n38), .CLK(n3), .Q(frm_nat[1]) );
  fdf1a3 \sof_time_reg[2]  ( .D(n37), .CLK(n3), .Q(frm_nat[2]) );
  fdf1a3 \sof_time_reg[3]  ( .D(n36), .CLK(n3), .Q(frm_nat[3]) );
  fdf1a3 \sof_time_reg[4]  ( .D(n35), .CLK(n3), .Q(frm_nat[4]) );
  fdf1a3 \sof_time_reg[5]  ( .D(n34), .CLK(n3), .Q(frm_nat[5]) );
  fdf1a3 \sof_time_reg[6]  ( .D(n33), .CLK(n3), .Q(frm_nat[6]) );
  fdf1a3 \sof_time_reg[7]  ( .D(n32), .CLK(n3), .Q(frm_nat[7]) );
  fdf1a3 \sof_time_reg[8]  ( .D(n31), .CLK(n3), .Q(frm_nat[8]) );
  fdf1a3 \sof_time_reg[9]  ( .D(n30), .CLK(n3), .Q(frm_nat[9]) );
  fdf1a3 \sof_time_reg[10]  ( .D(n29), .CLK(n3), .Q(frm_nat[10]) );
  fdf1a3 \sof_time_reg[11]  ( .D(n28), .CLK(n3), .Q(frm_nat[11]) );
  fdf2a3 \hms_cnt_reg[0]  ( .D(N44), .CLK(n3), .CLR(n2), .Q(hms_cnt[0]) );
  fdf1a3 clr_sof_time_reg ( .D(frame_no_we), .CLK(n3), .Q(clr_sof_time) );
  fdf1a3 \sof_time_reg[0]  ( .D(n39), .CLK(n3), .Q(frm_nat[0]) );
  fdf1a3 ctrl_setup_reg ( .D(N2), .CLK(n3), .Q(ctrl_setup) );
  fdf1a9 frame_no_we_r_reg ( .D(frame_no_we), .CLK(n3), .Q(frame_no_we_r) );
  fdf1a3 ctrl_in_reg ( .D(N3), .CLK(n3), .Q(ctrl_in) );
  fdf1a9 \rx_ctrl_data_d_reg[1]  ( .D(rx_ctrl_data[1]), .CLK(n3), .Q(
        rx_ctrl_data_d[1]) );
  fdf1a9 \rx_ctrl_data_d_reg[2]  ( .D(rx_ctrl_data[2]), .CLK(n3), .Q(
        rx_ctrl_data_d[2]) );
  fdf1a9 \rx_ctrl_data_d_reg[3]  ( .D(rx_ctrl_data[3]), .CLK(n3), .Q(
        rx_ctrl_data_d[3]) );
  fdf1a9 \rx_ctrl_data_d_reg[4]  ( .D(rx_ctrl_data[4]), .CLK(n3), .Q(
        rx_ctrl_data_d[4]) );
  fdf1a9 \rx_ctrl_data_d_reg[5]  ( .D(rx_ctrl_data[5]), .CLK(n3), .Q(
        rx_ctrl_data_d[5]) );
  fdf1a9 \rx_ctrl_data_d_reg[6]  ( .D(rx_ctrl_data[6]), .CLK(n3), .Q(
        rx_ctrl_data_d[6]) );
  fdf1a9 \rx_ctrl_data_d_reg[7]  ( .D(rx_ctrl_data[7]), .CLK(n3), .Q(
        rx_ctrl_data_d[7]) );
  fdf1a9 \rx_ctrl_data_d_reg[0]  ( .D(rx_ctrl_data[0]), .CLK(n3), .Q(
        rx_ctrl_data_d[0]) );
  and2c3 U3 ( .A(hms_cnt[0]), .B(n25), .Y(N44) );
  clk1b6 U4 ( .A(n1), .Y(n7) );
  or2a1 U5 ( .A(clr_sof_time), .B(n8), .Y(n1) );
  ao4a1 U6 ( .A(frm_nat[10]), .B(n7), .C(N17), .D(n8), .Y(n29) );
  ao4a1 U7 ( .A(frm_nat[9]), .B(n7), .C(N16), .D(n8), .Y(n30) );
  ao4a1 U8 ( .A(frm_nat[8]), .B(n7), .C(N15), .D(n8), .Y(n31) );
  ao4a1 U9 ( .A(frm_nat[7]), .B(n7), .C(N14), .D(n8), .Y(n32) );
  ao4a1 U10 ( .A(frm_nat[6]), .B(n7), .C(N13), .D(n8), .Y(n33) );
  ao4a1 U11 ( .A(frm_nat[5]), .B(n7), .C(N12), .D(n8), .Y(n34) );
  ao4a1 U12 ( .A(frm_nat[4]), .B(n7), .C(N11), .D(n8), .Y(n35) );
  ao4a1 U13 ( .A(frm_nat[3]), .B(n7), .C(N10), .D(n8), .Y(n36) );
  ao4a1 U14 ( .A(frm_nat[2]), .B(n7), .C(N9), .D(n8), .Y(n37) );
  ao4a1 U16 ( .A(frm_nat[1]), .B(n7), .C(N8), .D(n8), .Y(n38) );
  ao4a1 U17 ( .A(frm_nat[11]), .B(n7), .C(N18), .D(n8), .Y(n28) );
  inv1a1 U18 ( .A(crc5_err), .Y(n4) );
  and3d2 U19 ( .A(pid_ACK), .B(pid_NACK), .C(pid_ERR), .Y(n12) );
  and3d2 U20 ( .A(pid_PRE), .B(pid_STALL), .C(pid_SPLIT), .Y(n14) );
  and3a2 U21 ( .A(n15), .B(n16), .C(n17), .Y(fsel) );
  and2c1 U22 ( .A(n23), .B(n24), .Y(n15) );
  and2c3 U23 ( .A(n21), .B(n22), .Y(n16) );
  and3d2 U24 ( .A(n18), .B(n19), .C(n20), .Y(n17) );
  buf1a27 U25 ( .A(clk), .Y(n3) );
  and2a3 U26 ( .A(idma_we_d), .B(fsel), .Y(idma_we) );
  or2a2 U27 ( .A(hms_clk), .B(frame_no_we_r), .Y(n25) );
  and2c3 U28 ( .A(n10), .B(n11), .Y(match_o) );
  or2c1 U32 ( .A(n13), .B(n14), .Y(n10) );
  or3d1 U35 ( .A(token_valid), .B(n4), .C(n12), .Y(n11) );
  and2c1 U38 ( .A(pid_PING), .B(pid_NYET), .Y(n13) );
  and2b6 U43 ( .B(hms_clk), .A(clr_sof_time), .Y(n8) );
  or3d3 U44 ( .A(token_valid), .B(n5), .C(n27), .Y(n26) );
  inv1a1 U48 ( .A(ep_sel[0]), .Y(n5) );
  and3d2 U49 ( .A(ep_sel[1]), .B(ep_sel[3]), .C(ep_sel[2]), .Y(n27) );
  and3a2 U50 ( .A(pid_SOF), .B(n4), .C(token_valid), .Y(frame_no_we) );
  clk1a15 U51 ( .A(rst), .Y(n2) );
  and3a2 U52 ( .A(hms_cnt[4]), .B(hms_cnt[2]), .C(n9), .Y(n40) );
  and3c1 U53 ( .C(hms_cnt[1]), .A(hms_cnt[3]), .B(hms_cnt[0]), .Y(n9) );
  or2a2 U54 ( .A(rx_busy), .B(tx_busy), .Y(x_busy) );
  xor2a1 U55 ( .A(\add_266/carry[4] ), .B(hms_cnt[4]), .Y(N43) );
endmodule


module usb1_ctrl_DW01_inc_1 ( A, SUM );
  input [6:0] A;
  output [6:0] SUM;

  wire   [6:2] carry;

  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[6]), .B(A[6]), .Y(SUM[6]) );
endmodule


module usb1_ctrl ( clk, rst, rom_adr, rom_data, ctrl_setup, ctrl_in, ctrl_out, 
        rx_ctrl_data, rx_ctrl_dvalid, rx_ctrl_ddone, ep0_din, ep0_dout, ep0_re, 
        ep0_we, ep0_stat, ep0_size, send_stall, frame_no, funct_adr, 
        configured, halt, v_set_int, v_set_feature, wValue, wIndex, 
        vendor_data, reg_addr, reg_rdwrn, reg_req, reg_wdata, reg_rdata, 
        reg_ack );
  output [6:0] rom_adr;
  input [7:0] rom_data;
  input [7:0] rx_ctrl_data;
  input [7:0] ep0_din;
  output [7:0] ep0_dout;
  input [3:0] ep0_stat;
  output [7:0] ep0_size;
  input [10:0] frame_no;
  output [6:0] funct_adr;
  output [15:0] wValue;
  output [15:0] wIndex;
  input [15:0] vendor_data;
  output [31:0] reg_addr;
  output [31:0] reg_wdata;
  input [31:0] reg_rdata;
  input clk, rst, ctrl_setup, ctrl_in, ctrl_out, rx_ctrl_dvalid, rx_ctrl_ddone,
         reg_ack;
  output ep0_re, ep0_we, send_stall, configured, halt, v_set_int,
         v_set_feature, reg_rdwrn, reg_req;
  wire   set_address, set_config, rom_sel_r, N168, N169, N170, N171, N172,
         N173, N174, N190, N191, N192, N193, N194, N195, N196, fifo_we_rom_r,
         fifo_we_rom_r2, reg_wphase, high_sel, N260, N261, N262, N263, N264,
         N265, N266, N267, N268, N290, N291, N292, N293, hdr_done_r, N317,
         get_status, N318, clear_feature, N319, set_feature, N320, N321,
         get_descriptor, N322, set_descriptor, N323, get_config, N324, N325,
         get_interface, N326, set_interface, N327, synch_frame, N328, N329,
         N330, v_get_status, N331, v_set_reg_waddr, N332, v_set_reg_raddr,
         N351, N353, N361, config_err, set_adr_pending, n104, n105, n106, n107,
         n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
         n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
         n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
         n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
         n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
         n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
         n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
         n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
         n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
         n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
         n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
         n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
         n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250,
         n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261,
         n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272,
         n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
         n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294,
         n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
         n306, n307, n308, n309, n310, n311, n312, n313, n314, n316, n317,
         n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
         n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
         n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
         n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
         n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
         n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383,
         n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394,
         n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405,
         n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416,
         n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
         n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438,
         n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
         n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460,
         n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
         n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
         \gt_309/A[4] , \gt_309/A[3] , \gt_309/A[1] , \add_428/carry[3] ,
         \add_428/carry[2] , n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
         n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
         n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
         n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
         n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
         n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82,
         n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96,
         n97, n98, n99, n100, n101, n102, n103, n315, n482, n483, n484, n485,
         n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
         n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
         n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
         n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
         n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
         n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
         n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
         n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573;
  wire   [5:0] rom_size_dd;
  wire   [6:0] rom_size;
  wire   [7:0] le;
  wire   [6:0] hdr0;
  wire   [7:0] hdr1;
  wire   [6:0] hdr6;
  wire   [31:0] reg_rdata_r;
  wire   [3:0] tx_bcnt;
  wire   [19:0] state;
  wire   [1:0] reg_byte_cnt;
  wire   [6:0] funct_adr_tmp;
  assign ep0_size[7] = 1'b0;

  ao4f3 U6 ( .A(n537), .B(n108), .C(reg_byte_cnt[0]), .D(n109), .Y(n409) );
  oa4f3 U14 ( .A(N195), .B(n488), .C(n527), .D(n114), .Y(n113) );
  oa4f3 U16 ( .A(N194), .B(n488), .C(n527), .D(n116), .Y(n115) );
  oa4f3 U18 ( .A(N193), .B(n488), .C(n527), .D(n118), .Y(n117) );
  oa4f3 U20 ( .A(n527), .B(n120), .C(N192), .D(n488), .Y(n119) );
  oa4f3 U22 ( .A(n527), .B(n122), .C(N191), .D(n488), .Y(n121) );
  oa4f3 U24 ( .A(n527), .B(n124), .C(N190), .D(n488), .Y(n123) );
  xor2b2 U34 ( .A(n529), .B(wValue[8]), .Y(n129) );
  oa4f3 U53 ( .A(n557), .B(n509), .C(n508), .D(n124), .Y(n144) );
  ao4e3 U84 ( .B(wValue[3]), .A(n159), .C(n545), .D(n160), .Y(n436) );
  ao4e3 U85 ( .B(wValue[2]), .A(n159), .C(n546), .D(n160), .Y(n437) );
  ao4f3 U86 ( .A(n547), .B(n160), .C(n159), .D(n522), .Y(n438) );
  ao4f3 U87 ( .A(n548), .B(n160), .C(n159), .D(n521), .Y(n439) );
  ao4f3 U89 ( .A(n164), .B(n511), .C(n165), .D(n166), .Y(n440) );
  ao4f3 U94 ( .A(n164), .B(n532), .C(n169), .D(n531), .Y(n441) );
  ao4f3 U95 ( .A(n164), .B(n531), .C(n169), .D(n530), .Y(n442) );
  ao4f3 U96 ( .A(n164), .B(n530), .C(n169), .D(n523), .Y(n443) );
  oa4f3 U105 ( .A(rom_size_dd[5]), .B(n527), .C(rom_adr[4]), .D(n489), .Y(n179) );
  ao2i3 U112 ( .A(n182), .B(n528), .C(n183), .D(n184), .Y(n448) );
  and2b2 U121 ( .B(wValue[8]), .A(n529), .Y(n132) );
  ao4a3 U123 ( .A(rom_adr[3]), .B(n489), .C(N171), .D(n488), .Y(n450) );
  and2b2 U127 ( .B(rom_sel_r), .A(n191), .Y(n190) );
  ao4f3 U128 ( .A(n164), .B(n523), .C(n169), .D(n518), .Y(n451) );
  ao4f3 U129 ( .A(n164), .B(n518), .C(n169), .D(n513), .Y(n452) );
  ao4f3 U130 ( .A(n164), .B(n513), .C(n511), .D(n169), .Y(n453) );
  ao4e3 U140 ( .B(le[7]), .A(n164), .C(n169), .D(n532), .Y(n456) );
  or3d6 U141 ( .A(n20), .B(n169), .C(state[1]), .Y(n164) );
  or3d6 U142 ( .A(n20), .B(ep0_re), .C(state[1]), .Y(n169) );
  ao4e3 U145 ( .B(n199), .A(tx_bcnt[1]), .C(n491), .D(n567), .Y(n458) );
  ao4f3 U146 ( .A(n504), .B(n200), .C(tx_bcnt[0]), .D(n201), .Y(n459) );
  ao4f3 U153 ( .A(ctrl_setup), .B(n563), .C(n486), .D(n554), .Y(n208) );
  ao2i3 U170 ( .A(n24), .B(n227), .C(n228), .D(n229), .Y(n465) );
  ao4f3 U184 ( .A(n486), .B(n552), .C(n242), .D(n556), .Y(n241) );
  ao4f3 U188 ( .A(n486), .B(n551), .C(n539), .D(n558), .Y(n244) );
  ao4f3 U203 ( .A(n566), .B(n212), .C(n262), .D(n484), .Y(n472) );
  ao4f3 U207 ( .A(n509), .B(n212), .C(n266), .D(n484), .Y(n473) );
  oa4f3 U210 ( .A(n271), .B(state[14]), .C(state[0]), .D(v_set_reg_waddr), .Y(
        n270) );
  ao4e3 U211 ( .B(state[15]), .A(n272), .C(n566), .D(n484), .Y(n474) );
  ao4e3 U226 ( .B(state[19]), .A(n484), .C(n284), .D(n565), .Y(n477) );
  oa1f6 U234 ( .A(n267), .B(n20), .C(n486), .Y(n202) );
  or2b2 U235 ( .B(n234), .A(n227), .Y(n267) );
  ao4f3 U238 ( .A(n201), .B(n505), .C(n200), .D(n290), .Y(n479) );
  ao2i3 U246 ( .A(n295), .B(n296), .C(n201), .D(n20), .Y(n200) );
  xor2a2 U256 ( .A(ep0_size[2]), .B(N291), .Y(n309) );
  xor2a2 U257 ( .A(ep0_size[0]), .B(n504), .Y(n308) );
  xor2b2 U258 ( .A(ep0_size[1]), .B(N290), .Y(n306) );
  xor2b2 U259 ( .A(ep0_size[4]), .B(N293), .Y(n305) );
  xor2a2 U260 ( .A(ep0_size[3]), .B(N292), .Y(n303) );
  and2b2 U264 ( .B(n226), .A(n242), .Y(n271) );
  ao2i3 U279 ( .A(n300), .B(n490), .C(n322), .D(n323), .Y(n321) );
  oa4f3 U280 ( .A(state[15]), .B(n571), .C(state[19]), .D(n487), .Y(n323) );
  and2b2 U326 ( .B(n329), .A(hdr1[4]), .Y(n335) );
  oa4f3 U347 ( .A(vendor_data[15]), .B(n356), .C(rom_data[7]), .D(n525), .Y(
        n344) );
  oa4f3 U352 ( .A(reg_rdata_r[22]), .B(n353), .C(reg_rdata_r[30]), .D(n354), 
        .Y(n361) );
  oa4f3 U354 ( .A(vendor_data[14]), .B(n356), .C(rom_data[6]), .D(n525), .Y(
        n357) );
  oa4f3 U358 ( .A(reg_rdata_r[5]), .B(n351), .C(reg_rdata_r[13]), .D(n352), 
        .Y(n368) );
  oa4f3 U359 ( .A(reg_rdata_r[21]), .B(n353), .C(reg_rdata_r[29]), .D(n354), 
        .Y(n367) );
  oa4f3 U361 ( .A(vendor_data[13]), .B(n356), .C(rom_data[5]), .D(n525), .Y(
        n363) );
  oa4f3 U365 ( .A(reg_rdata_r[4]), .B(n351), .C(reg_rdata_r[12]), .D(n352), 
        .Y(n374) );
  oa4f3 U366 ( .A(reg_rdata_r[20]), .B(n353), .C(reg_rdata_r[28]), .D(n354), 
        .Y(n373) );
  oa4f3 U368 ( .A(vendor_data[12]), .B(n356), .C(rom_data[4]), .D(n525), .Y(
        n369) );
  oa4f3 U372 ( .A(reg_rdata_r[3]), .B(n351), .C(reg_rdata_r[11]), .D(n352), 
        .Y(n380) );
  oa4f3 U373 ( .A(reg_rdata_r[19]), .B(n353), .C(reg_rdata_r[27]), .D(n354), 
        .Y(n379) );
  oa4f3 U375 ( .A(vendor_data[11]), .B(n356), .C(rom_data[3]), .D(n525), .Y(
        n375) );
  oa4f3 U381 ( .A(reg_rdata_r[2]), .B(n351), .C(reg_rdata_r[10]), .D(n352), 
        .Y(n387) );
  oa4f3 U383 ( .A(frame_no[2]), .B(n355), .C(vendor_data[2]), .D(n347), .Y(
        n381) );
  oa4f3 U390 ( .A(reg_rdata_r[1]), .B(n351), .C(reg_rdata_r[9]), .D(n352), .Y(
        n394) );
  oa4f3 U392 ( .A(frame_no[1]), .B(n355), .C(vendor_data[1]), .D(n347), .Y(
        n388) );
  and3a3 U397 ( .A(n402), .B(tx_bcnt[1]), .C(n504), .Y(n352) );
  ao1f6 U398 ( .A(n504), .B(n567), .C(n402), .Y(n351) );
  oa4f3 U399 ( .A(reg_rdata_r[16]), .B(n353), .C(reg_rdata_r[24]), .D(n354), 
        .Y(n400) );
  and3a3 U400 ( .A(n402), .B(n504), .C(n567), .Y(n354) );
  and3a3 U401 ( .A(n402), .B(tx_bcnt[0]), .C(n567), .Y(n353) );
  oa4f3 U405 ( .A(n405), .B(n406), .C(frame_no[8]), .D(state[12]), .Y(n403) );
  and2a6 U409 ( .A(state[17]), .B(n505), .Y(n347) );
  oa4f3 U410 ( .A(rom_data[0]), .B(n525), .C(frame_no[0]), .D(n355), .Y(n395)
         );
  or3a3 U414 ( .A(wValue[13]), .B(wValue[15]), .C(wValue[14]), .Y(n407) );
  fdf1a6 \state_reg[1]  ( .D(n460), .CLK(n29), .Q(state[1]) );
  fdef1a15 \reg_wdata_reg[7]  ( .D(ep0_din[7]), .E(n6), .CLK(n41), .Q(
        reg_wdata[7]) );
  fdef1a15 \reg_wdata_reg[6]  ( .D(ep0_din[6]), .E(n6), .CLK(n41), .Q(
        reg_wdata[6]) );
  fdef1a15 \reg_wdata_reg[5]  ( .D(ep0_din[5]), .E(n6), .CLK(n41), .Q(
        reg_wdata[5]) );
  fdef1a15 \reg_wdata_reg[4]  ( .D(ep0_din[4]), .E(n6), .CLK(n41), .Q(
        reg_wdata[4]) );
  fdef1a15 \reg_wdata_reg[3]  ( .D(ep0_din[3]), .E(n6), .CLK(n41), .Q(
        reg_wdata[3]) );
  fdef1a15 \reg_wdata_reg[2]  ( .D(ep0_din[2]), .E(n6), .CLK(n41), .Q(
        reg_wdata[2]) );
  fdef1a15 \reg_wdata_reg[1]  ( .D(ep0_din[1]), .E(n6), .CLK(n41), .Q(
        reg_wdata[1]) );
  fdef1a15 \reg_wdata_reg[0]  ( .D(ep0_din[0]), .E(n6), .CLK(n41), .Q(
        reg_wdata[0]) );
  fdf1a6 \rom_adr_reg[3]  ( .D(n450), .CLK(n53), .Q(rom_adr[3]) );
  fdf1a6 \rom_adr_reg[0]  ( .D(n449), .CLK(n53), .Q(rom_adr[0]) );
  fdf1a6 \rom_adr_reg[1]  ( .D(n448), .CLK(n53), .Q(rom_adr[1]) );
  fdf1a6 \rom_adr_reg[4]  ( .D(n446), .CLK(n53), .Q(rom_adr[4]) );
  fdf1a6 \rom_adr_reg[5]  ( .D(n445), .CLK(n53), .Q(rom_adr[5]) );
  usb1_ctrl_DW01_inc_1 add_319_S2 ( .A(rom_adr), .SUM({N174, N173, N172, N171, 
        N170, N169, N168}) );
  ha1a2 \add_428/U1_1_1  ( .A(tx_bcnt[1]), .B(tx_bcnt[0]), .CO(
        \add_428/carry[2] ), .S(N290) );
  ha1a2 \add_428/U1_1_2  ( .A(tx_bcnt[2]), .B(\add_428/carry[2] ), .CO(
        \add_428/carry[3] ), .S(N291) );
  ha1a2 \add_428/U1_1_3  ( .A(tx_bcnt[3]), .B(\add_428/carry[3] ), .CO(N293), 
        .S(N292) );
  fdef1a3 \hdr0_reg[5]  ( .D(ep0_din[5]), .E(le[0]), .CLK(n30), .Q(hdr0[5]) );
  fdef1a3 \reg_rdata_r_reg[0]  ( .D(reg_rdata[0]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[0]) );
  fdef1a3 \reg_rdata_r_reg[1]  ( .D(reg_rdata[1]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[1]) );
  fdef1a3 \reg_rdata_r_reg[2]  ( .D(reg_rdata[2]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[2]) );
  fdef1a3 \reg_rdata_r_reg[3]  ( .D(reg_rdata[3]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[3]) );
  fdef1a3 \reg_rdata_r_reg[4]  ( .D(reg_rdata[4]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[4]) );
  fdef1a3 \reg_rdata_r_reg[5]  ( .D(reg_rdata[5]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[5]) );
  fdef1a3 \reg_rdata_r_reg[6]  ( .D(reg_rdata[6]), .E(n13), .CLK(n37), .Q(
        reg_rdata_r[6]) );
  fdef1a3 \reg_rdata_r_reg[7]  ( .D(reg_rdata[7]), .E(n13), .CLK(n38), .Q(
        reg_rdata_r[7]) );
  fdef1a3 \reg_rdata_r_reg[8]  ( .D(reg_rdata[8]), .E(n13), .CLK(n38), .Q(
        reg_rdata_r[8]) );
  fdef1a3 \reg_rdata_r_reg[9]  ( .D(reg_rdata[9]), .E(n13), .CLK(n38), .Q(
        reg_rdata_r[9]) );
  fdef1a3 \reg_rdata_r_reg[10]  ( .D(reg_rdata[10]), .E(n14), .CLK(n38), .Q(
        reg_rdata_r[10]) );
  fdef1a3 \reg_rdata_r_reg[11]  ( .D(reg_rdata[11]), .E(n14), .CLK(n38), .Q(
        reg_rdata_r[11]) );
  fdef1a3 \reg_rdata_r_reg[12]  ( .D(reg_rdata[12]), .E(n14), .CLK(n38), .Q(
        reg_rdata_r[12]) );
  fdef1a3 \reg_rdata_r_reg[13]  ( .D(reg_rdata[13]), .E(n14), .CLK(n38), .Q(
        reg_rdata_r[13]) );
  fdef1a3 \reg_rdata_r_reg[14]  ( .D(reg_rdata[14]), .E(n14), .CLK(n38), .Q(
        reg_rdata_r[14]) );
  fdef1a3 \reg_rdata_r_reg[15]  ( .D(reg_rdata[15]), .E(n14), .CLK(n38), .Q(
        reg_rdata_r[15]) );
  fdef1a3 \reg_rdata_r_reg[16]  ( .D(reg_rdata[16]), .E(n14), .CLK(n39), .Q(
        reg_rdata_r[16]) );
  fdef1a3 \reg_rdata_r_reg[17]  ( .D(reg_rdata[17]), .E(n14), .CLK(n39), .Q(
        reg_rdata_r[17]) );
  fdef1a3 \reg_rdata_r_reg[18]  ( .D(reg_rdata[18]), .E(n14), .CLK(n39), .Q(
        reg_rdata_r[18]) );
  fdef1a3 \reg_rdata_r_reg[19]  ( .D(reg_rdata[19]), .E(n14), .CLK(n39), .Q(
        reg_rdata_r[19]) );
  fdef1a3 \reg_rdata_r_reg[20]  ( .D(reg_rdata[20]), .E(n15), .CLK(n39), .Q(
        reg_rdata_r[20]) );
  fdef1a3 \reg_rdata_r_reg[21]  ( .D(reg_rdata[21]), .E(n15), .CLK(n39), .Q(
        reg_rdata_r[21]) );
  fdef1a3 \reg_rdata_r_reg[22]  ( .D(reg_rdata[22]), .E(n15), .CLK(n39), .Q(
        reg_rdata_r[22]) );
  fdef1a3 \reg_rdata_r_reg[23]  ( .D(reg_rdata[23]), .E(n15), .CLK(n39), .Q(
        reg_rdata_r[23]) );
  fdef1a3 \reg_rdata_r_reg[24]  ( .D(reg_rdata[24]), .E(n15), .CLK(n39), .Q(
        reg_rdata_r[24]) );
  fdef1a3 \reg_rdata_r_reg[25]  ( .D(reg_rdata[25]), .E(n15), .CLK(n40), .Q(
        reg_rdata_r[25]) );
  fdef1a3 \reg_rdata_r_reg[26]  ( .D(reg_rdata[26]), .E(n15), .CLK(n40), .Q(
        reg_rdata_r[26]) );
  fdef1a3 \reg_rdata_r_reg[27]  ( .D(reg_rdata[27]), .E(n15), .CLK(n40), .Q(
        reg_rdata_r[27]) );
  fdef1a3 \reg_rdata_r_reg[28]  ( .D(reg_rdata[28]), .E(n15), .CLK(n40), .Q(
        reg_rdata_r[28]) );
  fdef1a3 \reg_rdata_r_reg[29]  ( .D(reg_rdata[29]), .E(n15), .CLK(n40), .Q(
        reg_rdata_r[29]) );
  fdef1a3 \reg_rdata_r_reg[30]  ( .D(reg_rdata[30]), .E(n16), .CLK(n40), .Q(
        reg_rdata_r[30]) );
  fdef1a3 \reg_rdata_r_reg[31]  ( .D(reg_rdata[31]), .E(n16), .CLK(n40), .Q(
        reg_rdata_r[31]) );
  fdef1a3 \hdr0_reg[0]  ( .D(ep0_din[0]), .E(le[0]), .CLK(n30), .Q(hdr0[0]) );
  fdef1a3 \hdr0_reg[1]  ( .D(ep0_din[1]), .E(le[0]), .CLK(n30), .Q(hdr0[1]) );
  fdef1a3 \hdr0_reg[2]  ( .D(ep0_din[2]), .E(le[0]), .CLK(n30), .Q(hdr0[2]) );
  fdef1a3 \hdr0_reg[3]  ( .D(ep0_din[3]), .E(le[0]), .CLK(n30), .Q(hdr0[3]) );
  fdef1a3 \hdr0_reg[4]  ( .D(ep0_din[4]), .E(le[0]), .CLK(n30), .Q(hdr0[4]) );
  fdef1a3 \hdr1_reg[5]  ( .D(ep0_din[5]), .E(le[1]), .CLK(n31), .Q(hdr1[5]) );
  fdef1a3 \hdr1_reg[6]  ( .D(ep0_din[6]), .E(le[1]), .CLK(n31), .Q(hdr1[6]) );
  fdef1a3 \hdr1_reg[7]  ( .D(ep0_din[7]), .E(le[1]), .CLK(n31), .Q(hdr1[7]) );
  fdef1a3 \hdr6_reg[0]  ( .D(ep0_din[0]), .E(le[6]), .CLK(n36), .Q(hdr6[0]) );
  fdf1a3 halt_reg ( .D(n481), .CLK(n29), .Q(halt) );
  fdef1a3 \hdr1_reg[4]  ( .D(ep0_din[4]), .E(le[1]), .CLK(n31), .Q(hdr1[4]) );
  fdef1a3 \hdr6_reg[2]  ( .D(ep0_din[2]), .E(le[6]), .CLK(n36), .Q(hdr6[2]) );
  fdef1a3 \hdr6_reg[1]  ( .D(ep0_din[1]), .E(le[6]), .CLK(n36), .Q(hdr6[1]) );
  fdef1a3 \hdr6_reg[4]  ( .D(ep0_din[4]), .E(le[6]), .CLK(n36), .Q(hdr6[4]) );
  fdef1a3 \hdr6_reg[5]  ( .D(ep0_din[5]), .E(le[6]), .CLK(n36), .Q(hdr6[5]) );
  fdef1a3 \hdr3_reg[4]  ( .D(ep0_din[4]), .E(le[3]), .CLK(n33), .Q(wValue[12])
         );
  fdef1a3 \hdr3_reg[5]  ( .D(ep0_din[5]), .E(le[3]), .CLK(n33), .Q(wValue[13])
         );
  fdef1a3 \hdr3_reg[6]  ( .D(ep0_din[6]), .E(le[3]), .CLK(n33), .Q(wValue[14])
         );
  fdef1a3 \hdr3_reg[7]  ( .D(ep0_din[7]), .E(le[3]), .CLK(n33), .Q(wValue[15])
         );
  fdef1a3 \hdr6_reg[3]  ( .D(ep0_din[3]), .E(le[6]), .CLK(n36), .Q(hdr6[3]) );
  fdf1a3 \funct_adr_tmp_reg[6]  ( .D(n433), .CLK(n49), .Q(funct_adr_tmp[6]) );
  fdf1a3 \funct_adr_tmp_reg[5]  ( .D(n434), .CLK(n49), .Q(funct_adr_tmp[5]) );
  fdf1a3 \funct_adr_tmp_reg[4]  ( .D(n435), .CLK(n49), .Q(funct_adr_tmp[4]) );
  fdf1a3 \funct_adr_tmp_reg[3]  ( .D(n436), .CLK(n49), .Q(funct_adr_tmp[3]) );
  fdf1a3 \funct_adr_tmp_reg[2]  ( .D(n437), .CLK(n49), .Q(funct_adr_tmp[2]) );
  fdf1a3 \funct_adr_tmp_reg[1]  ( .D(n438), .CLK(n50), .Q(funct_adr_tmp[1]) );
  fdf1a3 \funct_adr_tmp_reg[0]  ( .D(n439), .CLK(n50), .Q(funct_adr_tmp[0]) );
  fdf1a3 fifo_we_rom_r2_reg ( .D(fifo_we_rom_r), .CLK(n53), .Q(fifo_we_rom_r2)
         );
  fdf1a3 send_stall_reg ( .D(config_err), .CLK(n51), .Q(send_stall) );
  fdef1a3 \hdr2_reg[4]  ( .D(ep0_din[4]), .E(le[2]), .CLK(n32), .Q(wValue[4])
         );
  fdef1a3 \hdr2_reg[5]  ( .D(ep0_din[5]), .E(le[2]), .CLK(n32), .Q(wValue[5])
         );
  fdef1a3 \hdr2_reg[6]  ( .D(ep0_din[6]), .E(le[2]), .CLK(n32), .Q(wValue[6])
         );
  fdef1a3 \hdr3_reg[2]  ( .D(ep0_din[2]), .E(le[3]), .CLK(n33), .Q(wValue[10])
         );
  fdef1a3 \hdr3_reg[3]  ( .D(ep0_din[3]), .E(le[3]), .CLK(n33), .Q(wValue[11])
         );
  fdef1a3 \hdr1_reg[2]  ( .D(ep0_din[2]), .E(le[1]), .CLK(n31), .Q(hdr1[2]) );
  fdef1a3 \hdr1_reg[1]  ( .D(ep0_din[1]), .E(le[1]), .CLK(n31), .Q(hdr1[1]) );
  fdef1a3 \reg_addr_reg[2]  ( .D(wIndex[10]), .E(n10), .CLK(n48), .Q(
        reg_addr[2]) );
  fdef1a3 \hdr1_reg[3]  ( .D(ep0_din[3]), .E(le[1]), .CLK(n31), .Q(hdr1[3]) );
  fdf1a3 configured_reg ( .D(n424), .CLK(n50), .Q(configured) );
  fdef1a3 \reg_addr_reg[5]  ( .D(wIndex[13]), .E(n10), .CLK(n47), .Q(
        reg_addr[5]) );
  fdef1a3 \hdr6_reg[6]  ( .D(ep0_din[6]), .E(le[6]), .CLK(n36), .Q(hdr6[6]) );
  fdf1a3 \state_reg[7]  ( .D(n466), .CLK(n54), .Q(state[7]) );
  fdef1a3 \hdr3_reg[1]  ( .D(ep0_din[1]), .E(le[3]), .CLK(n33), .Q(wValue[9])
         );
  fdef1a3 \hdr2_reg[0]  ( .D(ep0_din[0]), .E(le[2]), .CLK(n32), .Q(wValue[0])
         );
  fdef1a3 \hdr2_reg[1]  ( .D(ep0_din[1]), .E(le[2]), .CLK(n32), .Q(wValue[1])
         );
  fdf1c3 hdr_done_r_reg ( .D(n324), .CLK(n36), .QN(hdr_done_r) );
  fdef1a3 \reg_addr_reg[3]  ( .D(wIndex[11]), .E(n10), .CLK(n47), .Q(
        reg_addr[3]) );
  fdf1a3 \state_reg[13]  ( .D(n472), .CLK(n55), .Q(state[13]) );
  fdef1a3 \hdr0_reg[6]  ( .D(ep0_din[6]), .E(le[0]), .CLK(n30), .Q(hdr0[6]) );
  fdf1a3 \reg_byte_cnt_reg[1]  ( .D(n455), .CLK(n40), .Q(reg_byte_cnt[1]) );
  fdef1a3 \hdr2_reg[2]  ( .D(ep0_din[2]), .E(le[2]), .CLK(n32), .Q(wValue[2])
         );
  fdef1a3 \hdr2_reg[3]  ( .D(ep0_din[3]), .E(le[2]), .CLK(n32), .Q(wValue[3])
         );
  fdef1a3 \reg_addr_reg[4]  ( .D(wIndex[12]), .E(n10), .CLK(n47), .Q(
        reg_addr[4]) );
  fdf1a3 \funct_adr_reg[6]  ( .D(n425), .CLK(n49), .Q(funct_adr[6]) );
  fdf1a3 \funct_adr_reg[5]  ( .D(n426), .CLK(n49), .Q(funct_adr[5]) );
  fdf1a3 \funct_adr_reg[4]  ( .D(n427), .CLK(n49), .Q(funct_adr[4]) );
  fdf1a3 \funct_adr_reg[3]  ( .D(n428), .CLK(n49), .Q(funct_adr[3]) );
  fdf1a3 \funct_adr_reg[2]  ( .D(n429), .CLK(n50), .Q(funct_adr[2]) );
  fdf1a3 \funct_adr_reg[1]  ( .D(n430), .CLK(n50), .Q(funct_adr[1]) );
  fdf1a3 \funct_adr_reg[0]  ( .D(n431), .CLK(n50), .Q(funct_adr[0]) );
  fdf1a3 \rom_size_reg[1]  ( .D(n415), .CLK(n54), .Q(rom_size[1]) );
  fdf1a3 \rom_size_reg[2]  ( .D(n414), .CLK(n54), .Q(rom_size[2]) );
  fdf1c3 rom_sel_r_reg ( .D(n191), .CLK(n53), .QN(rom_sel_r) );
  fdf1a3 \state_reg[11]  ( .D(n470), .CLK(n29), .Q(state[11]) );
  fdf1a3 get_descriptor_reg ( .D(N321), .CLK(n48), .Q(get_descriptor) );
  fdf1a3 set_adr_pending_reg ( .D(n432), .CLK(n48), .Q(set_adr_pending) );
  fdf1a3 set_interface_reg ( .D(N326), .CLK(n50), .Q(set_interface) );
  fdf1a3 get_interface_reg ( .D(N325), .CLK(n50), .Q(get_interface) );
  fdf1a3 get_config_reg ( .D(N323), .CLK(n51), .Q(get_config) );
  fdf1a3 get_status_reg ( .D(N317), .CLK(n51), .Q(get_status) );
  fdf1a3 \state_reg[9]  ( .D(n468), .CLK(n52), .Q(state[9]) );
  fdf1a3 \state_reg[4]  ( .D(n463), .CLK(n52), .Q(state[4]) );
  fdf1a3 \state_reg[5]  ( .D(n464), .CLK(n52), .Q(state[5]) );
  fdf1a3 reg_rdwrn_reg ( .D(n408), .CLK(n37), .Q(reg_rdwrn) );
  fdf1a3 reg_req_reg ( .D(N353), .CLK(n44), .Q(reg_req) );
  fdf1a3 \ep0_dout_reg[7]  ( .D(N267), .CLK(n56), .Q(ep0_dout[7]) );
  fdf1a3 \ep0_dout_reg[6]  ( .D(N266), .CLK(n56), .Q(ep0_dout[6]) );
  fdf1a3 \ep0_dout_reg[5]  ( .D(N265), .CLK(n56), .Q(ep0_dout[5]) );
  fdf1a3 \ep0_dout_reg[4]  ( .D(N264), .CLK(n57), .Q(ep0_dout[4]) );
  fdf1a3 \ep0_dout_reg[3]  ( .D(N263), .CLK(n57), .Q(ep0_dout[3]) );
  fdf1a3 \ep0_dout_reg[2]  ( .D(N262), .CLK(n57), .Q(ep0_dout[2]) );
  fdf1a3 \ep0_dout_reg[1]  ( .D(N261), .CLK(n57), .Q(ep0_dout[1]) );
  fdf1a3 \ep0_dout_reg[0]  ( .D(N260), .CLK(n57), .Q(ep0_dout[0]) );
  fdf1a3 \state_reg[15]  ( .D(n474), .CLK(n55), .Q(state[15]) );
  fdf1a3 \reg_byte_cnt_reg[0]  ( .D(n409), .CLK(n44), .Q(reg_byte_cnt[0]) );
  fdf1a3 \rom_size_reg[3]  ( .D(n413), .CLK(n54), .Q(rom_size[3]) );
  fdf1a3 \rom_size_reg[6]  ( .D(n410), .CLK(n54), .Q(rom_size[6]) );
  fdf1a3 \rom_adr_reg[2]  ( .D(n447), .CLK(n53), .Q(rom_adr[2]) );
  fdf1a3 \tx_bcnt_reg[3]  ( .D(n480), .CLK(n29), .Q(tx_bcnt[3]) );
  fdf1a3 set_config_reg ( .D(N324), .CLK(n50), .Q(set_config) );
  fdf1a3 \state_reg[8]  ( .D(n467), .CLK(n51), .Q(state[8]) );
  fdf1a3 \rom_size_reg[4]  ( .D(n412), .CLK(n54), .Q(rom_size[4]) );
  fdf1a3 \state_reg[2]  ( .D(n461), .CLK(n54), .Q(state[2]) );
  fdf1a9 \le_reg[3]  ( .D(n451), .CLK(n32), .Q(le[3]) );
  fdf1a9 \le_reg[4]  ( .D(n443), .CLK(n33), .Q(le[4]) );
  fdf1a3 \ep0_size_reg[6]  ( .D(n417), .CLK(n55), .Q(ep0_size[6]) );
  fdf1a3 \ep0_size_reg[5]  ( .D(n418), .CLK(n55), .Q(ep0_size[5]) );
  fdf1a3 \ep0_size_reg[4]  ( .D(n419), .CLK(n55), .Q(ep0_size[4]) );
  fdf1a3 \ep0_size_reg[3]  ( .D(n420), .CLK(n55), .Q(ep0_size[3]) );
  fdf1a3 \ep0_size_reg[0]  ( .D(n423), .CLK(n56), .Q(ep0_size[0]) );
  fdf1a3 ep0_we_reg ( .D(N268), .CLK(n56), .Q(ep0_we) );
  fdf1a3 \le_reg[7]  ( .D(n456), .CLK(n29), .Q(le[7]) );
  fdf1a3 v_get_status_reg ( .D(N330), .CLK(n48), .Q(v_get_status) );
  fdf1a3 \state_reg[10]  ( .D(n469), .CLK(n52), .Q(state[10]) );
  fdf1a3 \state_reg[3]  ( .D(n462), .CLK(n52), .Q(state[3]) );
  fdf1a9 \le_reg[0]  ( .D(n440), .CLK(n30), .Q(le[0]) );
  fdf1a9 \le_reg[6]  ( .D(n441), .CLK(n35), .Q(le[6]) );
  fdf1a3 \ep0_size_reg[2]  ( .D(n421), .CLK(n56), .Q(ep0_size[2]) );
  fdf1a3 \ep0_size_reg[1]  ( .D(n422), .CLK(n56), .Q(ep0_size[1]) );
  fdf1a3 \rom_size_reg[5]  ( .D(n411), .CLK(n54), .Q(rom_size[5]) );
  fdf1a3 set_descriptor_reg ( .D(N322), .CLK(n48), .Q(set_descriptor) );
  fdf1a3 set_address_reg ( .D(N320), .CLK(n48), .Q(set_address) );
  fdf1a3 synch_frame_reg ( .D(N327), .CLK(n51), .Q(synch_frame) );
  fdf1a3 \state_reg[16]  ( .D(n475), .CLK(n52), .Q(state[16]) );
  fdf1a9 \le_reg[1]  ( .D(n453), .CLK(n30), .Q(le[1]) );
  fdf1a9 \le_reg[2]  ( .D(n452), .CLK(n31), .Q(le[2]) );
  fdf1a9 \le_reg[5]  ( .D(n442), .CLK(n34), .Q(le[5]) );
  fdf1a3 \rom_size_reg[0]  ( .D(n416), .CLK(n54), .Q(rom_size[0]) );
  fdf1a3 \state_reg[14]  ( .D(n473), .CLK(n29), .Q(state[14]) );
  fdf1a3 \state_reg[19]  ( .D(n478), .CLK(n52), .Q(state[19]) );
  fdf1a3 \state_reg[18]  ( .D(n477), .CLK(n55), .Q(state[18]) );
  fdf1a3 v_set_feature_reg ( .D(N329), .CLK(n48), .Q(v_set_feature) );
  fdf1a3 v_set_int_reg ( .D(N328), .CLK(n51), .Q(v_set_int) );
  fdf1a3 reg_wphase_reg ( .D(n454), .CLK(n40), .Q(reg_wphase) );
  fdf1a3 \state_reg[6]  ( .D(n465), .CLK(n52), .Q(state[6]) );
  fdf1a3 clear_feature_reg ( .D(N318), .CLK(n51), .Q(clear_feature) );
  fdf1a3 \tx_bcnt_reg[2]  ( .D(n457), .CLK(n56), .Q(tx_bcnt[2]) );
  fdf1a3 v_set_reg_raddr_reg ( .D(N332), .CLK(n36), .Q(v_set_reg_raddr) );
  fdf1a3 set_feature_reg ( .D(N319), .CLK(n51), .Q(set_feature) );
  fdf1a3 \state_reg[17]  ( .D(n476), .CLK(n55), .Q(state[17]) );
  fdf1a3 config_err_reg ( .D(N361), .CLK(n51), .Q(config_err) );
  fdef1a3 \hdr2_reg[7]  ( .D(ep0_din[7]), .E(le[2]), .CLK(n32), .Q(wValue[7])
         );
  fdef1a3 \hdr4_reg[0]  ( .D(ep0_din[0]), .E(le[4]), .CLK(n34), .Q(wIndex[0])
         );
  fdef1a3 \hdr4_reg[1]  ( .D(ep0_din[1]), .E(le[4]), .CLK(n34), .Q(wIndex[1])
         );
  fdef1a3 \hdr4_reg[2]  ( .D(ep0_din[2]), .E(le[4]), .CLK(n34), .Q(wIndex[2])
         );
  fdef1a3 \hdr4_reg[3]  ( .D(ep0_din[3]), .E(le[4]), .CLK(n34), .Q(wIndex[3])
         );
  fdef1a3 \hdr4_reg[4]  ( .D(ep0_din[4]), .E(le[4]), .CLK(n34), .Q(wIndex[4])
         );
  fdef1a3 \hdr4_reg[5]  ( .D(ep0_din[5]), .E(le[4]), .CLK(n34), .Q(wIndex[5])
         );
  fdef1a3 \hdr4_reg[6]  ( .D(ep0_din[6]), .E(le[4]), .CLK(n34), .Q(wIndex[6])
         );
  fdef1a3 \hdr4_reg[7]  ( .D(ep0_din[7]), .E(le[4]), .CLK(n34), .Q(wIndex[7])
         );
  fdef1a3 \hdr5_reg[0]  ( .D(ep0_din[0]), .E(le[5]), .CLK(n35), .Q(wIndex[8])
         );
  fdef1a3 \hdr5_reg[1]  ( .D(ep0_din[1]), .E(le[5]), .CLK(n35), .Q(wIndex[9])
         );
  fdef1a3 \hdr5_reg[2]  ( .D(ep0_din[2]), .E(le[5]), .CLK(n35), .Q(wIndex[10])
         );
  fdef1a3 \hdr5_reg[3]  ( .D(ep0_din[3]), .E(le[5]), .CLK(n35), .Q(wIndex[11])
         );
  fdef1a3 \hdr5_reg[4]  ( .D(ep0_din[4]), .E(le[5]), .CLK(n35), .Q(wIndex[12])
         );
  fdef1a3 \hdr5_reg[5]  ( .D(ep0_din[5]), .E(le[5]), .CLK(n35), .Q(wIndex[13])
         );
  fdef1a3 \hdr5_reg[6]  ( .D(ep0_din[6]), .E(le[5]), .CLK(n35), .Q(wIndex[14])
         );
  fdef1a3 \hdr5_reg[7]  ( .D(ep0_din[7]), .E(le[5]), .CLK(n35), .Q(wIndex[15])
         );
  fdf1c3 fifo_we_rom_r_reg ( .D(n191), .CLK(n52), .QN(fifo_we_rom_r) );
  fdef1a3 \state_reg[0]  ( .D(n497), .E(n212), .CLK(n29), .Q(state[0]) );
  fdef1a3 \reg_wdata_reg[31]  ( .D(reg_wdata[23]), .E(n7), .CLK(n42), .Q(
        reg_wdata[31]) );
  fdef1a3 \reg_wdata_reg[30]  ( .D(reg_wdata[22]), .E(n7), .CLK(n42), .Q(
        reg_wdata[30]) );
  fdef1a3 \reg_wdata_reg[29]  ( .D(reg_wdata[21]), .E(n7), .CLK(n42), .Q(
        reg_wdata[29]) );
  fdef1a3 \reg_wdata_reg[28]  ( .D(reg_wdata[20]), .E(n7), .CLK(n43), .Q(
        reg_wdata[28]) );
  fdef1a3 \reg_wdata_reg[27]  ( .D(reg_wdata[19]), .E(n8), .CLK(n43), .Q(
        reg_wdata[27]) );
  fdef1a3 \reg_wdata_reg[26]  ( .D(reg_wdata[18]), .E(n8), .CLK(n43), .Q(
        reg_wdata[26]) );
  fdef1a3 \reg_wdata_reg[25]  ( .D(reg_wdata[17]), .E(n8), .CLK(n44), .Q(
        reg_wdata[25]) );
  fdef1a3 \reg_wdata_reg[24]  ( .D(reg_wdata[16]), .E(n9), .CLK(n44), .Q(
        reg_wdata[24]) );
  fdef1a3 \reg_addr_reg[31]  ( .D(wValue[7]), .E(n10), .CLK(n44), .Q(
        reg_addr[31]) );
  fdef1a3 \reg_addr_reg[30]  ( .D(wValue[6]), .E(n12), .CLK(n44), .Q(
        reg_addr[30]) );
  fdef1a3 \reg_addr_reg[29]  ( .D(wValue[5]), .E(n12), .CLK(n45), .Q(
        reg_addr[29]) );
  fdef1a3 \reg_addr_reg[28]  ( .D(wValue[4]), .E(n11), .CLK(n45), .Q(
        reg_addr[28]) );
  fdef1a3 \reg_addr_reg[27]  ( .D(wValue[3]), .E(n11), .CLK(n45), .Q(
        reg_addr[27]) );
  fdef1a3 \reg_addr_reg[26]  ( .D(wValue[2]), .E(n11), .CLK(n45), .Q(
        reg_addr[26]) );
  fdef1a3 \reg_addr_reg[25]  ( .D(wValue[1]), .E(n11), .CLK(n45), .Q(
        reg_addr[25]) );
  fdef1a3 \reg_addr_reg[24]  ( .D(wValue[0]), .E(n11), .CLK(n45), .Q(
        reg_addr[24]) );
  fdef1a3 \reg_addr_reg[23]  ( .D(wValue[15]), .E(n11), .CLK(n45), .Q(
        reg_addr[23]) );
  fdef1a3 \reg_addr_reg[22]  ( .D(wValue[14]), .E(n11), .CLK(n45), .Q(
        reg_addr[22]) );
  fdef1a3 \reg_addr_reg[21]  ( .D(wValue[13]), .E(n11), .CLK(n45), .Q(
        reg_addr[21]) );
  fdef1a3 \reg_addr_reg[20]  ( .D(wValue[12]), .E(n11), .CLK(n46), .Q(
        reg_addr[20]) );
  fdef1a3 \reg_addr_reg[19]  ( .D(wValue[11]), .E(n11), .CLK(n46), .Q(
        reg_addr[19]) );
  fdef1a3 \reg_addr_reg[18]  ( .D(wValue[10]), .E(n11), .CLK(n46), .Q(
        reg_addr[18]) );
  fdef1a3 \reg_addr_reg[17]  ( .D(wValue[9]), .E(n11), .CLK(n46), .Q(
        reg_addr[17]) );
  fdef1a3 \reg_addr_reg[16]  ( .D(wValue[8]), .E(n11), .CLK(n46), .Q(
        reg_addr[16]) );
  fdef1a3 \reg_addr_reg[15]  ( .D(wIndex[7]), .E(n11), .CLK(n46), .Q(
        reg_addr[15]) );
  fdef1a3 \reg_addr_reg[14]  ( .D(wIndex[6]), .E(n11), .CLK(n46), .Q(
        reg_addr[14]) );
  fdef1a3 \reg_addr_reg[13]  ( .D(wIndex[5]), .E(n11), .CLK(n46), .Q(
        reg_addr[13]) );
  fdef1a3 \reg_addr_reg[12]  ( .D(wIndex[4]), .E(n11), .CLK(n46), .Q(
        reg_addr[12]) );
  fdef1a3 \reg_addr_reg[11]  ( .D(wIndex[3]), .E(n10), .CLK(n47), .Q(
        reg_addr[11]) );
  fdef1a3 \reg_addr_reg[10]  ( .D(wIndex[2]), .E(n10), .CLK(n47), .Q(
        reg_addr[10]) );
  fdef1a3 \reg_addr_reg[9]  ( .D(wIndex[1]), .E(n10), .CLK(n47), .Q(
        reg_addr[9]) );
  fdef1a3 \reg_addr_reg[8]  ( .D(wIndex[0]), .E(n10), .CLK(n47), .Q(
        reg_addr[8]) );
  fdef1a3 \reg_addr_reg[7]  ( .D(wIndex[15]), .E(n10), .CLK(n47), .Q(
        reg_addr[7]) );
  fdef1a3 \reg_addr_reg[6]  ( .D(wIndex[14]), .E(n10), .CLK(n47), .Q(
        reg_addr[6]) );
  fdef1a3 \reg_addr_reg[1]  ( .D(wIndex[9]), .E(n10), .CLK(n48), .Q(
        reg_addr[1]) );
  fdef1a3 \reg_addr_reg[0]  ( .D(wIndex[8]), .E(n10), .CLK(n48), .Q(
        reg_addr[0]) );
  fdef1a3 \reg_wdata_reg[15]  ( .D(reg_wdata[7]), .E(n6), .CLK(n41), .Q(
        reg_wdata[15]) );
  fdef1a3 \reg_wdata_reg[23]  ( .D(reg_wdata[15]), .E(n6), .CLK(n42), .Q(
        reg_wdata[23]) );
  fdef1a3 \reg_wdata_reg[14]  ( .D(reg_wdata[6]), .E(n7), .CLK(n42), .Q(
        reg_wdata[14]) );
  fdef1a3 \reg_wdata_reg[22]  ( .D(reg_wdata[14]), .E(n7), .CLK(n42), .Q(
        reg_wdata[22]) );
  fdef1a3 \reg_wdata_reg[13]  ( .D(reg_wdata[5]), .E(n7), .CLK(n42), .Q(
        reg_wdata[13]) );
  fdef1a3 \reg_wdata_reg[21]  ( .D(reg_wdata[13]), .E(n7), .CLK(n42), .Q(
        reg_wdata[21]) );
  fdef1a3 \reg_wdata_reg[12]  ( .D(reg_wdata[4]), .E(n7), .CLK(n42), .Q(
        reg_wdata[12]) );
  fdef1a3 \reg_wdata_reg[20]  ( .D(reg_wdata[12]), .E(n7), .CLK(n43), .Q(
        reg_wdata[20]) );
  fdef1a3 \reg_wdata_reg[19]  ( .D(reg_wdata[11]), .E(n8), .CLK(n43), .Q(
        reg_wdata[19]) );
  fdef1a3 \reg_wdata_reg[18]  ( .D(reg_wdata[10]), .E(n8), .CLK(n43), .Q(
        reg_wdata[18]) );
  fdef1a3 \reg_wdata_reg[17]  ( .D(reg_wdata[9]), .E(n8), .CLK(n44), .Q(
        reg_wdata[17]) );
  fdef1a3 \reg_wdata_reg[16]  ( .D(reg_wdata[8]), .E(n9), .CLK(n44), .Q(
        reg_wdata[16]) );
  fdef1a3 \reg_wdata_reg[11]  ( .D(reg_wdata[3]), .E(n8), .CLK(n43), .Q(
        reg_wdata[11]) );
  fdef1a3 \reg_wdata_reg[10]  ( .D(reg_wdata[2]), .E(n8), .CLK(n43), .Q(
        reg_wdata[10]) );
  fdef1a3 \reg_wdata_reg[9]  ( .D(reg_wdata[1]), .E(n8), .CLK(n43), .Q(
        reg_wdata[9]) );
  fdef1a3 \reg_wdata_reg[8]  ( .D(reg_wdata[0]), .E(n8), .CLK(n44), .Q(
        reg_wdata[8]) );
  fdef1a3 \hdr3_reg[0]  ( .D(ep0_din[0]), .E(le[3]), .CLK(n33), .Q(wValue[8])
         );
  fdf1a3 \tx_bcnt_reg[0]  ( .D(n459), .CLK(n29), .Q(tx_bcnt[0]) );
  fdf1a3 write_done_reg ( .D(n479), .CLK(n29), .Q(high_sel) );
  fdef1a3 \hdr1_reg[0]  ( .D(ep0_din[0]), .E(le[1]), .CLK(n31), .Q(hdr1[0]) );
  fdf1a3 v_set_reg_waddr_reg ( .D(N331), .CLK(n37), .Q(v_set_reg_waddr) );
  fdf1a3 \rom_adr_reg[6]  ( .D(n444), .CLK(n53), .Q(rom_adr[6]) );
  fdf1a3 \state_reg[12]  ( .D(n471), .CLK(n55), .Q(state[12]) );
  fdf1a3 \tx_bcnt_reg[1]  ( .D(n458), .CLK(n56), .Q(tx_bcnt[1]) );
  and3d2 U4 ( .A(v_set_feature), .B(v_set_int), .C(v_get_status), .Y(n261) );
  inv1a3 U5 ( .A(state[14]), .Y(n509) );
  inv1a1 U7 ( .A(rom_size[4]), .Y(n90) );
  or2c3 U8 ( .A(hdr1[1]), .B(hdr1[0]), .Y(n333) );
  or2c3 U9 ( .A(set_address), .B(n19), .Y(n159) );
  inv1a3 U10 ( .A(ctrl_setup), .Y(n569) );
  ao1f9 U11 ( .A(hdr6[6]), .B(n103), .C(n102), .Y(n1) );
  ao1f2 U12 ( .A(n1), .B(n106), .C(n143), .Y(n122) );
  ao1f2 U13 ( .A(n1), .B(n520), .C(n138), .Y(n120) );
  and2c1 U15 ( .A(n85), .B(rom_size[2]), .Y(n2) );
  inv1a2 U17 ( .A(n2), .Y(n3) );
  and2c3 U19 ( .A(rom_size[5]), .B(n88), .Y(n89) );
  ao1f2 U21 ( .A(n1), .B(n524), .C(n145), .Y(n124) );
  oa4f2 U23 ( .A(reg_rdata_r[23]), .B(n353), .C(reg_rdata_r[31]), .D(n354), 
        .Y(n349) );
  or2c3 U25 ( .A(n87), .B(n90), .Y(n88) );
  and2c2 U26 ( .A(n3), .B(rom_size[3]), .Y(n87) );
  oa1d6 U27 ( .A(reg_wphase), .B(state[1]), .C(ep0_stat[1]), .Y(ep0_re) );
  ao1f2 U28 ( .A(n1), .B(n528), .C(n126), .Y(n114) );
  ao1f2 U29 ( .A(n1), .B(n104), .C(n127), .Y(n116) );
  ao1f2 U30 ( .A(n1), .B(n105), .C(n130), .Y(n118) );
  ao1d1 U31 ( .A(n4), .B(ep0_size[0]), .C(n144), .Y(n423) );
  oa4f2 U32 ( .A(reg_rdata_r[6]), .B(n351), .C(reg_rdata_r[14]), .D(n352), .Y(
        n362) );
  oa4f1 U33 ( .A(reg_rdata_r[7]), .B(n351), .C(reg_rdata_r[15]), .D(n352), .Y(
        n350) );
  oa4f1 U35 ( .A(reg_rdata_r[0]), .B(n351), .C(reg_rdata_r[8]), .D(n352), .Y(
        n401) );
  oa4f1 U36 ( .A(reg_rdata_r[17]), .B(n353), .C(reg_rdata_r[25]), .D(n354), 
        .Y(n393) );
  oa4f1 U37 ( .A(reg_rdata_r[18]), .B(n353), .C(reg_rdata_r[26]), .D(n354), 
        .Y(n386) );
  ao1d1 U38 ( .A(n4), .B(ep0_size[6]), .C(n125), .Y(n417) );
  ao2h1 U39 ( .B(rom_size[6]), .A(n110), .C(n111), .D(n112), .Y(n410) );
  ao4a1 U40 ( .A(n4), .B(ep0_size[3]), .C(n118), .D(n508), .Y(n420) );
  ao4a1 U41 ( .A(n4), .B(ep0_size[4]), .C(n116), .D(n508), .Y(n419) );
  ao4a1 U42 ( .A(n4), .B(ep0_size[5]), .C(n114), .D(n508), .Y(n418) );
  inv1a1 U43 ( .A(n271), .Y(n499) );
  or3d1 U44 ( .A(n20), .B(n224), .C(n226), .Y(n231) );
  or3d1 U45 ( .A(n131), .B(n128), .C(n132), .Y(n105) );
  or3d1 U46 ( .A(n261), .B(n552), .C(n240), .Y(n314) );
  or3d1 U47 ( .A(n219), .B(n540), .C(n501), .Y(n216) );
  or2c1 U48 ( .A(n260), .B(n261), .Y(n257) );
  and3d2 U49 ( .A(hdr0[6]), .B(hdr1[2]), .C(n493), .Y(n338) );
  and3d2 U50 ( .A(get_status), .B(set_feature), .C(clear_feature), .Y(n238) );
  and3d2 U51 ( .A(state[17]), .B(state[2]), .C(state[12]), .Y(n136) );
  or3d1 U52 ( .A(n572), .B(n302), .C(n573), .Y(n290) );
  and2c1 U54 ( .A(n303), .B(n304), .Y(n573) );
  or3d1 U55 ( .A(hdr1[2]), .B(n335), .C(hdr1[3]), .Y(n334) );
  or3d1 U56 ( .A(n317), .B(n318), .C(n319), .Y(n289) );
  and2c1 U57 ( .A(rom_size[4]), .B(rom_size[3]), .Y(n317) );
  and2c1 U58 ( .A(rom_size[6]), .B(rom_size[5]), .Y(n318) );
  or3d1 U59 ( .A(n298), .B(n507), .C(n299), .Y(n268) );
  and2c1 U60 ( .A(state[3]), .B(state[16]), .Y(n298) );
  inv1a1 U61 ( .A(n294), .Y(n491) );
  inv1a1 U62 ( .A(reg_ack), .Y(n487) );
  inv1a1 U63 ( .A(v_set_reg_raddr), .Y(n533) );
  inv1a1 U64 ( .A(hdr1[2]), .Y(n516) );
  inv1a1 U65 ( .A(get_config), .Y(n552) );
  inv1a1 U66 ( .A(hdr0[6]), .Y(n512) );
  inv1a1 U67 ( .A(state[2]), .Y(n563) );
  inv1a1 U68 ( .A(reg_byte_cnt[0]), .Y(n537) );
  inv1a1 U69 ( .A(reg_rdwrn), .Y(n536) );
  inv1a1 U70 ( .A(v_set_reg_waddr), .Y(n535) );
  inv1a1 U71 ( .A(state[9]), .Y(n558) );
  inv1a1 U72 ( .A(state[11]), .Y(n507) );
  inv1a1 U73 ( .A(rst), .Y(n18) );
  and2c1 U74 ( .A(state[6]), .B(state[19]), .Y(n301) );
  inv1a1 U75 ( .A(funct_adr_tmp[0]), .Y(n548) );
  inv1a1 U76 ( .A(funct_adr_tmp[1]), .Y(n547) );
  inv1a1 U77 ( .A(funct_adr_tmp[2]), .Y(n546) );
  inv1a1 U78 ( .A(funct_adr_tmp[3]), .Y(n545) );
  inv1a1 U79 ( .A(funct_adr_tmp[4]), .Y(n544) );
  inv1a1 U80 ( .A(funct_adr_tmp[5]), .Y(n543) );
  inv1a1 U81 ( .A(funct_adr_tmp[6]), .Y(n542) );
  inv1a1 U82 ( .A(tx_bcnt[2]), .Y(n568) );
  inv1a1 U83 ( .A(rom_size[2]), .Y(n562) );
  inv1a1 U88 ( .A(rom_size[1]), .Y(n561) );
  and2c1 U90 ( .A(n308), .B(n309), .Y(n307) );
  inv1a1 U91 ( .A(get_interface), .Y(n550) );
  inv1a1 U92 ( .A(set_interface), .Y(n549) );
  inv1a1 U93 ( .A(hdr1[0]), .Y(n514) );
  or2c1 U97 ( .A(n128), .B(n129), .Y(n104) );
  inv1a1 U98 ( .A(set_descriptor), .Y(n538) );
  oa2i2 U99 ( .A(n139), .B(rom_size_dd[0]), .C(wValue[12]), .D(n407), .Y(n316)
         );
  inv1a1 U100 ( .A(n273), .Y(n498) );
  clk1a3 U101 ( .A(n59), .Y(n55) );
  clk1a3 U102 ( .A(n59), .Y(n54) );
  clk1a3 U103 ( .A(n60), .Y(n53) );
  clk1a3 U104 ( .A(n60), .Y(n52) );
  clk1a3 U106 ( .A(n61), .Y(n51) );
  clk1a3 U107 ( .A(n61), .Y(n50) );
  clk1a3 U108 ( .A(n62), .Y(n49) );
  clk1a3 U109 ( .A(n62), .Y(n48) );
  clk1a3 U110 ( .A(n63), .Y(n47) );
  clk1a3 U111 ( .A(n63), .Y(n46) );
  clk1a3 U113 ( .A(n64), .Y(n45) );
  clk1a3 U114 ( .A(n64), .Y(n44) );
  clk1a3 U115 ( .A(n65), .Y(n43) );
  clk1a3 U116 ( .A(n65), .Y(n42) );
  clk1a3 U117 ( .A(n66), .Y(n41) );
  clk1a3 U118 ( .A(n66), .Y(n40) );
  clk1a3 U119 ( .A(n67), .Y(n39) );
  clk1a3 U120 ( .A(n67), .Y(n38) );
  clk1a3 U122 ( .A(n68), .Y(n37) );
  clk1a3 U124 ( .A(n68), .Y(n36) );
  clk1a3 U125 ( .A(n69), .Y(n35) );
  clk1a3 U126 ( .A(n69), .Y(n34) );
  clk1a3 U131 ( .A(n70), .Y(n33) );
  clk1a3 U132 ( .A(n70), .Y(n32) );
  clk1a3 U133 ( .A(n71), .Y(n31) );
  clk1a3 U134 ( .A(n71), .Y(n30) );
  and2c3 U135 ( .A(n499), .B(n10), .Y(n273) );
  inv1a3 U136 ( .A(n202), .Y(n485) );
  inv1a3 U137 ( .A(n276), .Y(n484) );
  clk1b6 U138 ( .A(n23), .Y(n19) );
  clk1b6 U139 ( .A(n23), .Y(n20) );
  clk1a3 U143 ( .A(n72), .Y(n29) );
  clk1a3 U144 ( .A(n73), .Y(n72) );
  clk1a3 U147 ( .A(n58), .Y(n56) );
  clk1a3 U148 ( .A(n58), .Y(n57) );
  clk1a3 U149 ( .A(n79), .Y(n59) );
  clk1a3 U150 ( .A(n79), .Y(n60) );
  clk1a3 U151 ( .A(n78), .Y(n61) );
  clk1a3 U152 ( .A(n78), .Y(n62) );
  clk1a3 U154 ( .A(n77), .Y(n63) );
  clk1a3 U155 ( .A(n77), .Y(n64) );
  clk1a3 U156 ( .A(n76), .Y(n65) );
  clk1a3 U157 ( .A(n76), .Y(n66) );
  clk1a3 U158 ( .A(n75), .Y(n67) );
  clk1a3 U159 ( .A(n75), .Y(n68) );
  clk1a3 U160 ( .A(n74), .Y(n69) );
  clk1a3 U161 ( .A(n74), .Y(n70) );
  clk1a3 U162 ( .A(n73), .Y(n71) );
  and2c3 U163 ( .A(n22), .B(n486), .Y(n276) );
  inv1a3 U164 ( .A(n257), .Y(n496) );
  clk1b6 U165 ( .A(n110), .Y(n489) );
  inv1a3 U166 ( .A(n133), .Y(n508) );
  inv1a3 U167 ( .A(n231), .Y(n501) );
  inv1a1 U168 ( .A(n216), .Y(n500) );
  clk1b6 U169 ( .A(n182), .Y(n527) );
  inv1a1 U171 ( .A(n171), .Y(n526) );
  and2c1 U172 ( .A(n332), .B(n341), .Y(N317) );
  inv1a1 U173 ( .A(n185), .Y(n519) );
  buf1a9 U174 ( .A(n534), .Y(n11) );
  buf1a9 U175 ( .A(n534), .Y(n10) );
  inv1a1 U176 ( .A(\gt_309/A[3] ), .Y(n483) );
  inv1a1 U177 ( .A(n105), .Y(\gt_309/A[3] ) );
  inv1a1 U178 ( .A(n106), .Y(\gt_309/A[1] ) );
  clk1a6 U179 ( .A(n495), .Y(n8) );
  clk1a6 U180 ( .A(n495), .Y(n7) );
  clk1a6 U181 ( .A(n495), .Y(n6) );
  clk1a6 U182 ( .A(N351), .Y(n15) );
  clk1a6 U183 ( .A(N351), .Y(n14) );
  clk1a6 U185 ( .A(N351), .Y(n13) );
  clk1a3 U186 ( .A(n27), .Y(n22) );
  inv1a1 U187 ( .A(n17), .Y(n27) );
  clk1a3 U189 ( .A(n26), .Y(n23) );
  inv1a1 U190 ( .A(n17), .Y(n26) );
  clk1a3 U191 ( .A(n25), .Y(n24) );
  inv1a1 U192 ( .A(rst), .Y(n25) );
  clk1a3 U193 ( .A(n534), .Y(n12) );
  clk1a3 U194 ( .A(n495), .Y(n9) );
  clk1a3 U195 ( .A(N351), .Y(n16) );
  clk1a3 U196 ( .A(n80), .Y(n58) );
  clk1a3 U197 ( .A(n81), .Y(n80) );
  clk1a3 U198 ( .A(n81), .Y(n79) );
  clk1a3 U199 ( .A(n82), .Y(n78) );
  clk1a3 U200 ( .A(n82), .Y(n77) );
  clk1a3 U201 ( .A(n83), .Y(n76) );
  clk1a3 U202 ( .A(n83), .Y(n75) );
  clk1a3 U204 ( .A(n84), .Y(n74) );
  clk1a3 U205 ( .A(n84), .Y(n73) );
  and3d3 U206 ( .A(n22), .B(n10), .C(n502), .Y(n260) );
  or3d3 U208 ( .A(n20), .B(n290), .C(n302), .Y(n201) );
  and2a3 U209 ( .A(n146), .B(n20), .Y(n148) );
  and2c3 U212 ( .A(n300), .B(ep0_stat[2]), .Y(n302) );
  or3d3 U213 ( .A(n188), .B(n182), .C(n19), .Y(n110) );
  or2c3 U214 ( .A(n19), .B(n159), .Y(n160) );
  and3a2 U215 ( .A(n238), .B(n219), .C(n540), .Y(n205) );
  and2c3 U216 ( .A(n504), .B(n201), .Y(n199) );
  ao1f2 U217 ( .A(n131), .B(n139), .C(n528), .Y(rom_size_dd[2]) );
  and2c3 U218 ( .A(n536), .B(n487), .Y(N351) );
  ao1f2 U219 ( .A(n131), .B(n529), .C(n524), .Y(n106) );
  and3a2 U220 ( .A(n133), .B(n509), .C(n300), .Y(n4) );
  or3d3 U221 ( .A(n193), .B(n535), .C(n196), .Y(n109) );
  and2c3 U222 ( .A(n107), .B(n21), .Y(n196) );
  and2c3 U223 ( .A(n314), .B(n502), .Y(n226) );
  or3d3 U224 ( .A(n525), .B(n509), .C(n300), .Y(n133) );
  and2c3 U225 ( .A(n171), .B(n131), .Y(n185) );
  and2a3 U227 ( .A(n265), .B(n142), .Y(n300) );
  or2c3 U228 ( .A(n514), .B(n515), .Y(n332) );
  or3d3 U229 ( .A(n238), .B(n569), .C(n501), .Y(n222) );
  clk1b6 U230 ( .A(n212), .Y(n486) );
  or3d3 U231 ( .A(n512), .B(n517), .C(n340), .Y(n339) );
  and2c3 U232 ( .A(n493), .B(n516), .Y(n340) );
  inv1a3 U233 ( .A(n159), .Y(n541) );
  inv1a3 U236 ( .A(n335), .Y(n493) );
  or2c3 U237 ( .A(n189), .B(n19), .Y(n182) );
  clk1b6 U239 ( .A(n191), .Y(n525) );
  or2c3 U240 ( .A(n338), .B(n517), .Y(n341) );
  or2c3 U241 ( .A(n527), .B(n132), .Y(n171) );
  and2a3 U242 ( .A(n246), .B(n254), .Y(n240) );
  inv1a2 U243 ( .A(n107), .Y(n495) );
  ao1f2 U244 ( .A(n202), .B(n558), .C(n243), .Y(n468) );
  or3d1 U245 ( .A(n244), .B(n550), .C(n245), .Y(n243) );
  and2a3 U247 ( .A(n246), .B(n496), .Y(n245) );
  and3d2 U248 ( .A(n333), .B(n331), .C(n493), .Y(N329) );
  inv1a1 U249 ( .A(n193), .Y(n494) );
  or2c3 U250 ( .A(n525), .B(n289), .Y(n227) );
  and3d2 U251 ( .A(n493), .B(n331), .C(n332), .Y(N330) );
  and3d2 U252 ( .A(n334), .B(n512), .C(n333), .Y(N328) );
  or2c3 U253 ( .A(n205), .B(n569), .Y(n242) );
  inv1a1 U254 ( .A(ep0_stat[2]), .Y(n490) );
  and2c1 U255 ( .A(n231), .B(n540), .Y(n230) );
  and2c1 U261 ( .A(n567), .B(n568), .Y(n293) );
  or3d1 U262 ( .A(n212), .B(n224), .C(n225), .Y(n223) );
  and2a3 U263 ( .A(n226), .B(n541), .Y(n225) );
  inv1a3 U265 ( .A(rom_size_dd[5]), .Y(n528) );
  inv1a1 U266 ( .A(n250), .Y(n539) );
  inv1a3 U267 ( .A(n142), .Y(n557) );
  inv1a1 U268 ( .A(rom_size_dd[0]), .Y(n524) );
  and2c1 U269 ( .A(n336), .B(n337), .Y(N324) );
  and2c1 U270 ( .A(n333), .B(n341), .Y(N319) );
  and2c1 U271 ( .A(n333), .B(n336), .Y(N326) );
  and2c1 U272 ( .A(n333), .B(n339), .Y(N322) );
  inv1a1 U273 ( .A(n136), .Y(n564) );
  and2c1 U274 ( .A(n332), .B(n336), .Y(N323) );
  inv1a3 U275 ( .A(n224), .Y(n534) );
  and2c1 U276 ( .A(n337), .B(n339), .Y(N320) );
  and2c1 U277 ( .A(n328), .B(n514), .Y(N332) );
  and2c1 U278 ( .A(n337), .B(n341), .Y(N318) );
  or2c1 U281 ( .A(n569), .B(n554), .Y(n218) );
  or2c1 U282 ( .A(n254), .B(n549), .Y(n259) );
  clk1b6 U283 ( .A(n188), .Y(n488) );
  inv1a1 U284 ( .A(n104), .Y(\gt_309/A[4] ) );
  or2c1 U285 ( .A(n561), .B(n562), .Y(n320) );
  or2c1 U286 ( .A(n234), .B(n19), .Y(n233) );
  clk1a3 U287 ( .A(n28), .Y(n21) );
  inv1a1 U288 ( .A(n17), .Y(n28) );
  inv1a1 U289 ( .A(n18), .Y(n17) );
  clk1a3 U290 ( .A(clk), .Y(n81) );
  clk1a3 U291 ( .A(clk), .Y(n82) );
  clk1a3 U292 ( .A(clk), .Y(n83) );
  clk1a3 U293 ( .A(clk), .Y(n84) );
  or3d1 U294 ( .A(n506), .B(n297), .C(state[0]), .Y(n296) );
  or3d1 U295 ( .A(n300), .B(n566), .C(n301), .Y(n295) );
  inv1a1 U296 ( .A(n268), .Y(n506) );
  or3d3 U297 ( .A(ctrl_in), .B(n19), .C(set_adr_pending), .Y(n146) );
  and2c3 U298 ( .A(n242), .B(get_config), .Y(n250) );
  or2c6 U299 ( .A(n19), .B(n321), .Y(n212) );
  oa1f3 U300 ( .A(state[1]), .B(n324), .C(n325), .Y(n322) );
  or3d2 U301 ( .A(reg_byte_cnt[0]), .B(ep0_re), .C(reg_byte_cnt[1]), .Y(n193)
         );
  and2c3 U302 ( .A(wValue[11]), .B(wValue[10]), .Y(n128) );
  and2c3 U303 ( .A(n564), .B(state[18]), .Y(n265) );
  or3d2 U304 ( .A(state[1]), .B(ep0_re), .C(le[7]), .Y(n324) );
  and2a3 U305 ( .A(state[12]), .B(n505), .Y(n355) );
  or2c1 U306 ( .A(reg_wphase), .B(ep0_re), .Y(n107) );
  and2c3 U307 ( .A(n139), .B(wValue[8]), .Y(rom_size_dd[5]) );
  and2c3 U308 ( .A(v_set_reg_waddr), .B(v_set_reg_raddr), .Y(n224) );
  and2c3 U309 ( .A(tx_bcnt[3]), .B(tx_bcnt[2]), .Y(n402) );
  and2c3 U310 ( .A(state[8]), .B(state[10]), .Y(n142) );
  and2c3 U311 ( .A(get_interface), .B(set_config), .Y(n254) );
  or2c3 U312 ( .A(state[6]), .B(n316), .Y(n191) );
  or2c3 U313 ( .A(n212), .B(n285), .Y(n206) );
  ao1d2 U314 ( .A(n227), .B(high_sel), .C(n20), .Y(n285) );
  oa1f3 U315 ( .A(n273), .B(n19), .C(n206), .Y(n284) );
  and2c3 U316 ( .A(n191), .B(rom_sel_r), .Y(n189) );
  or2c1 U317 ( .A(N196), .B(n488), .Y(n111) );
  or3d1 U318 ( .A(n1), .B(n527), .C(hdr6[6]), .Y(n112) );
  and2c3 U319 ( .A(set_address), .B(set_descriptor), .Y(n219) );
  and2c3 U320 ( .A(set_interface), .B(synch_frame), .Y(n246) );
  oa1f3 U321 ( .A(n273), .B(n20), .C(n485), .Y(n272) );
  and2c3 U322 ( .A(n265), .B(high_sel), .Y(n234) );
  or2c3 U323 ( .A(n338), .B(hdr1[3]), .Y(n336) );
  ao2h1 U324 ( .B(n122), .A(n133), .C(n140), .D(n141), .Y(n422) );
  or2c1 U325 ( .A(ep0_size[1]), .B(n4), .Y(n141) );
  or3d1 U327 ( .A(n564), .B(n509), .C(n142), .Y(n140) );
  ao2h1 U328 ( .B(n120), .A(n133), .C(n134), .D(n135), .Y(n421) );
  or2c1 U329 ( .A(ep0_size[2]), .B(n4), .Y(n135) );
  or3d1 U330 ( .A(n136), .B(n509), .C(n137), .Y(n134) );
  and2c1 U331 ( .A(n557), .B(n565), .Y(n137) );
  ao1f2 U332 ( .A(tx_bcnt[1]), .B(n201), .C(n491), .Y(n197) );
  and2c3 U333 ( .A(wValue[3]), .B(wValue[2]), .Y(n176) );
  and2a3 U334 ( .A(state[17]), .B(high_sel), .Y(n356) );
  or3d1 U335 ( .A(n523), .B(n530), .C(n168), .Y(n165) );
  or3d1 U336 ( .A(state[1]), .B(n19), .C(n167), .Y(n166) );
  and3d2 U337 ( .A(le[5]), .B(le[7]), .C(le[6]), .Y(n168) );
  or3d3 U338 ( .A(n516), .B(n517), .C(hdr0[6]), .Y(n331) );
  oa2i2 U339 ( .A(state[13]), .B(n263), .C(n557), .D(n264), .Y(n262) );
  or3d1 U340 ( .A(n227), .B(n498), .C(n265), .Y(n263) );
  and2c3 U341 ( .A(n265), .B(n505), .Y(n264) );
  oa2i2 U342 ( .A(n267), .B(state[14]), .C(n268), .D(n269), .Y(n266) );
  and2c1 U343 ( .A(v_set_reg_raddr), .B(n270), .Y(n269) );
  and3d2 U344 ( .A(le[0]), .B(le[2]), .C(le[1]), .Y(n167) );
  or2c1 U345 ( .A(rom_adr[1]), .B(n489), .Y(n183) );
  oa1f3 U346 ( .A(N169), .B(n488), .C(n185), .Y(n184) );
  or2c1 U348 ( .A(hdr6[3]), .B(n1), .Y(n130) );
  and3d2 U349 ( .A(n5), .B(state[1]), .C(state[7]), .Y(n297) );
  or2a2 U350 ( .A(state[15]), .B(state[14]), .Y(n5) );
  or2c1 U351 ( .A(hdr6[4]), .B(n1), .Y(n127) );
  inv1a3 U353 ( .A(high_sel), .Y(n505) );
  or2c1 U355 ( .A(hdr6[5]), .B(n1), .Y(n126) );
  or2c1 U356 ( .A(hdr6[1]), .B(n1), .Y(n143) );
  ao1f2 U357 ( .A(n146), .B(n548), .C(n154), .Y(n431) );
  or2c1 U360 ( .A(funct_adr[0]), .B(n148), .Y(n154) );
  ao1f2 U362 ( .A(n146), .B(n547), .C(n153), .Y(n430) );
  or2c1 U363 ( .A(funct_adr[1]), .B(n148), .Y(n153) );
  ao1f2 U364 ( .A(n146), .B(n546), .C(n152), .Y(n429) );
  or2c1 U367 ( .A(funct_adr[2]), .B(n148), .Y(n152) );
  ao1f2 U369 ( .A(n146), .B(n545), .C(n151), .Y(n428) );
  or2c1 U370 ( .A(funct_adr[3]), .B(n148), .Y(n151) );
  ao1f2 U371 ( .A(n146), .B(n544), .C(n150), .Y(n427) );
  or2c1 U374 ( .A(funct_adr[4]), .B(n148), .Y(n150) );
  ao1f2 U376 ( .A(n146), .B(n543), .C(n149), .Y(n426) );
  or2c1 U377 ( .A(funct_adr[5]), .B(n148), .Y(n149) );
  ao1f2 U378 ( .A(n146), .B(n542), .C(n147), .Y(n425) );
  or2c1 U379 ( .A(funct_adr[6]), .B(n148), .Y(n147) );
  or2c1 U380 ( .A(hdr6[0]), .B(n1), .Y(n145) );
  or2c1 U382 ( .A(hdr6[2]), .B(n1), .Y(n138) );
  inv1a1 U384 ( .A(rom_size_dd[2]), .Y(n520) );
  inv1a3 U385 ( .A(tx_bcnt[1]), .Y(n567) );
  inv1a3 U386 ( .A(tx_bcnt[0]), .Y(n504) );
  or2c1 U387 ( .A(state[6]), .B(n232), .Y(n228) );
  or3d1 U388 ( .A(n212), .B(n538), .C(n230), .Y(n229) );
  ao2h2 U389 ( .B(n219), .A(n222), .C(n233), .D(n212), .Y(n232) );
  inv1a3 U391 ( .A(hdr1[1]), .Y(n515) );
  or2c3 U393 ( .A(hdr1[0]), .B(n515), .Y(n337) );
  ao1f2 U394 ( .A(n202), .B(n560), .C(n220), .Y(n464) );
  or3d1 U395 ( .A(n540), .B(n538), .C(n221), .Y(n220) );
  ao1f2 U396 ( .A(n222), .B(n560), .C(n223), .Y(n221) );
  inv1a1 U402 ( .A(state[5]), .Y(n560) );
  ao1f2 U403 ( .A(n202), .B(n556), .C(n239), .Y(n467) );
  or3d1 U404 ( .A(n240), .B(n241), .C(n496), .Y(n239) );
  inv1a1 U406 ( .A(state[8]), .Y(n556) );
  ao1f2 U407 ( .A(n202), .B(n510), .C(n203), .Y(n460) );
  or3d1 U408 ( .A(n501), .B(n204), .C(n205), .Y(n203) );
  ao1f2 U411 ( .A(n486), .B(n569), .C(n510), .Y(n204) );
  inv1a1 U412 ( .A(state[1]), .Y(n510) );
  ao1f2 U413 ( .A(n202), .B(n507), .C(n251), .Y(n470) );
  or3d1 U415 ( .A(n252), .B(n555), .C(n496), .Y(n251) );
  inv1a1 U416 ( .A(synch_frame), .Y(n555) );
  ao1f2 U417 ( .A(n486), .B(n549), .C(n253), .Y(n252) );
  inv1a3 U418 ( .A(get_descriptor), .Y(n540) );
  oa1f3 U419 ( .A(n379), .B(n380), .C(n565), .Y(n378) );
  oa1f3 U420 ( .A(n373), .B(n374), .C(n565), .Y(n372) );
  oa1f3 U421 ( .A(n367), .B(n368), .C(n565), .Y(n366) );
  oa1f3 U422 ( .A(n361), .B(n362), .C(n565), .Y(n360) );
  oa1f3 U423 ( .A(n349), .B(n350), .C(n565), .Y(n348) );
  and3d2 U424 ( .A(n336), .B(hdr1[0]), .C(n515), .Y(N325) );
  ao1f2 U425 ( .A(n110), .B(n562), .C(n119), .Y(n414) );
  ao1f2 U426 ( .A(n110), .B(n561), .C(n121), .Y(n415) );
  or2c3 U427 ( .A(wValue[9]), .B(n128), .Y(n139) );
  and3d2 U428 ( .A(n339), .B(hdr1[0]), .C(n515), .Y(N321) );
  and3d2 U429 ( .A(n334), .B(hdr0[6]), .C(n332), .Y(N327) );
  and2c3 U430 ( .A(ep0_size[6]), .B(ep0_size[5]), .Y(n572) );
  or3d1 U431 ( .A(n305), .B(n306), .C(n307), .Y(n304) );
  and3c1 U432 ( .C(n342), .A(n324), .B(hdr0[5]), .Y(n329) );
  and3d2 U433 ( .A(hdr1[5]), .B(hdr1[7]), .C(hdr1[6]), .Y(n342) );
  or2c3 U434 ( .A(n128), .B(wValue[8]), .Y(rom_size_dd[0]) );
  or3d3 U435 ( .A(hdr1[4]), .B(n329), .C(n330), .Y(n328) );
  and2c3 U436 ( .A(hdr1[1]), .B(n331), .Y(n330) );
  oa1f3 U437 ( .A(n566), .B(n509), .C(ctrl_in), .Y(n325) );
  and3d2 U438 ( .A(n326), .B(n10), .C(n314), .Y(N361) );
  or2c1 U439 ( .A(hdr_done_r), .B(n205), .Y(n326) );
  and3d2 U440 ( .A(hdr0[2]), .B(hdr0[4]), .C(hdr0[3]), .Y(n406) );
  inv1a3 U441 ( .A(state[13]), .Y(n566) );
  and3d2 U442 ( .A(n320), .B(rom_size[0]), .C(n189), .Y(n319) );
  or3d3 U443 ( .A(n20), .B(n490), .C(n190), .Y(n188) );
  ao1f2 U444 ( .A(n544), .B(n160), .C(n163), .Y(n435) );
  or2c1 U445 ( .A(wValue[4]), .B(n541), .Y(n163) );
  ao1f2 U446 ( .A(n543), .B(n160), .C(n162), .Y(n434) );
  or2c1 U447 ( .A(wValue[5]), .B(n541), .Y(n162) );
  ao1f2 U448 ( .A(n542), .B(n160), .C(n161), .Y(n433) );
  or2c1 U449 ( .A(wValue[6]), .B(n541), .Y(n161) );
  and2c1 U450 ( .A(ctrl_in), .B(n159), .Y(n158) );
  inv1a3 U451 ( .A(state[0]), .Y(n502) );
  ao1f2 U452 ( .A(n537), .B(n109), .C(n194), .Y(n455) );
  ao1d2 U453 ( .A(n109), .B(n108), .C(reg_byte_cnt[1]), .Y(n194) );
  inv1a3 U454 ( .A(hdr1[3]), .Y(n517) );
  oa1d2 U455 ( .A(set_config), .B(configured), .C(n24), .Y(n424) );
  or3d1 U456 ( .A(n250), .B(n254), .C(state[11]), .Y(n253) );
  ao1f2 U457 ( .A(high_sel), .B(n492), .C(n343), .Y(N268) );
  or2c1 U458 ( .A(fifo_we_rom_r2), .B(n525), .Y(n343) );
  inv1a1 U459 ( .A(n302), .Y(n492) );
  oa1f3 U460 ( .A(n400), .B(n401), .C(n565), .Y(n399) );
  ao1f2 U461 ( .A(v_set_reg_waddr), .B(n536), .C(n533), .Y(n408) );
  oa2i6 U462 ( .A(n522), .B(n521), .C(wValue[2]), .D(wValue[3]), .Y(n131) );
  ao1f2 U463 ( .A(n274), .B(n559), .C(n275), .Y(n475) );
  inv1a1 U464 ( .A(state[16]), .Y(n559) );
  or3d1 U465 ( .A(n276), .B(state[0]), .C(n277), .Y(n275) );
  oa1f3 U466 ( .A(n276), .B(n267), .C(n486), .Y(n274) );
  ao1f2 U467 ( .A(n155), .B(n156), .C(n157), .Y(n432) );
  or2c1 U468 ( .A(set_adr_pending), .B(n19), .Y(n156) );
  or3d1 U469 ( .A(n571), .B(n569), .C(n158), .Y(n157) );
  or3d1 U470 ( .A(n571), .B(n569), .C(n570), .Y(n155) );
  and3d2 U471 ( .A(state[4]), .B(state[9]), .C(state[5]), .Y(n299) );
  ao1f2 U472 ( .A(n291), .B(n503), .C(n292), .Y(n480) );
  or3d1 U473 ( .A(n199), .B(n503), .C(n293), .Y(n292) );
  oa1d2 U474 ( .A(n201), .B(tx_bcnt[2]), .C(n197), .Y(n291) );
  inv1a1 U475 ( .A(tx_bcnt[3]), .Y(n503) );
  inv1a3 U476 ( .A(get_status), .Y(n554) );
  ao1f2 U477 ( .A(n21), .B(n535), .C(n192), .Y(n454) );
  ao1f2 U478 ( .A(n21), .B(n193), .C(reg_wphase), .Y(n192) );
  inv1a3 U479 ( .A(wValue[9]), .Y(n529) );
  or3d1 U480 ( .A(n20), .B(n109), .C(n195), .Y(n108) );
  and2c1 U481 ( .A(v_set_reg_waddr), .B(n494), .Y(n195) );
  oa1f3 U482 ( .A(n403), .B(n404), .C(n505), .Y(n398) );
  or2c1 U483 ( .A(vendor_data[8]), .B(state[17]), .Y(n404) );
  and3d2 U484 ( .A(n563), .B(hdr0[1]), .C(hdr0[0]), .Y(n405) );
  ao1d2 U485 ( .A(vendor_data[9]), .B(n356), .C(n392), .Y(n391) );
  or3d1 U486 ( .A(state[12]), .B(high_sel), .C(frame_no[9]), .Y(n392) );
  ao1d2 U487 ( .A(vendor_data[10]), .B(n356), .C(n385), .Y(n384) );
  or3d1 U488 ( .A(state[12]), .B(high_sel), .C(frame_no[10]), .Y(n385) );
  inv1a3 U489 ( .A(ctrl_out), .Y(n571) );
  inv1a3 U490 ( .A(le[4]), .Y(n530) );
  inv1a3 U491 ( .A(le[3]), .Y(n523) );
  oa1f3 U492 ( .A(n533), .B(n327), .C(n23), .Y(N353) );
  or2c1 U493 ( .A(n494), .B(reg_wphase), .Y(n327) );
  or3d1 U494 ( .A(n569), .B(n554), .C(state[3]), .Y(n213) );
  ao1f2 U495 ( .A(tx_bcnt[0]), .B(n201), .C(n200), .Y(n294) );
  and2c1 U496 ( .A(hdr1[0]), .B(n328), .Y(N331) );
  or3d1 U497 ( .A(n388), .B(n389), .C(n390), .Y(N261) );
  ao1d2 U498 ( .A(n393), .B(n394), .C(state[18]), .Y(n389) );
  oa1f3 U499 ( .A(rom_data[1]), .B(n525), .C(n391), .Y(n390) );
  or3d1 U500 ( .A(n381), .B(n382), .C(n383), .Y(N262) );
  ao1d2 U501 ( .A(n386), .B(n387), .C(state[18]), .Y(n382) );
  oa1f3 U502 ( .A(rom_data[2]), .B(n525), .C(n384), .Y(n383) );
  or3d1 U503 ( .A(n395), .B(n396), .C(n397), .Y(N260) );
  oa2i2 U504 ( .A(configured), .B(state[8]), .C(n398), .D(n399), .Y(n397) );
  or2c1 U505 ( .A(vendor_data[0]), .B(n347), .Y(n396) );
  or3d1 U506 ( .A(n375), .B(n376), .C(n377), .Y(N263) );
  or2c1 U507 ( .A(frame_no[3]), .B(n355), .Y(n376) );
  oa1f3 U508 ( .A(vendor_data[3]), .B(n347), .C(n378), .Y(n377) );
  or3d1 U509 ( .A(n369), .B(n370), .C(n371), .Y(N264) );
  or2c1 U510 ( .A(frame_no[4]), .B(n355), .Y(n370) );
  oa1f3 U511 ( .A(vendor_data[4]), .B(n347), .C(n372), .Y(n371) );
  or3d1 U512 ( .A(n363), .B(n364), .C(n365), .Y(N265) );
  or2c1 U513 ( .A(frame_no[5]), .B(n355), .Y(n364) );
  oa1f3 U514 ( .A(vendor_data[5]), .B(n347), .C(n366), .Y(n365) );
  or3d1 U515 ( .A(n357), .B(n358), .C(n359), .Y(N266) );
  or2c1 U516 ( .A(frame_no[6]), .B(n355), .Y(n358) );
  oa1f3 U517 ( .A(vendor_data[6]), .B(n347), .C(n360), .Y(n359) );
  or3d1 U518 ( .A(n344), .B(n345), .C(n346), .Y(N267) );
  or2c1 U519 ( .A(frame_no[7]), .B(n355), .Y(n345) );
  oa1f3 U520 ( .A(vendor_data[7]), .B(n347), .C(n348), .Y(n346) );
  ao1d2 U521 ( .A(n489), .B(rom_size[4]), .C(n115), .Y(n412) );
  or3d1 U522 ( .A(n177), .B(n178), .C(n179), .Y(n446) );
  or2c1 U523 ( .A(N172), .B(n488), .Y(n177) );
  or3d1 U524 ( .A(n526), .B(wValue[0]), .C(n176), .Y(n178) );
  inv1a1 U525 ( .A(set_config), .Y(n551) );
  ao1d2 U526 ( .A(state[0]), .B(n234), .C(n498), .Y(n313) );
  ao1d2 U527 ( .A(n489), .B(rom_size[5]), .C(n113), .Y(n411) );
  ao1d2 U528 ( .A(n489), .B(rom_size[3]), .C(n117), .Y(n413) );
  inv1a1 U529 ( .A(n86), .Y(N193) );
  or3d1 U530 ( .A(n170), .B(n171), .C(n172), .Y(n444) );
  or2c1 U531 ( .A(N174), .B(n488), .Y(n170) );
  or2c1 U532 ( .A(rom_adr[6]), .B(n489), .Y(n172) );
  ao1d2 U533 ( .A(n489), .B(rom_size[0]), .C(n123), .Y(n416) );
  ao1d2 U534 ( .A(n197), .B(tx_bcnt[2]), .C(n198), .Y(n457) );
  or3d1 U535 ( .A(n199), .B(n568), .C(tx_bcnt[1]), .Y(n198) );
  and3c1 U536 ( .C(n240), .A(v_set_feature), .B(v_set_int), .Y(n283) );
  or3d1 U537 ( .A(n186), .B(n519), .C(n187), .Y(n449) );
  or2c1 U538 ( .A(N168), .B(n488), .Y(n186) );
  or2c1 U539 ( .A(rom_adr[0]), .B(n489), .Y(n187) );
  and3c1 U540 ( .C(halt), .A(n24), .B(ctrl_setup), .Y(n481) );
  ao1d2 U541 ( .A(n206), .B(state[2]), .C(n207), .Y(n461) );
  or3d1 U542 ( .A(n500), .B(n208), .C(n209), .Y(n207) );
  and2c1 U543 ( .A(set_feature), .B(clear_feature), .Y(n209) );
  ao1d2 U544 ( .A(n485), .B(state[10]), .C(n247), .Y(n469) );
  or3d1 U545 ( .A(n246), .B(n248), .C(n496), .Y(n247) );
  ao1f2 U546 ( .A(n486), .B(n550), .C(n249), .Y(n248) );
  or3d1 U547 ( .A(n250), .B(n551), .C(state[10]), .Y(n249) );
  or3d1 U548 ( .A(hdr6[6]), .B(n1), .C(n508), .Y(n125) );
  ao1d2 U549 ( .A(n485), .B(state[3]), .C(n210), .Y(n462) );
  or3d1 U550 ( .A(n211), .B(n553), .C(n500), .Y(n210) );
  inv1a1 U551 ( .A(set_feature), .Y(n553) );
  ao1d2 U552 ( .A(n212), .B(clear_feature), .C(n213), .Y(n211) );
  or3d1 U553 ( .A(n173), .B(n174), .C(n175), .Y(n445) );
  or2c1 U554 ( .A(N173), .B(n488), .Y(n173) );
  or3d1 U555 ( .A(n526), .B(wValue[1]), .C(n176), .Y(n174) );
  or2c1 U556 ( .A(rom_adr[5]), .B(n489), .Y(n175) );
  inv1a1 U557 ( .A(le[5]), .Y(n531) );
  inv1a1 U558 ( .A(le[2]), .Y(n518) );
  inv1a1 U559 ( .A(le[1]), .Y(n513) );
  inv1a1 U560 ( .A(le[0]), .Y(n511) );
  inv1a1 U561 ( .A(le[6]), .Y(n532) );
  or3d1 U562 ( .A(n180), .B(n519), .C(n181), .Y(n447) );
  or2c1 U563 ( .A(N170), .B(n488), .Y(n180) );
  or2c1 U564 ( .A(rom_adr[2]), .B(n489), .Y(n181) );
  or2c1 U565 ( .A(n280), .B(n281), .Y(n476) );
  or3d1 U566 ( .A(n260), .B(n212), .C(v_get_status), .Y(n281) );
  ao1f2 U567 ( .A(n282), .B(n206), .C(state[17]), .Y(n280) );
  and3a2 U568 ( .A(n283), .B(n260), .C(n250), .Y(n282) );
  inv1a1 U569 ( .A(ctrl_in), .Y(n570) );
  inv1a1 U570 ( .A(rom_size[0]), .Y(N190) );
  or2c1 U571 ( .A(n286), .B(n287), .Y(n478) );
  or3d1 U572 ( .A(n276), .B(state[0]), .C(v_set_reg_raddr), .Y(n287) );
  ao1f2 U573 ( .A(n288), .B(n485), .C(state[19]), .Y(n286) );
  and3d2 U574 ( .A(n499), .B(v_set_reg_waddr), .C(n22), .Y(n288) );
  inv1a1 U575 ( .A(wValue[0]), .Y(n521) );
  inv1a1 U576 ( .A(wValue[1]), .Y(n522) );
  or2c1 U577 ( .A(n255), .B(n256), .Y(n471) );
  or3d1 U578 ( .A(n496), .B(n212), .C(synch_frame), .Y(n256) );
  ao1f2 U579 ( .A(n258), .B(n206), .C(state[12]), .Y(n255) );
  and3d2 U580 ( .A(n259), .B(n257), .C(n539), .Y(n258) );
  or2c1 U581 ( .A(n235), .B(n236), .Y(n466) );
  or3d1 U582 ( .A(n501), .B(n212), .C(set_descriptor), .Y(n236) );
  ao1f2 U583 ( .A(n237), .B(n485), .C(state[7]), .Y(n235) );
  and3d2 U584 ( .A(n222), .B(set_address), .C(get_descriptor), .Y(n237) );
  or2c1 U585 ( .A(n214), .B(n215), .Y(n463) );
  or3d1 U586 ( .A(n500), .B(n212), .C(set_feature), .Y(n215) );
  ao1f2 U587 ( .A(n217), .B(n485), .C(state[4]), .Y(n214) );
  and3d2 U588 ( .A(n218), .B(clear_feature), .C(n216), .Y(n217) );
  oa2i2 U589 ( .A(n278), .B(n279), .C(v_get_status), .D(n11), .Y(n277) );
  and2c3 U590 ( .A(v_set_int), .B(v_set_feature), .Y(n278) );
  or3d1 U591 ( .A(n250), .B(n240), .C(state[16]), .Y(n279) );
  inv1a1 U592 ( .A(n310), .Y(n497) );
  oa2i2 U593 ( .A(state[6]), .B(n311), .C(n312), .D(n313), .Y(n310) );
  or2c1 U594 ( .A(n297), .B(n19), .Y(n312) );
  or3d1 U595 ( .A(n289), .B(n502), .C(n316), .Y(n311) );
  inv1a1 U596 ( .A(hdr6[1]), .Y(n482) );
  inv1a1 U597 ( .A(hdr6[6]), .Y(n315) );
  or2b1 U598 ( .B(rom_size[1]), .A(N190), .Y(n85) );
  ao1d1 U599 ( .A(rom_size[0]), .B(rom_size[1]), .C(n85), .Y(N191) );
  ao1d1 U600 ( .A(n85), .B(rom_size[2]), .C(n3), .Y(N192) );
  oa1f1 U601 ( .A(n3), .B(rom_size[3]), .C(n87), .Y(n86) );
  ao1f1 U602 ( .A(n87), .B(n90), .C(n88), .Y(N194) );
  xor2b1 U603 ( .A(rom_size[5]), .B(n88), .Y(N195) );
  xor2a1 U604 ( .A(rom_size[6]), .B(n89), .Y(N196) );
  and2b1 U605 ( .B(\gt_309/A[4] ), .A(hdr6[4]), .Y(n92) );
  ao4e1 U606 ( .B(n92), .A(hdr6[5]), .C(hdr6[5]), .D(n528), .Y(n91) );
  oa1f1 U607 ( .A(n92), .B(rom_size_dd[5]), .C(n91), .Y(n103) );
  or2b1 U608 ( .B(hdr6[2]), .A(rom_size_dd[2]), .Y(n95) );
  ao4f1 U609 ( .A(hdr6[3]), .B(n483), .C(hdr6[3]), .D(n95), .Y(n101) );
  and2b1 U610 ( .B(hdr6[2]), .A(rom_size_dd[2]), .Y(n93) );
  oa4a1 U611 ( .A(hdr6[3]), .B(n93), .C(n93), .D(n483), .Y(n97) );
  oa1d1 U612 ( .A(n482), .B(\gt_309/A[1] ), .C(hdr6[0]), .Y(n94) );
  oa4f1 U613 ( .A(\gt_309/A[1] ), .B(n482), .C(n94), .D(rom_size_dd[0]), .Y(
        n96) );
  ao4f1 U614 ( .A(n97), .B(n96), .C(n95), .D(n483), .Y(n100) );
  and2b1 U615 ( .B(hdr6[4]), .A(\gt_309/A[4] ), .Y(n98) );
  ao4f1 U616 ( .A(n98), .B(n528), .C(hdr6[5]), .D(n98), .Y(n99) );
  ao2i1 U617 ( .A(n101), .B(n100), .C(n99), .D(n315), .Y(n102) );
  clk1b6 U618 ( .A(state[18]), .Y(n565) );
endmodule


module usb1_rom1 ( clk, adr, dout );
  input [6:0] adr;
  output [7:0] dout;
  input clk;
  wire   N15, N40, N42, N46, N51, N70, N88, N121, n21, n22, n23, n24, n25, n26,
         n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
         n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
         n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
         n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n1, n2, n3, n4,
         n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19,
         n20, n80, n81;

  ao2i3 U3 ( .A(adr[3]), .B(n21), .C(n22), .D(n23), .Y(N88) );
  and2b2 U5 ( .B(n28), .A(n29), .Y(n27) );
  ao4f3 U10 ( .A(adr[0]), .B(n80), .C(n11), .D(n19), .Y(n35) );
  ao4f3 U13 ( .A(n3), .B(n42), .C(n43), .D(n16), .Y(n40) );
  oa4f3 U14 ( .A(n44), .B(n45), .C(n46), .D(n28), .Y(n43) );
  oa4e3 U20 ( .C(n50), .D(n34), .B(n33), .A(n25), .Y(n37) );
  ao2i3 U21 ( .A(n33), .B(n51), .C(n52), .D(n6), .Y(N51) );
  ao2i3 U24 ( .A(adr[5]), .B(n36), .C(n33), .D(n54), .Y(N46) );
  ao2i3 U30 ( .A(adr[4]), .B(n60), .C(n61), .D(n33), .Y(n59) );
  ao2i3 U33 ( .A(n64), .B(n18), .C(adr[3]), .D(n65), .Y(n57) );
  ao2i3 U36 ( .A(n17), .B(n51), .C(n66), .D(n6), .Y(N15) );
  or2b2 U48 ( .B(n51), .A(n46), .Y(n68) );
  ao2i3 U55 ( .A(n53), .B(n19), .C(n75), .D(n81), .Y(n74) );
  oa4f3 U62 ( .A(n77), .B(n8), .C(n7), .D(n11), .Y(n69) );
  oa4f3 U66 ( .A(n62), .B(adr[0]), .C(n25), .D(adr[5]), .Y(n79) );
  and2c6 U67 ( .A(adr[0]), .B(adr[1]), .Y(n25) );
  fdf1a3 \dout_reg[7]  ( .D(N15), .CLK(n2), .Q(dout[7]) );
  fdf1a3 \dout_reg[6]  ( .D(N40), .CLK(n2), .Q(dout[6]) );
  fdf1a3 \dout_reg[5]  ( .D(N42), .CLK(n2), .Q(dout[5]) );
  fdf1a3 \dout_reg[4]  ( .D(N46), .CLK(n2), .Q(dout[4]) );
  fdf1a3 \dout_reg[3]  ( .D(N51), .CLK(n2), .Q(dout[3]) );
  fdf1a3 \dout_reg[0]  ( .D(N121), .CLK(n2), .Q(dout[0]) );
  fdf1a3 \dout_reg[2]  ( .D(N70), .CLK(n2), .Q(dout[2]) );
  fdf1a3 \dout_reg[1]  ( .D(N88), .CLK(n2), .Q(dout[1]) );
  inv1a3 U4 ( .A(adr[4]), .Y(n20) );
  and2c3 U6 ( .A(n80), .B(adr[4]), .Y(n46) );
  inv1a3 U7 ( .A(adr[3]), .Y(n8) );
  or2c1 U8 ( .A(n50), .B(n16), .Y(n42) );
  or3d1 U9 ( .A(n11), .B(n20), .C(n7), .Y(n47) );
  or3d1 U11 ( .A(n46), .B(n16), .C(n63), .Y(n41) );
  or3d1 U12 ( .A(n20), .B(n81), .C(n25), .Y(n36) );
  inv1a1 U15 ( .A(n65), .Y(n10) );
  clk1a6 U16 ( .A(adr[2]), .Y(n1) );
  or3d1 U17 ( .A(n1), .B(n8), .C(n78), .Y(n60) );
  and2c1 U18 ( .A(adr[6]), .B(adr[5]), .Y(n78) );
  inv1a1 U19 ( .A(n42), .Y(n15) );
  inv1a1 U22 ( .A(n55), .Y(n6) );
  or2c3 U23 ( .A(n47), .B(n41), .Y(n55) );
  inv1a3 U25 ( .A(n49), .Y(n3) );
  inv1a1 U26 ( .A(n29), .Y(n18) );
  inv1a1 U27 ( .A(n24), .Y(n17) );
  inv1a1 U28 ( .A(n36), .Y(n13) );
  or2c1 U29 ( .A(n68), .B(n17), .Y(n72) );
  inv1a1 U31 ( .A(n41), .Y(n9) );
  and2c3 U32 ( .A(n8), .B(n11), .Y(n49) );
  and2c3 U34 ( .A(n14), .B(n1), .Y(n34) );
  and2c3 U35 ( .A(n20), .B(n80), .Y(n50) );
  and2c3 U37 ( .A(n81), .B(n1), .Y(n24) );
  ao1f2 U38 ( .A(n14), .B(n3), .C(n12), .Y(n45) );
  and3d2 U39 ( .A(n10), .B(n32), .C(n8), .Y(n31) );
  oa1f3 U40 ( .A(n7), .B(n25), .C(n55), .Y(n54) );
  or3d1 U41 ( .A(n34), .B(n4), .C(n44), .Y(n52) );
  inv1a1 U42 ( .A(n53), .Y(n4) );
  oa1f3 U43 ( .A(n1), .B(n46), .C(n15), .Y(n32) );
  or2c1 U44 ( .A(n67), .B(n8), .Y(n66) );
  ao1f2 U45 ( .A(n12), .B(n29), .C(n68), .Y(n67) );
  inv1a3 U46 ( .A(n25), .Y(n12) );
  and2c3 U47 ( .A(n49), .B(n63), .Y(n53) );
  ao1f2 U49 ( .A(n14), .B(n81), .C(n33), .Y(n30) );
  inv1a3 U50 ( .A(n44), .Y(n19) );
  or2c3 U51 ( .A(n50), .B(n1), .Y(n29) );
  inv1a3 U52 ( .A(n1), .Y(n16) );
  inv1a3 U53 ( .A(n60), .Y(n7) );
  or2c1 U54 ( .A(n47), .B(n48), .Y(n26) );
  or3d1 U56 ( .A(n34), .B(n20), .C(n49), .Y(n48) );
  and2c3 U57 ( .A(n1), .B(n19), .Y(n64) );
  or3d1 U58 ( .A(n69), .B(n70), .C(n71), .Y(N121) );
  oa2i2 U59 ( .A(n15), .B(n14), .C(n72), .D(n73), .Y(n71) );
  oa4d1 U60 ( .B(n14), .A(n74), .D(n32), .C(n3), .Y(n70) );
  or3d1 U61 ( .A(n37), .B(n5), .C(n38), .Y(N70) );
  oa2i2 U63 ( .A(n24), .B(n39), .C(n40), .D(n9), .Y(n38) );
  inv1a1 U64 ( .A(n26), .Y(n5) );
  and3a2 U65 ( .A(n46), .B(n16), .C(n49), .Y(n73) );
  clk1a3 U68 ( .A(clk), .Y(n2) );
  and2c3 U69 ( .A(adr[0]), .B(adr[3]), .Y(n63) );
  and3d2 U70 ( .A(adr[4]), .B(adr[5]), .C(n1), .Y(n62) );
  and2c3 U71 ( .A(n20), .B(adr[5]), .Y(n44) );
  inv1a3 U72 ( .A(adr[0]), .Y(n11) );
  or2c1 U73 ( .A(n63), .B(n18), .Y(n61) );
  or2c3 U74 ( .A(n62), .B(adr[3]), .Y(n33) );
  inv1a3 U75 ( .A(adr[1]), .Y(n14) );
  and2c3 U76 ( .A(n11), .B(adr[1]), .Y(n65) );
  or3d1 U77 ( .A(adr[0]), .B(n76), .C(n1), .Y(n75) );
  ao1f2 U78 ( .A(n8), .B(n20), .C(n19), .Y(n76) );
  oa2i2 U79 ( .A(n24), .B(n25), .C(n26), .D(n27), .Y(n23) );
  oa1f3 U80 ( .A(n34), .B(n35), .C(n13), .Y(n21) );
  oa1f1 U81 ( .A(adr[0]), .B(n30), .C(n31), .Y(n22) );
  ao1f2 U82 ( .A(adr[3]), .B(adr[1]), .C(n12), .Y(n28) );
  inv1a3 U83 ( .A(adr[6]), .Y(n81) );
  ao1f1 U84 ( .A(adr[0]), .B(n33), .C(n54), .Y(N42) );
  inv1a3 U85 ( .A(adr[5]), .Y(n80) );
  or2c3 U86 ( .A(adr[1]), .B(n11), .Y(n51) );
  ao1f2 U87 ( .A(n1), .B(n10), .C(n79), .Y(n77) );
  or2c1 U88 ( .A(adr[1]), .B(adr[0]), .Y(n39) );
  or3d1 U89 ( .A(n56), .B(n57), .C(n58), .Y(N40) );
  or3d1 U90 ( .A(adr[6]), .B(n1), .C(n25), .Y(n56) );
  oa1f3 U91 ( .A(adr[1]), .B(n59), .C(n55), .Y(n58) );
endmodule


module sync_fifo_W8_D8 ( clk, reset_n, clr, wr_en, wr_data, full, empty, rd_en, 
        rd_data );
  input [7:0] wr_data;
  output [7:0] rd_data;
  input clk, reset_n, clr, wr_en, rd_en;
  output full, empty;
  wire   N19, N20, N21, N53, N66, \mem[7][7] , \mem[7][6] , \mem[7][5] ,
         \mem[7][4] , \mem[7][3] , \mem[7][2] , \mem[7][1] , \mem[7][0] ,
         \mem[6][7] , \mem[6][6] , \mem[6][5] , \mem[6][4] , \mem[6][3] ,
         \mem[6][2] , \mem[6][1] , \mem[6][0] , \mem[5][7] , \mem[5][6] ,
         \mem[5][5] , \mem[5][4] , \mem[5][3] , \mem[5][2] , \mem[5][1] ,
         \mem[5][0] , \mem[4][7] , \mem[4][6] , \mem[4][5] , \mem[4][4] ,
         \mem[4][3] , \mem[4][2] , \mem[4][1] , \mem[4][0] , \mem[3][7] ,
         \mem[3][6] , \mem[3][5] , \mem[3][4] , \mem[3][3] , \mem[3][2] ,
         \mem[3][1] , \mem[3][0] , \mem[2][7] , \mem[2][6] , \mem[2][5] ,
         \mem[2][4] , \mem[2][3] , \mem[2][2] , \mem[2][1] , \mem[2][0] ,
         \mem[1][7] , \mem[1][6] , \mem[1][5] , \mem[1][4] , \mem[1][3] ,
         \mem[1][2] , \mem[1][1] , \mem[1][0] , \mem[0][7] , \mem[0][6] ,
         \mem[0][5] , \mem[0][4] , \mem[0][3] , \mem[0][2] , \mem[0][1] ,
         \mem[0][0] , n43, n45, n48, n50, n54, n55, n56, n57, n58, n59, n60,
         n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
         n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n1, n2,
         n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
         n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
         n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n44, n46, n47,
         n49, n51, n52, n53;
  wire   [2:0] wr_ptr;

  ao4a3 U34 ( .A(n62), .B(wr_ptr[1]), .C(n45), .D(n38), .Y(n85) );
  ao4f3 U37 ( .A(n42), .B(n64), .C(wr_ptr[0]), .D(n63), .Y(n86) );
  xor2b2 U48 ( .A(n75), .B(n76), .Y(n67) );
  xor2a2 U50 ( .A(n78), .B(n79), .Y(n71) );
  xor2b2 U52 ( .A(N21), .B(n46), .Y(n75) );
  fac2a1 U70 ( .A(N20), .B(n77), .CI(n44), .CO(n76) );
  fdef1a3 \mem_reg[7][7]  ( .D(wr_data[7]), .E(n1), .CLK(n31), .Q(\mem[7][7] )
         );
  fdef1a3 \mem_reg[7][6]  ( .D(wr_data[6]), .E(n1), .CLK(n31), .Q(\mem[7][6] )
         );
  fdef1a3 \mem_reg[7][5]  ( .D(wr_data[5]), .E(n1), .CLK(n31), .Q(\mem[7][5] )
         );
  fdef1a3 \mem_reg[7][4]  ( .D(wr_data[4]), .E(n1), .CLK(n31), .Q(\mem[7][4] )
         );
  fdef1a3 \mem_reg[7][3]  ( .D(wr_data[3]), .E(n1), .CLK(n31), .Q(\mem[7][3] )
         );
  fdef1a3 \mem_reg[7][2]  ( .D(wr_data[2]), .E(n1), .CLK(n31), .Q(\mem[7][2] )
         );
  fdef1a3 \mem_reg[7][1]  ( .D(wr_data[1]), .E(n1), .CLK(n31), .Q(\mem[7][1] )
         );
  fdef1a3 \mem_reg[7][0]  ( .D(wr_data[0]), .E(n1), .CLK(n31), .Q(\mem[7][0] )
         );
  fdef1a3 \mem_reg[3][7]  ( .D(wr_data[7]), .E(n6), .CLK(n28), .Q(\mem[3][7] )
         );
  fdef1a3 \mem_reg[3][6]  ( .D(wr_data[6]), .E(n6), .CLK(n28), .Q(\mem[3][6] )
         );
  fdef1a3 \mem_reg[3][5]  ( .D(wr_data[5]), .E(n6), .CLK(n28), .Q(\mem[3][5] )
         );
  fdef1a3 \mem_reg[3][4]  ( .D(wr_data[4]), .E(n6), .CLK(n28), .Q(\mem[3][4] )
         );
  fdef1a3 \mem_reg[3][3]  ( .D(wr_data[3]), .E(n6), .CLK(n28), .Q(\mem[3][3] )
         );
  fdef1a3 \mem_reg[3][2]  ( .D(wr_data[2]), .E(n6), .CLK(n28), .Q(\mem[3][2] )
         );
  fdef1a3 \mem_reg[3][1]  ( .D(wr_data[1]), .E(n6), .CLK(n28), .Q(\mem[3][1] )
         );
  fdef1a3 \mem_reg[3][0]  ( .D(wr_data[0]), .E(n6), .CLK(n28), .Q(\mem[3][0] )
         );
  fdef1a3 \mem_reg[6][7]  ( .D(wr_data[7]), .E(n8), .CLK(n31), .Q(\mem[6][7] )
         );
  fdef1a3 \mem_reg[6][6]  ( .D(wr_data[6]), .E(n8), .CLK(n31), .Q(\mem[6][6] )
         );
  fdef1a3 \mem_reg[6][5]  ( .D(wr_data[5]), .E(n8), .CLK(n31), .Q(\mem[6][5] )
         );
  fdef1a3 \mem_reg[6][4]  ( .D(wr_data[4]), .E(n8), .CLK(n30), .Q(\mem[6][4] )
         );
  fdef1a3 \mem_reg[6][3]  ( .D(wr_data[3]), .E(n8), .CLK(n30), .Q(\mem[6][3] )
         );
  fdef1a3 \mem_reg[6][2]  ( .D(wr_data[2]), .E(n8), .CLK(n30), .Q(\mem[6][2] )
         );
  fdef1a3 \mem_reg[6][1]  ( .D(wr_data[1]), .E(n8), .CLK(n30), .Q(\mem[6][1] )
         );
  fdef1a3 \mem_reg[6][0]  ( .D(wr_data[0]), .E(n8), .CLK(n30), .Q(\mem[6][0] )
         );
  fdef1a3 \mem_reg[4][7]  ( .D(wr_data[7]), .E(n3), .CLK(n29), .Q(\mem[4][7] )
         );
  fdef1a3 \mem_reg[4][6]  ( .D(wr_data[6]), .E(n3), .CLK(n29), .Q(\mem[4][6] )
         );
  fdef1a3 \mem_reg[4][5]  ( .D(wr_data[5]), .E(n3), .CLK(n29), .Q(\mem[4][5] )
         );
  fdef1a3 \mem_reg[4][4]  ( .D(wr_data[4]), .E(n3), .CLK(n29), .Q(\mem[4][4] )
         );
  fdef1a3 \mem_reg[4][3]  ( .D(wr_data[3]), .E(n3), .CLK(n29), .Q(\mem[4][3] )
         );
  fdef1a3 \mem_reg[4][2]  ( .D(wr_data[2]), .E(n3), .CLK(n29), .Q(\mem[4][2] )
         );
  fdef1a3 \mem_reg[4][1]  ( .D(wr_data[1]), .E(n3), .CLK(n29), .Q(\mem[4][1] )
         );
  fdef1a3 \mem_reg[4][0]  ( .D(wr_data[0]), .E(n3), .CLK(n29), .Q(\mem[4][0] )
         );
  fdef1a3 \mem_reg[2][7]  ( .D(wr_data[7]), .E(n7), .CLK(n28), .Q(\mem[2][7] )
         );
  fdef1a3 \mem_reg[2][6]  ( .D(wr_data[6]), .E(n7), .CLK(n28), .Q(\mem[2][6] )
         );
  fdef1a3 \mem_reg[2][5]  ( .D(wr_data[5]), .E(n7), .CLK(n28), .Q(\mem[2][5] )
         );
  fdef1a3 \mem_reg[2][4]  ( .D(wr_data[4]), .E(n7), .CLK(n27), .Q(\mem[2][4] )
         );
  fdef1a3 \mem_reg[2][3]  ( .D(wr_data[3]), .E(n7), .CLK(n27), .Q(\mem[2][3] )
         );
  fdef1a3 \mem_reg[2][2]  ( .D(wr_data[2]), .E(n7), .CLK(n27), .Q(\mem[2][2] )
         );
  fdef1a3 \mem_reg[2][1]  ( .D(wr_data[1]), .E(n7), .CLK(n27), .Q(\mem[2][1] )
         );
  fdef1a3 \mem_reg[2][0]  ( .D(wr_data[0]), .E(n7), .CLK(n27), .Q(\mem[2][0] )
         );
  fdef1a3 \mem_reg[0][0]  ( .D(wr_data[0]), .E(n2), .CLK(n29), .Q(\mem[0][0] )
         );
  fdef1a3 \mem_reg[0][7]  ( .D(wr_data[7]), .E(n2), .CLK(n26), .Q(\mem[0][7] )
         );
  fdef1a3 \mem_reg[0][6]  ( .D(wr_data[6]), .E(n2), .CLK(n26), .Q(\mem[0][6] )
         );
  fdef1a3 \mem_reg[0][5]  ( .D(wr_data[5]), .E(n2), .CLK(n26), .Q(\mem[0][5] )
         );
  fdef1a3 \mem_reg[0][4]  ( .D(wr_data[4]), .E(n2), .CLK(n26), .Q(\mem[0][4] )
         );
  fdef1a3 \mem_reg[0][3]  ( .D(wr_data[3]), .E(n2), .CLK(n26), .Q(\mem[0][3] )
         );
  fdef1a3 \mem_reg[0][2]  ( .D(wr_data[2]), .E(n2), .CLK(n26), .Q(\mem[0][2] )
         );
  fdef1a3 \mem_reg[0][1]  ( .D(wr_data[1]), .E(n2), .CLK(n26), .Q(\mem[0][1] )
         );
  fdef1a3 \mem_reg[5][7]  ( .D(wr_data[7]), .E(n4), .CLK(n30), .Q(\mem[5][7] )
         );
  fdef1a3 \mem_reg[5][6]  ( .D(wr_data[6]), .E(n4), .CLK(n30), .Q(\mem[5][6] )
         );
  fdef1a3 \mem_reg[5][5]  ( .D(wr_data[5]), .E(n4), .CLK(n30), .Q(\mem[5][5] )
         );
  fdef1a3 \mem_reg[5][4]  ( .D(wr_data[4]), .E(n4), .CLK(n30), .Q(\mem[5][4] )
         );
  fdef1a3 \mem_reg[5][3]  ( .D(wr_data[3]), .E(n4), .CLK(n30), .Q(\mem[5][3] )
         );
  fdef1a3 \mem_reg[5][2]  ( .D(wr_data[2]), .E(n4), .CLK(n30), .Q(\mem[5][2] )
         );
  fdef1a3 \mem_reg[5][1]  ( .D(wr_data[1]), .E(n4), .CLK(n29), .Q(\mem[5][1] )
         );
  fdef1a3 \mem_reg[5][0]  ( .D(wr_data[0]), .E(n4), .CLK(n29), .Q(\mem[5][0] )
         );
  fdef1a3 \mem_reg[1][7]  ( .D(wr_data[7]), .E(n5), .CLK(n27), .Q(\mem[1][7] )
         );
  fdef1a3 \mem_reg[1][6]  ( .D(wr_data[6]), .E(n5), .CLK(n27), .Q(\mem[1][6] )
         );
  fdef1a3 \mem_reg[1][5]  ( .D(wr_data[5]), .E(n5), .CLK(n27), .Q(\mem[1][5] )
         );
  fdef1a3 \mem_reg[1][4]  ( .D(wr_data[4]), .E(n5), .CLK(n27), .Q(\mem[1][4] )
         );
  fdef1a3 \mem_reg[1][3]  ( .D(wr_data[3]), .E(n5), .CLK(n27), .Q(\mem[1][3] )
         );
  fdef1a3 \mem_reg[1][2]  ( .D(wr_data[2]), .E(n5), .CLK(n27), .Q(\mem[1][2] )
         );
  fdef1a3 \mem_reg[1][1]  ( .D(wr_data[1]), .E(n5), .CLK(n26), .Q(\mem[1][1] )
         );
  fdef1a3 \mem_reg[1][0]  ( .D(wr_data[0]), .E(n5), .CLK(n26), .Q(\mem[1][0] )
         );
  fdf3a3 empty_reg ( .D(N53), .CLK(n26), .PRE(n25), .Q(empty) );
  fdf2a3 full_reg ( .D(N66), .CLK(n26), .CLR(n25), .Q(full) );
  fdf2a3 \wr_ptr_reg[2]  ( .D(n84), .CLK(n32), .CLR(n25), .Q(wr_ptr[2]) );
  fdf2a6 \rd_ptr_reg[2]  ( .D(n81), .CLK(n32), .CLR(n25), .Q(N21) );
  fdf2a3 \wr_ptr_reg[0]  ( .D(n86), .CLK(n32), .CLR(n25), .Q(wr_ptr[0]) );
  fdf2a3 \wr_ptr_reg[1]  ( .D(n85), .CLK(n32), .CLR(n25), .Q(wr_ptr[1]) );
  fdf2a15 \rd_ptr_reg[0]  ( .D(n83), .CLK(n32), .CLR(n25), .Q(N19) );
  fdf2a15 \rd_ptr_reg[1]  ( .D(n82), .CLK(n32), .CLR(n25), .Q(N20) );
  and2a6 U3 ( .A(n50), .B(n45), .Y(n4) );
  and2a6 U4 ( .A(n48), .B(n43), .Y(n6) );
  and3a6 U5 ( .A(n42), .B(n44), .C(n50), .Y(n3) );
  and3a6 U6 ( .A(n43), .B(n42), .C(wr_ptr[1]), .Y(n7) );
  and3a6 U7 ( .A(wr_ptr[1]), .B(n42), .C(n50), .Y(n8) );
  and2a6 U8 ( .A(n50), .B(n48), .Y(n1) );
  and2a6 U9 ( .A(n45), .B(n43), .Y(n5) );
  and3a6 U10 ( .A(n42), .B(n44), .C(n43), .Y(n2) );
  and2c3 U11 ( .A(n37), .B(wr_ptr[2]), .Y(n43) );
  mx2d6 U12 ( .D0(n23), .D1(n24), .S(N21), .Y(rd_data[7]) );
  mx2d6 U13 ( .D0(n11), .D1(n12), .S(N21), .Y(rd_data[1]) );
  mx2d6 U14 ( .D0(n13), .D1(n14), .S(N21), .Y(rd_data[2]) );
  mx2d6 U15 ( .D0(n15), .D1(n16), .S(N21), .Y(rd_data[3]) );
  mx2d6 U16 ( .D0(n17), .D1(n18), .S(N21), .Y(rd_data[4]) );
  mx2d6 U17 ( .D0(n19), .D1(n20), .S(N21), .Y(rd_data[5]) );
  mx2d6 U18 ( .D0(n21), .D1(n22), .S(N21), .Y(rd_data[6]) );
  mx2d6 U19 ( .D0(n9), .D1(n10), .S(N21), .Y(rd_data[0]) );
  ao4f2 U20 ( .A(n51), .B(n59), .C(N19), .D(n57), .Y(n83) );
  xor2b1 U21 ( .A(N20), .B(wr_ptr[1]), .Y(n79) );
  ao4b1 U22 ( .C(n58), .D(N20), .B(n56), .A(N20), .Y(n82) );
  inv1a1 U23 ( .A(n70), .Y(n40) );
  ao1f2 U24 ( .A(N19), .B(n42), .C(n78), .Y(n70) );
  inv1a1 U25 ( .A(full), .Y(n39) );
  inv1a1 U26 ( .A(empty), .Y(n49) );
  inv1a3 U27 ( .A(wr_en), .Y(n37) );
  inv1a3 U28 ( .A(n63), .Y(n38) );
  inv1a1 U29 ( .A(n71), .Y(n41) );
  clk1a6 U30 ( .A(n35), .Y(n27) );
  clk1a6 U31 ( .A(n35), .Y(n28) );
  clk1a6 U32 ( .A(n34), .Y(n29) );
  clk1a6 U33 ( .A(n34), .Y(n30) );
  clk1a6 U35 ( .A(n33), .Y(n31) );
  clk1a3 U36 ( .A(n33), .Y(n32) );
  or3d2 U38 ( .A(n53), .B(n49), .C(rd_en), .Y(n57) );
  and2c3 U39 ( .A(n46), .B(n37), .Y(n50) );
  inv1a1 U40 ( .A(rd_en), .Y(n47) );
  and3d1 U41 ( .A(n37), .B(rd_en), .C(n41), .Y(n68) );
  and2c3 U42 ( .A(n44), .B(n42), .Y(n48) );
  or3d3 U43 ( .A(n53), .B(n39), .C(wr_en), .Y(n63) );
  and3d2 U44 ( .A(n67), .B(wr_en), .C(n40), .Y(n74) );
  and2c3 U45 ( .A(n51), .B(n57), .Y(n56) );
  or2c1 U46 ( .A(n53), .B(n57), .Y(n59) );
  ao1f2 U47 ( .A(n60), .B(n46), .C(n61), .Y(n84) );
  or3d1 U49 ( .A(n48), .B(n46), .C(n38), .Y(n61) );
  oa1f3 U51 ( .A(n38), .B(n44), .C(n62), .Y(n60) );
  ao1f2 U53 ( .A(n65), .B(n39), .C(n66), .Y(N66) );
  and3c1 U54 ( .C(n67), .A(n69), .B(n47), .Y(n65) );
  or3d1 U55 ( .A(n67), .B(n40), .C(n68), .Y(n66) );
  or3d1 U56 ( .A(n70), .B(n37), .C(n71), .Y(n69) );
  or2c1 U57 ( .A(n53), .B(n63), .Y(n64) );
  ao1f2 U58 ( .A(n72), .B(n49), .C(n73), .Y(N53) );
  and3d2 U59 ( .A(n80), .B(n70), .C(n75), .Y(n72) );
  or3d1 U60 ( .A(n41), .B(rd_en), .C(n74), .Y(n73) );
  or3d1 U61 ( .A(wr_en), .B(n47), .C(n79), .Y(n80) );
  clk1a6 U62 ( .A(n36), .Y(n26) );
  clk1a3 U63 ( .A(clk), .Y(n36) );
  clk1a3 U64 ( .A(clk), .Y(n35) );
  clk1a3 U65 ( .A(clk), .Y(n34) );
  clk1a3 U66 ( .A(clk), .Y(n33) );
  mx4e3 U67 ( .D0(\mem[0][6] ), .D1(\mem[1][6] ), .D2(\mem[2][6] ), .D3(
        \mem[3][6] ), .S0(N19), .S1(N20), .Y(n21) );
  mx4e3 U68 ( .D0(\mem[4][6] ), .D1(\mem[5][6] ), .D2(\mem[6][6] ), .D3(
        \mem[7][6] ), .S0(N19), .S1(N20), .Y(n22) );
  mx4e3 U69 ( .D0(\mem[0][5] ), .D1(\mem[1][5] ), .D2(\mem[2][5] ), .D3(
        \mem[3][5] ), .S0(N19), .S1(N20), .Y(n19) );
  mx4e3 U71 ( .D0(\mem[4][5] ), .D1(\mem[5][5] ), .D2(\mem[6][5] ), .D3(
        \mem[7][5] ), .S0(N19), .S1(N20), .Y(n20) );
  mx4e3 U72 ( .D0(\mem[0][4] ), .D1(\mem[1][4] ), .D2(\mem[2][4] ), .D3(
        \mem[3][4] ), .S0(N19), .S1(N20), .Y(n17) );
  mx4e3 U73 ( .D0(\mem[4][4] ), .D1(\mem[5][4] ), .D2(\mem[6][4] ), .D3(
        \mem[7][4] ), .S0(N19), .S1(N20), .Y(n18) );
  mx4e3 U74 ( .D0(\mem[0][3] ), .D1(\mem[1][3] ), .D2(\mem[2][3] ), .D3(
        \mem[3][3] ), .S0(N19), .S1(N20), .Y(n15) );
  mx4e3 U75 ( .D0(\mem[4][3] ), .D1(\mem[5][3] ), .D2(\mem[6][3] ), .D3(
        \mem[7][3] ), .S0(N19), .S1(N20), .Y(n16) );
  mx4e3 U76 ( .D0(\mem[0][2] ), .D1(\mem[1][2] ), .D2(\mem[2][2] ), .D3(
        \mem[3][2] ), .S0(N19), .S1(N20), .Y(n13) );
  mx4e3 U77 ( .D0(\mem[4][2] ), .D1(\mem[5][2] ), .D2(\mem[6][2] ), .D3(
        \mem[7][2] ), .S0(N19), .S1(N20), .Y(n14) );
  mx4e3 U78 ( .D0(\mem[0][1] ), .D1(\mem[1][1] ), .D2(\mem[2][1] ), .D3(
        \mem[3][1] ), .S0(N19), .S1(N20), .Y(n11) );
  mx4e3 U79 ( .D0(\mem[4][1] ), .D1(\mem[5][1] ), .D2(\mem[6][1] ), .D3(
        \mem[7][1] ), .S0(N19), .S1(N20), .Y(n12) );
  mx4e3 U80 ( .D0(\mem[0][0] ), .D1(\mem[1][0] ), .D2(\mem[2][0] ), .D3(
        \mem[3][0] ), .S0(N19), .S1(N20), .Y(n9) );
  mx4e3 U81 ( .D0(\mem[4][0] ), .D1(\mem[5][0] ), .D2(\mem[6][0] ), .D3(
        \mem[7][0] ), .S0(N19), .S1(N20), .Y(n10) );
  mx4e3 U82 ( .D0(\mem[0][7] ), .D1(\mem[1][7] ), .D2(\mem[2][7] ), .D3(
        \mem[3][7] ), .S0(N19), .S1(N20), .Y(n23) );
  mx4e3 U83 ( .D0(\mem[4][7] ), .D1(\mem[5][7] ), .D2(\mem[6][7] ), .D3(
        \mem[7][7] ), .S0(N19), .S1(N20), .Y(n24) );
  and2c3 U84 ( .A(wr_ptr[0]), .B(n51), .Y(n77) );
  and2c3 U85 ( .A(n42), .B(wr_ptr[1]), .Y(n45) );
  ao1f2 U86 ( .A(wr_ptr[0]), .B(n63), .C(n64), .Y(n62) );
  ao1f2 U87 ( .A(N19), .B(n57), .C(n59), .Y(n58) );
  inv1a3 U88 ( .A(wr_ptr[1]), .Y(n44) );
  inv1a2 U89 ( .A(N19), .Y(n51) );
  or2c2 U90 ( .A(N19), .B(n42), .Y(n78) );
  inv1a3 U91 ( .A(clr), .Y(n53) );
  inv1a3 U92 ( .A(wr_ptr[2]), .Y(n46) );
  clk1b6 U93 ( .A(wr_ptr[0]), .Y(n42) );
  ao1f2 U94 ( .A(n54), .B(n52), .C(n55), .Y(n81) );
  or3d1 U95 ( .A(n56), .B(n52), .C(N20), .Y(n55) );
  oa1d1 U96 ( .A(n57), .B(N20), .C(n58), .Y(n54) );
  inv1a1 U97 ( .A(N21), .Y(n52) );
  clk1a6 U98 ( .A(reset_n), .Y(n25) );
endmodule


module generic_dpram_aw6_dw8 ( rclk, rrst, rce, oe, raddr, do, wclk, wrst, wce, 
        we, waddr, di );
  input [5:0] raddr;
  output [7:0] do;
  input [5:0] waddr;
  input [7:0] di;
  input rclk, rrst, rce, oe, wclk, wrst, wce, we;
  wire   N17, N18, N19, N20, N21, N22, \mem[63][7] , \mem[63][6] ,
         \mem[63][5] , \mem[63][4] , \mem[63][3] , \mem[63][2] , \mem[63][1] ,
         \mem[63][0] , \mem[62][7] , \mem[62][6] , \mem[62][5] , \mem[62][4] ,
         \mem[62][3] , \mem[62][2] , \mem[62][1] , \mem[62][0] , \mem[61][7] ,
         \mem[61][6] , \mem[61][5] , \mem[61][4] , \mem[61][3] , \mem[61][2] ,
         \mem[61][1] , \mem[61][0] , \mem[60][7] , \mem[60][6] , \mem[60][5] ,
         \mem[60][4] , \mem[60][3] , \mem[60][2] , \mem[60][1] , \mem[60][0] ,
         \mem[59][7] , \mem[59][6] , \mem[59][5] , \mem[59][4] , \mem[59][3] ,
         \mem[59][2] , \mem[59][1] , \mem[59][0] , \mem[58][7] , \mem[58][6] ,
         \mem[58][5] , \mem[58][4] , \mem[58][3] , \mem[58][2] , \mem[58][1] ,
         \mem[58][0] , \mem[57][7] , \mem[57][6] , \mem[57][5] , \mem[57][4] ,
         \mem[57][3] , \mem[57][2] , \mem[57][1] , \mem[57][0] , \mem[56][7] ,
         \mem[56][6] , \mem[56][5] , \mem[56][4] , \mem[56][3] , \mem[56][2] ,
         \mem[56][1] , \mem[56][0] , \mem[55][7] , \mem[55][6] , \mem[55][5] ,
         \mem[55][4] , \mem[55][3] , \mem[55][2] , \mem[55][1] , \mem[55][0] ,
         \mem[54][7] , \mem[54][6] , \mem[54][5] , \mem[54][4] , \mem[54][3] ,
         \mem[54][2] , \mem[54][1] , \mem[54][0] , \mem[53][7] , \mem[53][6] ,
         \mem[53][5] , \mem[53][4] , \mem[53][3] , \mem[53][2] , \mem[53][1] ,
         \mem[53][0] , \mem[52][7] , \mem[52][6] , \mem[52][5] , \mem[52][4] ,
         \mem[52][3] , \mem[52][2] , \mem[52][1] , \mem[52][0] , \mem[51][7] ,
         \mem[51][6] , \mem[51][5] , \mem[51][4] , \mem[51][3] , \mem[51][2] ,
         \mem[51][1] , \mem[51][0] , \mem[50][7] , \mem[50][6] , \mem[50][5] ,
         \mem[50][4] , \mem[50][3] , \mem[50][2] , \mem[50][1] , \mem[50][0] ,
         \mem[49][7] , \mem[49][6] , \mem[49][5] , \mem[49][4] , \mem[49][3] ,
         \mem[49][2] , \mem[49][1] , \mem[49][0] , \mem[48][7] , \mem[48][6] ,
         \mem[48][5] , \mem[48][4] , \mem[48][3] , \mem[48][2] , \mem[48][1] ,
         \mem[48][0] , \mem[47][7] , \mem[47][6] , \mem[47][5] , \mem[47][4] ,
         \mem[47][3] , \mem[47][2] , \mem[47][1] , \mem[47][0] , \mem[46][7] ,
         \mem[46][6] , \mem[46][5] , \mem[46][4] , \mem[46][3] , \mem[46][2] ,
         \mem[46][1] , \mem[46][0] , \mem[45][7] , \mem[45][6] , \mem[45][5] ,
         \mem[45][4] , \mem[45][3] , \mem[45][2] , \mem[45][1] , \mem[45][0] ,
         \mem[44][7] , \mem[44][6] , \mem[44][5] , \mem[44][4] , \mem[44][3] ,
         \mem[44][2] , \mem[44][1] , \mem[44][0] , \mem[43][7] , \mem[43][6] ,
         \mem[43][5] , \mem[43][4] , \mem[43][3] , \mem[43][2] , \mem[43][1] ,
         \mem[43][0] , \mem[42][7] , \mem[42][6] , \mem[42][5] , \mem[42][4] ,
         \mem[42][3] , \mem[42][2] , \mem[42][1] , \mem[42][0] , \mem[41][7] ,
         \mem[41][6] , \mem[41][5] , \mem[41][4] , \mem[41][3] , \mem[41][2] ,
         \mem[41][1] , \mem[41][0] , \mem[40][7] , \mem[40][6] , \mem[40][5] ,
         \mem[40][4] , \mem[40][3] , \mem[40][2] , \mem[40][1] , \mem[40][0] ,
         \mem[39][7] , \mem[39][6] , \mem[39][5] , \mem[39][4] , \mem[39][3] ,
         \mem[39][2] , \mem[39][1] , \mem[39][0] , \mem[38][7] , \mem[38][6] ,
         \mem[38][5] , \mem[38][4] , \mem[38][3] , \mem[38][2] , \mem[38][1] ,
         \mem[38][0] , \mem[37][7] , \mem[37][6] , \mem[37][5] , \mem[37][4] ,
         \mem[37][3] , \mem[37][2] , \mem[37][1] , \mem[37][0] , \mem[36][7] ,
         \mem[36][6] , \mem[36][5] , \mem[36][4] , \mem[36][3] , \mem[36][2] ,
         \mem[36][1] , \mem[36][0] , \mem[35][7] , \mem[35][6] , \mem[35][5] ,
         \mem[35][4] , \mem[35][3] , \mem[35][2] , \mem[35][1] , \mem[35][0] ,
         \mem[34][7] , \mem[34][6] , \mem[34][5] , \mem[34][4] , \mem[34][3] ,
         \mem[34][2] , \mem[34][1] , \mem[34][0] , \mem[33][7] , \mem[33][6] ,
         \mem[33][5] , \mem[33][4] , \mem[33][3] , \mem[33][2] , \mem[33][1] ,
         \mem[33][0] , \mem[32][7] , \mem[32][6] , \mem[32][5] , \mem[32][4] ,
         \mem[32][3] , \mem[32][2] , \mem[32][1] , \mem[32][0] , \mem[31][7] ,
         \mem[31][6] , \mem[31][5] , \mem[31][4] , \mem[31][3] , \mem[31][2] ,
         \mem[31][1] , \mem[31][0] , \mem[30][7] , \mem[30][6] , \mem[30][5] ,
         \mem[30][4] , \mem[30][3] , \mem[30][2] , \mem[30][1] , \mem[30][0] ,
         \mem[29][7] , \mem[29][6] , \mem[29][5] , \mem[29][4] , \mem[29][3] ,
         \mem[29][2] , \mem[29][1] , \mem[29][0] , \mem[28][7] , \mem[28][6] ,
         \mem[28][5] , \mem[28][4] , \mem[28][3] , \mem[28][2] , \mem[28][1] ,
         \mem[28][0] , \mem[27][7] , \mem[27][6] , \mem[27][5] , \mem[27][4] ,
         \mem[27][3] , \mem[27][2] , \mem[27][1] , \mem[27][0] , \mem[26][7] ,
         \mem[26][6] , \mem[26][5] , \mem[26][4] , \mem[26][3] , \mem[26][2] ,
         \mem[26][1] , \mem[26][0] , \mem[25][7] , \mem[25][6] , \mem[25][5] ,
         \mem[25][4] , \mem[25][3] , \mem[25][2] , \mem[25][1] , \mem[25][0] ,
         \mem[24][7] , \mem[24][6] , \mem[24][5] , \mem[24][4] , \mem[24][3] ,
         \mem[24][2] , \mem[24][1] , \mem[24][0] , \mem[23][7] , \mem[23][6] ,
         \mem[23][5] , \mem[23][4] , \mem[23][3] , \mem[23][2] , \mem[23][1] ,
         \mem[23][0] , \mem[22][7] , \mem[22][6] , \mem[22][5] , \mem[22][4] ,
         \mem[22][3] , \mem[22][2] , \mem[22][1] , \mem[22][0] , \mem[21][7] ,
         \mem[21][6] , \mem[21][5] , \mem[21][4] , \mem[21][3] , \mem[21][2] ,
         \mem[21][1] , \mem[21][0] , \mem[20][7] , \mem[20][6] , \mem[20][5] ,
         \mem[20][4] , \mem[20][3] , \mem[20][2] , \mem[20][1] , \mem[20][0] ,
         \mem[19][7] , \mem[19][6] , \mem[19][5] , \mem[19][4] , \mem[19][3] ,
         \mem[19][2] , \mem[19][1] , \mem[19][0] , \mem[18][7] , \mem[18][6] ,
         \mem[18][5] , \mem[18][4] , \mem[18][3] , \mem[18][2] , \mem[18][1] ,
         \mem[18][0] , \mem[17][7] , \mem[17][6] , \mem[17][5] , \mem[17][4] ,
         \mem[17][3] , \mem[17][2] , \mem[17][1] , \mem[17][0] , \mem[16][7] ,
         \mem[16][6] , \mem[16][5] , \mem[16][4] , \mem[16][3] , \mem[16][2] ,
         \mem[16][1] , \mem[16][0] , \mem[15][7] , \mem[15][6] , \mem[15][5] ,
         \mem[15][4] , \mem[15][3] , \mem[15][2] , \mem[15][1] , \mem[15][0] ,
         \mem[14][7] , \mem[14][6] , \mem[14][5] , \mem[14][4] , \mem[14][3] ,
         \mem[14][2] , \mem[14][1] , \mem[14][0] , \mem[13][7] , \mem[13][6] ,
         \mem[13][5] , \mem[13][4] , \mem[13][3] , \mem[13][2] , \mem[13][1] ,
         \mem[13][0] , \mem[12][7] , \mem[12][6] , \mem[12][5] , \mem[12][4] ,
         \mem[12][3] , \mem[12][2] , \mem[12][1] , \mem[12][0] , \mem[11][7] ,
         \mem[11][6] , \mem[11][5] , \mem[11][4] , \mem[11][3] , \mem[11][2] ,
         \mem[11][1] , \mem[11][0] , \mem[10][7] , \mem[10][6] , \mem[10][5] ,
         \mem[10][4] , \mem[10][3] , \mem[10][2] , \mem[10][1] , \mem[10][0] ,
         \mem[9][7] , \mem[9][6] , \mem[9][5] , \mem[9][4] , \mem[9][3] ,
         \mem[9][2] , \mem[9][1] , \mem[9][0] , \mem[8][7] , \mem[8][6] ,
         \mem[8][5] , \mem[8][4] , \mem[8][3] , \mem[8][2] , \mem[8][1] ,
         \mem[8][0] , \mem[7][7] , \mem[7][6] , \mem[7][5] , \mem[7][4] ,
         \mem[7][3] , \mem[7][2] , \mem[7][1] , \mem[7][0] , \mem[6][7] ,
         \mem[6][6] , \mem[6][5] , \mem[6][4] , \mem[6][3] , \mem[6][2] ,
         \mem[6][1] , \mem[6][0] , \mem[5][7] , \mem[5][6] , \mem[5][5] ,
         \mem[5][4] , \mem[5][3] , \mem[5][2] , \mem[5][1] , \mem[5][0] ,
         \mem[4][7] , \mem[4][6] , \mem[4][5] , \mem[4][4] , \mem[4][3] ,
         \mem[4][2] , \mem[4][1] , \mem[4][0] , \mem[3][7] , \mem[3][6] ,
         \mem[3][5] , \mem[3][4] , \mem[3][3] , \mem[3][2] , \mem[3][1] ,
         \mem[3][0] , \mem[2][7] , \mem[2][6] , \mem[2][5] , \mem[2][4] ,
         \mem[2][3] , \mem[2][2] , \mem[2][1] , \mem[2][0] , \mem[1][7] ,
         \mem[1][6] , \mem[1][5] , \mem[1][4] , \mem[1][3] , \mem[1][2] ,
         \mem[1][1] , \mem[1][0] , \mem[0][7] , \mem[0][6] , \mem[0][5] ,
         \mem[0][4] , \mem[0][3] , \mem[0][2] , \mem[0][1] , \mem[0][0] , N24,
         N25, N26, N27, N28, N29, N30, N31, n1, n2, n3, n4, n5, n6, n7, n8, n9,
         n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n25, n26, n27, n28,
         n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42,
         n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56,
         n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
         n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84,
         n85, n86, n87, n88, n89, n10, n11, n22, n23, n24, n90, n91, n92, n93,
         n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
         n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
         n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
         n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
         n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
         n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
         n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
         n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
         n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
         n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
         n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
         n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
         n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
         n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248,
         n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259,
         n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270,
         n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281,
         n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
         n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
         n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
         n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
         n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
         n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347,
         n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358,
         n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369,
         n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, n380,
         n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391,
         n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
         n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
         n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
         n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
         n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
         n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
         n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
         n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
         n480, n481, n482, n483;
  wire   [7:0] do_reg;
  tri   [7:0] do;
  assign N17 = raddr[0];
  assign N18 = raddr[1];
  assign N19 = raddr[2];
  assign N20 = raddr[3];
  assign N21 = raddr[4];
  assign N22 = raddr[5];

  and2c6 U2 ( .A(n1), .B(n2), .Y(n26) );
  and2c6 U3 ( .A(n1), .B(n3), .Y(n27) );
  and2c6 U4 ( .A(n1), .B(n4), .Y(n28) );
  and2c6 U5 ( .A(n1), .B(n5), .Y(n29) );
  and2c6 U6 ( .A(n1), .B(n6), .Y(n30) );
  and2c6 U7 ( .A(n1), .B(n7), .Y(n31) );
  and2c6 U8 ( .A(n1), .B(n8), .Y(n32) );
  and2c6 U9 ( .A(n1), .B(n9), .Y(n33) );
  or3d6 U10 ( .A(n482), .B(n483), .C(n12), .Y(n1) );
  and2c6 U11 ( .A(n2), .B(n13), .Y(n34) );
  and2c6 U12 ( .A(n3), .B(n13), .Y(n35) );
  and2c6 U13 ( .A(n4), .B(n13), .Y(n36) );
  and2c6 U14 ( .A(n5), .B(n13), .Y(n37) );
  and2c6 U15 ( .A(n6), .B(n13), .Y(n38) );
  and2c6 U16 ( .A(n7), .B(n13), .Y(n39) );
  and2c6 U17 ( .A(n8), .B(n13), .Y(n40) );
  and2c6 U18 ( .A(n9), .B(n13), .Y(n41) );
  or3d6 U19 ( .A(n12), .B(n483), .C(waddr[3]), .Y(n13) );
  and2c6 U20 ( .A(n2), .B(n14), .Y(n42) );
  and2c6 U21 ( .A(n3), .B(n14), .Y(n43) );
  and2c6 U22 ( .A(n4), .B(n14), .Y(n44) );
  and2c6 U23 ( .A(n5), .B(n14), .Y(n45) );
  and2c6 U24 ( .A(n6), .B(n14), .Y(n46) );
  and2c6 U25 ( .A(n7), .B(n14), .Y(n47) );
  and2c6 U26 ( .A(n8), .B(n14), .Y(n48) );
  and2c6 U27 ( .A(n9), .B(n14), .Y(n49) );
  or3d6 U28 ( .A(n12), .B(n482), .C(waddr[4]), .Y(n14) );
  and2c6 U29 ( .A(n2), .B(n15), .Y(n50) );
  and2c6 U30 ( .A(n3), .B(n15), .Y(n51) );
  and2c6 U31 ( .A(n4), .B(n15), .Y(n52) );
  and2c6 U32 ( .A(n5), .B(n15), .Y(n53) );
  and2c6 U33 ( .A(n6), .B(n15), .Y(n54) );
  and2c6 U34 ( .A(n7), .B(n15), .Y(n55) );
  and2c6 U35 ( .A(n8), .B(n15), .Y(n56) );
  and2c6 U36 ( .A(n9), .B(n15), .Y(n57) );
  or3d6 U37 ( .A(waddr[3]), .B(n12), .C(waddr[4]), .Y(n15) );
  and2c6 U39 ( .A(n2), .B(n17), .Y(n58) );
  and2c6 U40 ( .A(n3), .B(n17), .Y(n59) );
  and2c6 U41 ( .A(n4), .B(n17), .Y(n60) );
  and2c6 U42 ( .A(n5), .B(n17), .Y(n61) );
  and2c6 U43 ( .A(n6), .B(n17), .Y(n62) );
  and2c6 U44 ( .A(n7), .B(n17), .Y(n63) );
  and2c6 U45 ( .A(n8), .B(n17), .Y(n64) );
  and2c6 U46 ( .A(n9), .B(n17), .Y(n65) );
  or3d6 U47 ( .A(n482), .B(n483), .C(n18), .Y(n17) );
  and2c6 U48 ( .A(n2), .B(n19), .Y(n66) );
  and2c6 U49 ( .A(n3), .B(n19), .Y(n67) );
  and2c6 U50 ( .A(n4), .B(n19), .Y(n68) );
  and2c6 U51 ( .A(n5), .B(n19), .Y(n69) );
  and2c6 U52 ( .A(n6), .B(n19), .Y(n70) );
  and2c6 U53 ( .A(n7), .B(n19), .Y(n71) );
  and2c6 U54 ( .A(n8), .B(n19), .Y(n72) );
  and2c6 U55 ( .A(n9), .B(n19), .Y(n73) );
  or3d6 U56 ( .A(waddr[3]), .B(n483), .C(n18), .Y(n19) );
  and2c6 U58 ( .A(n2), .B(n20), .Y(n74) );
  and2c6 U59 ( .A(n3), .B(n20), .Y(n75) );
  and2c6 U60 ( .A(n4), .B(n20), .Y(n76) );
  and2c6 U61 ( .A(n5), .B(n20), .Y(n77) );
  and2c6 U62 ( .A(n6), .B(n20), .Y(n78) );
  and2c6 U63 ( .A(n7), .B(n20), .Y(n79) );
  and2c6 U64 ( .A(n8), .B(n20), .Y(n80) );
  and2c6 U65 ( .A(n9), .B(n20), .Y(n81) );
  or3d6 U66 ( .A(waddr[4]), .B(n482), .C(n18), .Y(n20) );
  and2c6 U68 ( .A(n2), .B(n21), .Y(n82) );
  or3d6 U69 ( .A(n480), .B(n481), .C(n479), .Y(n2) );
  and2c6 U70 ( .A(n3), .B(n21), .Y(n83) );
  or3d6 U71 ( .A(n480), .B(n481), .C(waddr[0]), .Y(n3) );
  and2c6 U72 ( .A(n4), .B(n21), .Y(n84) );
  or3d6 U73 ( .A(n479), .B(n481), .C(waddr[1]), .Y(n4) );
  and2c6 U74 ( .A(n5), .B(n21), .Y(n85) );
  or3d6 U75 ( .A(waddr[0]), .B(n481), .C(waddr[1]), .Y(n5) );
  and2c6 U77 ( .A(n6), .B(n21), .Y(n86) );
  or3d6 U78 ( .A(n479), .B(n480), .C(waddr[2]), .Y(n6) );
  and2c6 U79 ( .A(n7), .B(n21), .Y(n87) );
  or3d6 U80 ( .A(waddr[0]), .B(n480), .C(waddr[2]), .Y(n7) );
  and2c6 U82 ( .A(n8), .B(n21), .Y(n88) );
  or3d6 U83 ( .A(waddr[1]), .B(n479), .C(waddr[2]), .Y(n8) );
  and2c6 U85 ( .A(n9), .B(n21), .Y(n89) );
  or3d6 U86 ( .A(waddr[4]), .B(waddr[3]), .C(n18), .Y(n21) );
  or3d6 U89 ( .A(waddr[1]), .B(waddr[0]), .C(waddr[2]), .Y(n9) );
  and2a6 U90 ( .A(rce), .B(oe), .Y(n25) );
  fdef1a3 \mem_reg[59][7]  ( .D(n356), .E(n85), .CLK(n368), .Q(\mem[59][7] )
         );
  fdef1a3 \mem_reg[59][6]  ( .D(n347), .E(n85), .CLK(n368), .Q(\mem[59][6] )
         );
  fdef1a3 \mem_reg[59][5]  ( .D(n338), .E(n85), .CLK(n368), .Q(\mem[59][5] )
         );
  fdef1a3 \mem_reg[59][4]  ( .D(n329), .E(n85), .CLK(n368), .Q(\mem[59][4] )
         );
  fdef1a3 \mem_reg[59][3]  ( .D(n320), .E(n85), .CLK(n369), .Q(\mem[59][3] )
         );
  fdef1a3 \mem_reg[59][2]  ( .D(n311), .E(n85), .CLK(n369), .Q(\mem[59][2] )
         );
  fdef1a3 \mem_reg[59][1]  ( .D(n302), .E(n85), .CLK(n369), .Q(\mem[59][1] )
         );
  fdef1a3 \mem_reg[59][0]  ( .D(n293), .E(n85), .CLK(n369), .Q(\mem[59][0] )
         );
  fdef1a3 \mem_reg[55][7]  ( .D(n356), .E(n81), .CLK(n372), .Q(\mem[55][7] )
         );
  fdef1a3 \mem_reg[55][6]  ( .D(n347), .E(n81), .CLK(n372), .Q(\mem[55][6] )
         );
  fdef1a3 \mem_reg[55][5]  ( .D(n338), .E(n81), .CLK(n372), .Q(\mem[55][5] )
         );
  fdef1a3 \mem_reg[55][4]  ( .D(n329), .E(n81), .CLK(n372), .Q(\mem[55][4] )
         );
  fdef1a3 \mem_reg[55][3]  ( .D(n320), .E(n81), .CLK(n372), .Q(\mem[55][3] )
         );
  fdef1a3 \mem_reg[55][2]  ( .D(n311), .E(n81), .CLK(n372), .Q(\mem[55][2] )
         );
  fdef1a3 \mem_reg[55][1]  ( .D(n302), .E(n81), .CLK(n372), .Q(\mem[55][1] )
         );
  fdef1a3 \mem_reg[55][0]  ( .D(n293), .E(n81), .CLK(n372), .Q(\mem[55][0] )
         );
  fdef1a3 \mem_reg[51][7]  ( .D(n357), .E(n77), .CLK(n375), .Q(\mem[51][7] )
         );
  fdef1a3 \mem_reg[51][6]  ( .D(n348), .E(n77), .CLK(n375), .Q(\mem[51][6] )
         );
  fdef1a3 \mem_reg[51][5]  ( .D(n339), .E(n77), .CLK(n375), .Q(\mem[51][5] )
         );
  fdef1a3 \mem_reg[51][4]  ( .D(n330), .E(n77), .CLK(n376), .Q(\mem[51][4] )
         );
  fdef1a3 \mem_reg[51][3]  ( .D(n321), .E(n77), .CLK(n376), .Q(\mem[51][3] )
         );
  fdef1a3 \mem_reg[51][2]  ( .D(n312), .E(n77), .CLK(n376), .Q(\mem[51][2] )
         );
  fdef1a3 \mem_reg[51][1]  ( .D(n303), .E(n77), .CLK(n376), .Q(\mem[51][1] )
         );
  fdef1a3 \mem_reg[51][0]  ( .D(n294), .E(n77), .CLK(n376), .Q(\mem[51][0] )
         );
  fdef1a3 \mem_reg[47][7]  ( .D(n357), .E(n73), .CLK(n379), .Q(\mem[47][7] )
         );
  fdef1a3 \mem_reg[47][6]  ( .D(n348), .E(n73), .CLK(n379), .Q(\mem[47][6] )
         );
  fdef1a3 \mem_reg[47][5]  ( .D(n339), .E(n73), .CLK(n379), .Q(\mem[47][5] )
         );
  fdef1a3 \mem_reg[47][4]  ( .D(n330), .E(n73), .CLK(n379), .Q(\mem[47][4] )
         );
  fdef1a3 \mem_reg[47][3]  ( .D(n321), .E(n73), .CLK(n379), .Q(\mem[47][3] )
         );
  fdef1a3 \mem_reg[47][2]  ( .D(n312), .E(n73), .CLK(n379), .Q(\mem[47][2] )
         );
  fdef1a3 \mem_reg[47][1]  ( .D(n303), .E(n73), .CLK(n379), .Q(\mem[47][1] )
         );
  fdef1a3 \mem_reg[47][0]  ( .D(n294), .E(n73), .CLK(n380), .Q(\mem[47][0] )
         );
  fdef1a3 \mem_reg[43][7]  ( .D(n357), .E(n69), .CLK(n382), .Q(\mem[43][7] )
         );
  fdef1a3 \mem_reg[43][6]  ( .D(n348), .E(n69), .CLK(n382), .Q(\mem[43][6] )
         );
  fdef1a3 \mem_reg[43][5]  ( .D(n339), .E(n69), .CLK(n383), .Q(\mem[43][5] )
         );
  fdef1a3 \mem_reg[43][4]  ( .D(n330), .E(n69), .CLK(n383), .Q(\mem[43][4] )
         );
  fdef1a3 \mem_reg[43][3]  ( .D(n321), .E(n69), .CLK(n383), .Q(\mem[43][3] )
         );
  fdef1a3 \mem_reg[43][2]  ( .D(n312), .E(n69), .CLK(n383), .Q(\mem[43][2] )
         );
  fdef1a3 \mem_reg[43][1]  ( .D(n303), .E(n69), .CLK(n383), .Q(\mem[43][1] )
         );
  fdef1a3 \mem_reg[43][0]  ( .D(n294), .E(n69), .CLK(n383), .Q(\mem[43][0] )
         );
  fdef1a3 \mem_reg[39][7]  ( .D(n358), .E(n65), .CLK(n386), .Q(\mem[39][7] )
         );
  fdef1a3 \mem_reg[39][6]  ( .D(n349), .E(n65), .CLK(n386), .Q(\mem[39][6] )
         );
  fdef1a3 \mem_reg[39][5]  ( .D(n340), .E(n65), .CLK(n386), .Q(\mem[39][5] )
         );
  fdef1a3 \mem_reg[39][4]  ( .D(n331), .E(n65), .CLK(n386), .Q(\mem[39][4] )
         );
  fdef1a3 \mem_reg[39][3]  ( .D(n322), .E(n65), .CLK(n386), .Q(\mem[39][3] )
         );
  fdef1a3 \mem_reg[39][2]  ( .D(n313), .E(n65), .CLK(n386), .Q(\mem[39][2] )
         );
  fdef1a3 \mem_reg[39][1]  ( .D(n304), .E(n65), .CLK(n387), .Q(\mem[39][1] )
         );
  fdef1a3 \mem_reg[39][0]  ( .D(n295), .E(n65), .CLK(n387), .Q(\mem[39][0] )
         );
  fdef1a3 \mem_reg[35][7]  ( .D(n358), .E(n61), .CLK(n389), .Q(\mem[35][7] )
         );
  fdef1a3 \mem_reg[35][6]  ( .D(n349), .E(n61), .CLK(n390), .Q(\mem[35][6] )
         );
  fdef1a3 \mem_reg[35][5]  ( .D(n340), .E(n61), .CLK(n390), .Q(\mem[35][5] )
         );
  fdef1a3 \mem_reg[35][4]  ( .D(n331), .E(n61), .CLK(n390), .Q(\mem[35][4] )
         );
  fdef1a3 \mem_reg[35][3]  ( .D(n322), .E(n61), .CLK(n390), .Q(\mem[35][3] )
         );
  fdef1a3 \mem_reg[35][2]  ( .D(n313), .E(n61), .CLK(n390), .Q(\mem[35][2] )
         );
  fdef1a3 \mem_reg[35][1]  ( .D(n304), .E(n61), .CLK(n390), .Q(\mem[35][1] )
         );
  fdef1a3 \mem_reg[35][0]  ( .D(n295), .E(n61), .CLK(n390), .Q(\mem[35][0] )
         );
  fdef1a3 \mem_reg[31][7]  ( .D(n358), .E(n57), .CLK(n393), .Q(\mem[31][7] )
         );
  fdef1a3 \mem_reg[31][6]  ( .D(n349), .E(n57), .CLK(n393), .Q(\mem[31][6] )
         );
  fdef1a3 \mem_reg[31][5]  ( .D(n340), .E(n57), .CLK(n393), .Q(\mem[31][5] )
         );
  fdef1a3 \mem_reg[31][4]  ( .D(n331), .E(n57), .CLK(n393), .Q(\mem[31][4] )
         );
  fdef1a3 \mem_reg[31][3]  ( .D(n322), .E(n57), .CLK(n393), .Q(\mem[31][3] )
         );
  fdef1a3 \mem_reg[31][2]  ( .D(n313), .E(n57), .CLK(n394), .Q(\mem[31][2] )
         );
  fdef1a3 \mem_reg[31][1]  ( .D(n304), .E(n57), .CLK(n394), .Q(\mem[31][1] )
         );
  fdef1a3 \mem_reg[31][0]  ( .D(n295), .E(n57), .CLK(n394), .Q(\mem[31][0] )
         );
  fdef1a3 \mem_reg[27][7]  ( .D(n359), .E(n53), .CLK(n397), .Q(\mem[27][7] )
         );
  fdef1a3 \mem_reg[27][6]  ( .D(n350), .E(n53), .CLK(n397), .Q(\mem[27][6] )
         );
  fdef1a3 \mem_reg[27][5]  ( .D(n341), .E(n53), .CLK(n397), .Q(\mem[27][5] )
         );
  fdef1a3 \mem_reg[27][4]  ( .D(n332), .E(n53), .CLK(n397), .Q(\mem[27][4] )
         );
  fdef1a3 \mem_reg[27][3]  ( .D(n323), .E(n53), .CLK(n397), .Q(\mem[27][3] )
         );
  fdef1a3 \mem_reg[27][2]  ( .D(n314), .E(n53), .CLK(n397), .Q(\mem[27][2] )
         );
  fdef1a3 \mem_reg[27][1]  ( .D(n305), .E(n53), .CLK(n397), .Q(\mem[27][1] )
         );
  fdef1a3 \mem_reg[27][0]  ( .D(n296), .E(n53), .CLK(n397), .Q(\mem[27][0] )
         );
  fdef1a3 \mem_reg[23][7]  ( .D(n359), .E(n49), .CLK(n400), .Q(\mem[23][7] )
         );
  fdef1a3 \mem_reg[23][6]  ( .D(n350), .E(n49), .CLK(n400), .Q(\mem[23][6] )
         );
  fdef1a3 \mem_reg[23][5]  ( .D(n341), .E(n49), .CLK(n400), .Q(\mem[23][5] )
         );
  fdef1a3 \mem_reg[23][4]  ( .D(n332), .E(n49), .CLK(n400), .Q(\mem[23][4] )
         );
  fdef1a3 \mem_reg[23][3]  ( .D(n323), .E(n49), .CLK(n401), .Q(\mem[23][3] )
         );
  fdef1a3 \mem_reg[23][2]  ( .D(n314), .E(n49), .CLK(n401), .Q(\mem[23][2] )
         );
  fdef1a3 \mem_reg[23][1]  ( .D(n305), .E(n49), .CLK(n401), .Q(\mem[23][1] )
         );
  fdef1a3 \mem_reg[23][0]  ( .D(n296), .E(n49), .CLK(n401), .Q(\mem[23][0] )
         );
  fdef1a3 \mem_reg[19][7]  ( .D(n360), .E(n45), .CLK(n404), .Q(\mem[19][7] )
         );
  fdef1a3 \mem_reg[19][6]  ( .D(n351), .E(n45), .CLK(n404), .Q(\mem[19][6] )
         );
  fdef1a3 \mem_reg[19][5]  ( .D(n342), .E(n45), .CLK(n404), .Q(\mem[19][5] )
         );
  fdef1a3 \mem_reg[19][4]  ( .D(n333), .E(n45), .CLK(n404), .Q(\mem[19][4] )
         );
  fdef1a3 \mem_reg[19][3]  ( .D(n324), .E(n45), .CLK(n404), .Q(\mem[19][3] )
         );
  fdef1a3 \mem_reg[19][2]  ( .D(n315), .E(n45), .CLK(n404), .Q(\mem[19][2] )
         );
  fdef1a3 \mem_reg[19][1]  ( .D(n306), .E(n45), .CLK(n404), .Q(\mem[19][1] )
         );
  fdef1a3 \mem_reg[19][0]  ( .D(n297), .E(n45), .CLK(n404), .Q(\mem[19][0] )
         );
  fdef1a3 \mem_reg[15][7]  ( .D(n360), .E(n41), .CLK(n407), .Q(\mem[15][7] )
         );
  fdef1a3 \mem_reg[15][6]  ( .D(n351), .E(n41), .CLK(n407), .Q(\mem[15][6] )
         );
  fdef1a3 \mem_reg[15][5]  ( .D(n342), .E(n41), .CLK(n407), .Q(\mem[15][5] )
         );
  fdef1a3 \mem_reg[15][4]  ( .D(n333), .E(n41), .CLK(n408), .Q(\mem[15][4] )
         );
  fdef1a3 \mem_reg[15][3]  ( .D(n324), .E(n41), .CLK(n408), .Q(\mem[15][3] )
         );
  fdef1a3 \mem_reg[15][2]  ( .D(n315), .E(n41), .CLK(n408), .Q(\mem[15][2] )
         );
  fdef1a3 \mem_reg[15][1]  ( .D(n306), .E(n41), .CLK(n408), .Q(\mem[15][1] )
         );
  fdef1a3 \mem_reg[15][0]  ( .D(n297), .E(n41), .CLK(n408), .Q(\mem[15][0] )
         );
  fdef1a3 \mem_reg[11][7]  ( .D(n360), .E(n37), .CLK(n411), .Q(\mem[11][7] )
         );
  fdef1a3 \mem_reg[11][6]  ( .D(n351), .E(n37), .CLK(n411), .Q(\mem[11][6] )
         );
  fdef1a3 \mem_reg[11][5]  ( .D(n342), .E(n37), .CLK(n411), .Q(\mem[11][5] )
         );
  fdef1a3 \mem_reg[11][4]  ( .D(n333), .E(n37), .CLK(n411), .Q(\mem[11][4] )
         );
  fdef1a3 \mem_reg[11][3]  ( .D(n324), .E(n37), .CLK(n411), .Q(\mem[11][3] )
         );
  fdef1a3 \mem_reg[11][2]  ( .D(n315), .E(n37), .CLK(n411), .Q(\mem[11][2] )
         );
  fdef1a3 \mem_reg[11][1]  ( .D(n306), .E(n37), .CLK(n411), .Q(\mem[11][1] )
         );
  fdef1a3 \mem_reg[11][0]  ( .D(n297), .E(n37), .CLK(n412), .Q(\mem[11][0] )
         );
  fdef1a3 \mem_reg[7][7]  ( .D(n361), .E(n33), .CLK(n414), .Q(\mem[7][7] ) );
  fdef1a3 \mem_reg[7][6]  ( .D(n352), .E(n33), .CLK(n414), .Q(\mem[7][6] ) );
  fdef1a3 \mem_reg[7][5]  ( .D(n343), .E(n33), .CLK(n415), .Q(\mem[7][5] ) );
  fdef1a3 \mem_reg[7][4]  ( .D(n334), .E(n33), .CLK(n415), .Q(\mem[7][4] ) );
  fdef1a3 \mem_reg[7][3]  ( .D(n325), .E(n33), .CLK(n415), .Q(\mem[7][3] ) );
  fdef1a3 \mem_reg[7][2]  ( .D(n316), .E(n33), .CLK(n415), .Q(\mem[7][2] ) );
  fdef1a3 \mem_reg[7][1]  ( .D(n307), .E(n33), .CLK(n415), .Q(\mem[7][1] ) );
  fdef1a3 \mem_reg[7][0]  ( .D(n298), .E(n33), .CLK(n415), .Q(\mem[7][0] ) );
  fdef1a3 \mem_reg[3][7]  ( .D(n361), .E(n29), .CLK(n418), .Q(\mem[3][7] ) );
  fdef1a3 \mem_reg[3][6]  ( .D(n352), .E(n29), .CLK(n418), .Q(\mem[3][6] ) );
  fdef1a3 \mem_reg[3][5]  ( .D(n343), .E(n29), .CLK(n418), .Q(\mem[3][5] ) );
  fdef1a3 \mem_reg[3][4]  ( .D(n334), .E(n29), .CLK(n418), .Q(\mem[3][4] ) );
  fdef1a3 \mem_reg[3][3]  ( .D(n325), .E(n29), .CLK(n418), .Q(\mem[3][3] ) );
  fdef1a3 \mem_reg[3][2]  ( .D(n316), .E(n29), .CLK(n418), .Q(\mem[3][2] ) );
  fdef1a3 \mem_reg[3][1]  ( .D(n307), .E(n29), .CLK(n419), .Q(\mem[3][1] ) );
  fdef1a3 \mem_reg[3][0]  ( .D(n298), .E(n29), .CLK(n419), .Q(\mem[3][0] ) );
  fdef1a3 \mem_reg[63][7]  ( .D(n356), .E(n89), .CLK(n365), .Q(\mem[63][7] )
         );
  fdef1a3 \mem_reg[63][6]  ( .D(n347), .E(n89), .CLK(n365), .Q(\mem[63][6] )
         );
  fdef1a3 \mem_reg[63][5]  ( .D(n338), .E(n89), .CLK(n365), .Q(\mem[63][5] )
         );
  fdef1a3 \mem_reg[63][4]  ( .D(n329), .E(n89), .CLK(n365), .Q(\mem[63][4] )
         );
  fdef1a3 \mem_reg[63][3]  ( .D(n320), .E(n89), .CLK(n365), .Q(\mem[63][3] )
         );
  fdef1a3 \mem_reg[63][2]  ( .D(n311), .E(n89), .CLK(n365), .Q(\mem[63][2] )
         );
  fdef1a3 \mem_reg[63][1]  ( .D(n302), .E(n89), .CLK(n365), .Q(\mem[63][1] )
         );
  fdef1a3 \mem_reg[63][0]  ( .D(n293), .E(n89), .CLK(n365), .Q(\mem[63][0] )
         );
  fdef1a3 \mem_reg[0][7]  ( .D(n361), .E(n26), .CLK(n421), .Q(\mem[0][7] ) );
  fdef1a3 \mem_reg[0][6]  ( .D(n352), .E(n26), .CLK(n421), .Q(\mem[0][6] ) );
  fdef1a3 \mem_reg[0][5]  ( .D(n343), .E(n26), .CLK(n421), .Q(\mem[0][5] ) );
  fdef1a3 \mem_reg[0][4]  ( .D(n334), .E(n26), .CLK(n421), .Q(\mem[0][4] ) );
  fdef1a3 \mem_reg[0][3]  ( .D(n325), .E(n26), .CLK(n421), .Q(\mem[0][3] ) );
  fdef1a3 \mem_reg[0][2]  ( .D(n316), .E(n26), .CLK(n421), .Q(\mem[0][2] ) );
  fdef1a3 \mem_reg[0][1]  ( .D(n307), .E(n26), .CLK(n421), .Q(\mem[0][1] ) );
  fdef1a3 \mem_reg[0][0]  ( .D(n298), .E(n26), .CLK(n421), .Q(\mem[0][0] ) );
  fdef1a3 \mem_reg[62][6]  ( .D(n347), .E(n88), .CLK(n366), .Q(\mem[62][6] )
         );
  fdef1a3 \mem_reg[62][5]  ( .D(n338), .E(n88), .CLK(n366), .Q(\mem[62][5] )
         );
  fdef1a3 \mem_reg[62][4]  ( .D(n329), .E(n88), .CLK(n366), .Q(\mem[62][4] )
         );
  fdef1a3 \mem_reg[62][3]  ( .D(n320), .E(n88), .CLK(n366), .Q(\mem[62][3] )
         );
  fdef1a3 \mem_reg[62][2]  ( .D(n311), .E(n88), .CLK(n366), .Q(\mem[62][2] )
         );
  fdef1a3 \mem_reg[62][1]  ( .D(n302), .E(n88), .CLK(n366), .Q(\mem[62][1] )
         );
  fdef1a3 \mem_reg[62][0]  ( .D(n293), .E(n88), .CLK(n366), .Q(\mem[62][0] )
         );
  fdef1a3 \mem_reg[60][7]  ( .D(n356), .E(n86), .CLK(n367), .Q(\mem[60][7] )
         );
  fdef1a3 \mem_reg[60][6]  ( .D(n347), .E(n86), .CLK(n367), .Q(\mem[60][6] )
         );
  fdef1a3 \mem_reg[60][5]  ( .D(n338), .E(n86), .CLK(n367), .Q(\mem[60][5] )
         );
  fdef1a3 \mem_reg[60][4]  ( .D(n329), .E(n86), .CLK(n368), .Q(\mem[60][4] )
         );
  fdef1a3 \mem_reg[60][3]  ( .D(n320), .E(n86), .CLK(n368), .Q(\mem[60][3] )
         );
  fdef1a3 \mem_reg[60][2]  ( .D(n311), .E(n86), .CLK(n368), .Q(\mem[60][2] )
         );
  fdef1a3 \mem_reg[60][1]  ( .D(n302), .E(n86), .CLK(n368), .Q(\mem[60][1] )
         );
  fdef1a3 \mem_reg[60][0]  ( .D(n293), .E(n86), .CLK(n368), .Q(\mem[60][0] )
         );
  fdef1a3 \mem_reg[58][7]  ( .D(n356), .E(n84), .CLK(n369), .Q(\mem[58][7] )
         );
  fdef1a3 \mem_reg[58][6]  ( .D(n347), .E(n84), .CLK(n369), .Q(\mem[58][6] )
         );
  fdef1a3 \mem_reg[58][5]  ( .D(n338), .E(n84), .CLK(n369), .Q(\mem[58][5] )
         );
  fdef1a3 \mem_reg[58][4]  ( .D(n329), .E(n84), .CLK(n369), .Q(\mem[58][4] )
         );
  fdef1a3 \mem_reg[58][3]  ( .D(n320), .E(n84), .CLK(n369), .Q(\mem[58][3] )
         );
  fdef1a3 \mem_reg[58][2]  ( .D(n311), .E(n84), .CLK(n370), .Q(\mem[58][2] )
         );
  fdef1a3 \mem_reg[58][1]  ( .D(n302), .E(n84), .CLK(n370), .Q(\mem[58][1] )
         );
  fdef1a3 \mem_reg[58][0]  ( .D(n293), .E(n84), .CLK(n370), .Q(\mem[58][0] )
         );
  fdef1a3 \mem_reg[56][7]  ( .D(n356), .E(n82), .CLK(n371), .Q(\mem[56][7] )
         );
  fdef1a3 \mem_reg[56][6]  ( .D(n347), .E(n82), .CLK(n371), .Q(\mem[56][6] )
         );
  fdef1a3 \mem_reg[56][5]  ( .D(n338), .E(n82), .CLK(n371), .Q(\mem[56][5] )
         );
  fdef1a3 \mem_reg[56][4]  ( .D(n329), .E(n82), .CLK(n371), .Q(\mem[56][4] )
         );
  fdef1a3 \mem_reg[56][3]  ( .D(n320), .E(n82), .CLK(n371), .Q(\mem[56][3] )
         );
  fdef1a3 \mem_reg[56][2]  ( .D(n311), .E(n82), .CLK(n371), .Q(\mem[56][2] )
         );
  fdef1a3 \mem_reg[56][1]  ( .D(n302), .E(n82), .CLK(n371), .Q(\mem[56][1] )
         );
  fdef1a3 \mem_reg[56][0]  ( .D(n293), .E(n82), .CLK(n372), .Q(\mem[56][0] )
         );
  fdef1a3 \mem_reg[54][7]  ( .D(n356), .E(n80), .CLK(n373), .Q(\mem[54][7] )
         );
  fdef1a3 \mem_reg[54][6]  ( .D(n347), .E(n80), .CLK(n373), .Q(\mem[54][6] )
         );
  fdef1a3 \mem_reg[54][5]  ( .D(n338), .E(n80), .CLK(n373), .Q(\mem[54][5] )
         );
  fdef1a3 \mem_reg[54][4]  ( .D(n329), .E(n80), .CLK(n373), .Q(\mem[54][4] )
         );
  fdef1a3 \mem_reg[54][3]  ( .D(n320), .E(n80), .CLK(n373), .Q(\mem[54][3] )
         );
  fdef1a3 \mem_reg[54][2]  ( .D(n311), .E(n80), .CLK(n373), .Q(\mem[54][2] )
         );
  fdef1a3 \mem_reg[54][1]  ( .D(n302), .E(n80), .CLK(n373), .Q(\mem[54][1] )
         );
  fdef1a3 \mem_reg[54][0]  ( .D(n293), .E(n80), .CLK(n373), .Q(\mem[54][0] )
         );
  fdef1a3 \mem_reg[52][7]  ( .D(n357), .E(n78), .CLK(n374), .Q(\mem[52][7] )
         );
  fdef1a3 \mem_reg[52][6]  ( .D(n348), .E(n78), .CLK(n374), .Q(\mem[52][6] )
         );
  fdef1a3 \mem_reg[52][5]  ( .D(n339), .E(n78), .CLK(n375), .Q(\mem[52][5] )
         );
  fdef1a3 \mem_reg[52][4]  ( .D(n330), .E(n78), .CLK(n375), .Q(\mem[52][4] )
         );
  fdef1a3 \mem_reg[52][3]  ( .D(n321), .E(n78), .CLK(n375), .Q(\mem[52][3] )
         );
  fdef1a3 \mem_reg[52][2]  ( .D(n312), .E(n78), .CLK(n375), .Q(\mem[52][2] )
         );
  fdef1a3 \mem_reg[52][1]  ( .D(n303), .E(n78), .CLK(n375), .Q(\mem[52][1] )
         );
  fdef1a3 \mem_reg[52][0]  ( .D(n294), .E(n78), .CLK(n375), .Q(\mem[52][0] )
         );
  fdef1a3 \mem_reg[50][7]  ( .D(n357), .E(n76), .CLK(n376), .Q(\mem[50][7] )
         );
  fdef1a3 \mem_reg[50][6]  ( .D(n348), .E(n76), .CLK(n376), .Q(\mem[50][6] )
         );
  fdef1a3 \mem_reg[50][5]  ( .D(n339), .E(n76), .CLK(n376), .Q(\mem[50][5] )
         );
  fdef1a3 \mem_reg[50][4]  ( .D(n330), .E(n76), .CLK(n376), .Q(\mem[50][4] )
         );
  fdef1a3 \mem_reg[50][3]  ( .D(n321), .E(n76), .CLK(n377), .Q(\mem[50][3] )
         );
  fdef1a3 \mem_reg[50][2]  ( .D(n312), .E(n76), .CLK(n377), .Q(\mem[50][2] )
         );
  fdef1a3 \mem_reg[50][1]  ( .D(n303), .E(n76), .CLK(n377), .Q(\mem[50][1] )
         );
  fdef1a3 \mem_reg[50][0]  ( .D(n294), .E(n76), .CLK(n377), .Q(\mem[50][0] )
         );
  fdef1a3 \mem_reg[48][7]  ( .D(n357), .E(n74), .CLK(n378), .Q(\mem[48][7] )
         );
  fdef1a3 \mem_reg[48][6]  ( .D(n348), .E(n74), .CLK(n378), .Q(\mem[48][6] )
         );
  fdef1a3 \mem_reg[48][5]  ( .D(n339), .E(n74), .CLK(n378), .Q(\mem[48][5] )
         );
  fdef1a3 \mem_reg[48][4]  ( .D(n330), .E(n74), .CLK(n378), .Q(\mem[48][4] )
         );
  fdef1a3 \mem_reg[48][3]  ( .D(n321), .E(n74), .CLK(n378), .Q(\mem[48][3] )
         );
  fdef1a3 \mem_reg[48][2]  ( .D(n312), .E(n74), .CLK(n378), .Q(\mem[48][2] )
         );
  fdef1a3 \mem_reg[48][1]  ( .D(n303), .E(n74), .CLK(n379), .Q(\mem[48][1] )
         );
  fdef1a3 \mem_reg[48][0]  ( .D(n294), .E(n74), .CLK(n379), .Q(\mem[48][0] )
         );
  fdef1a3 \mem_reg[46][7]  ( .D(n357), .E(n72), .CLK(n380), .Q(\mem[46][7] )
         );
  fdef1a3 \mem_reg[46][6]  ( .D(n348), .E(n72), .CLK(n380), .Q(\mem[46][6] )
         );
  fdef1a3 \mem_reg[46][5]  ( .D(n339), .E(n72), .CLK(n380), .Q(\mem[46][5] )
         );
  fdef1a3 \mem_reg[46][4]  ( .D(n330), .E(n72), .CLK(n380), .Q(\mem[46][4] )
         );
  fdef1a3 \mem_reg[46][3]  ( .D(n321), .E(n72), .CLK(n380), .Q(\mem[46][3] )
         );
  fdef1a3 \mem_reg[46][2]  ( .D(n312), .E(n72), .CLK(n380), .Q(\mem[46][2] )
         );
  fdef1a3 \mem_reg[46][1]  ( .D(n303), .E(n72), .CLK(n380), .Q(\mem[46][1] )
         );
  fdef1a3 \mem_reg[46][0]  ( .D(n294), .E(n72), .CLK(n380), .Q(\mem[46][0] )
         );
  fdef1a3 \mem_reg[44][7]  ( .D(n357), .E(n70), .CLK(n381), .Q(\mem[44][7] )
         );
  fdef1a3 \mem_reg[44][6]  ( .D(n348), .E(n70), .CLK(n382), .Q(\mem[44][6] )
         );
  fdef1a3 \mem_reg[44][5]  ( .D(n339), .E(n70), .CLK(n382), .Q(\mem[44][5] )
         );
  fdef1a3 \mem_reg[44][4]  ( .D(n330), .E(n70), .CLK(n382), .Q(\mem[44][4] )
         );
  fdef1a3 \mem_reg[44][3]  ( .D(n321), .E(n70), .CLK(n382), .Q(\mem[44][3] )
         );
  fdef1a3 \mem_reg[44][2]  ( .D(n312), .E(n70), .CLK(n382), .Q(\mem[44][2] )
         );
  fdef1a3 \mem_reg[44][1]  ( .D(n303), .E(n70), .CLK(n382), .Q(\mem[44][1] )
         );
  fdef1a3 \mem_reg[44][0]  ( .D(n294), .E(n70), .CLK(n382), .Q(\mem[44][0] )
         );
  fdef1a3 \mem_reg[42][7]  ( .D(n357), .E(n68), .CLK(n383), .Q(\mem[42][7] )
         );
  fdef1a3 \mem_reg[42][6]  ( .D(n348), .E(n68), .CLK(n383), .Q(\mem[42][6] )
         );
  fdef1a3 \mem_reg[42][5]  ( .D(n339), .E(n68), .CLK(n383), .Q(\mem[42][5] )
         );
  fdef1a3 \mem_reg[42][4]  ( .D(n330), .E(n68), .CLK(n384), .Q(\mem[42][4] )
         );
  fdef1a3 \mem_reg[42][3]  ( .D(n321), .E(n68), .CLK(n384), .Q(\mem[42][3] )
         );
  fdef1a3 \mem_reg[42][2]  ( .D(n312), .E(n68), .CLK(n384), .Q(\mem[42][2] )
         );
  fdef1a3 \mem_reg[42][1]  ( .D(n303), .E(n68), .CLK(n384), .Q(\mem[42][1] )
         );
  fdef1a3 \mem_reg[42][0]  ( .D(n294), .E(n68), .CLK(n384), .Q(\mem[42][0] )
         );
  fdef1a3 \mem_reg[40][7]  ( .D(n358), .E(n66), .CLK(n385), .Q(\mem[40][7] )
         );
  fdef1a3 \mem_reg[40][6]  ( .D(n349), .E(n66), .CLK(n385), .Q(\mem[40][6] )
         );
  fdef1a3 \mem_reg[40][5]  ( .D(n340), .E(n66), .CLK(n385), .Q(\mem[40][5] )
         );
  fdef1a3 \mem_reg[40][4]  ( .D(n331), .E(n66), .CLK(n385), .Q(\mem[40][4] )
         );
  fdef1a3 \mem_reg[40][3]  ( .D(n322), .E(n66), .CLK(n385), .Q(\mem[40][3] )
         );
  fdef1a3 \mem_reg[40][2]  ( .D(n313), .E(n66), .CLK(n386), .Q(\mem[40][2] )
         );
  fdef1a3 \mem_reg[40][1]  ( .D(n304), .E(n66), .CLK(n386), .Q(\mem[40][1] )
         );
  fdef1a3 \mem_reg[40][0]  ( .D(n295), .E(n66), .CLK(n386), .Q(\mem[40][0] )
         );
  fdef1a3 \mem_reg[38][7]  ( .D(n358), .E(n64), .CLK(n387), .Q(\mem[38][7] )
         );
  fdef1a3 \mem_reg[38][6]  ( .D(n349), .E(n64), .CLK(n387), .Q(\mem[38][6] )
         );
  fdef1a3 \mem_reg[38][5]  ( .D(n340), .E(n64), .CLK(n387), .Q(\mem[38][5] )
         );
  fdef1a3 \mem_reg[38][4]  ( .D(n331), .E(n64), .CLK(n387), .Q(\mem[38][4] )
         );
  fdef1a3 \mem_reg[38][3]  ( .D(n322), .E(n64), .CLK(n387), .Q(\mem[38][3] )
         );
  fdef1a3 \mem_reg[38][2]  ( .D(n313), .E(n64), .CLK(n387), .Q(\mem[38][2] )
         );
  fdef1a3 \mem_reg[38][1]  ( .D(n304), .E(n64), .CLK(n387), .Q(\mem[38][1] )
         );
  fdef1a3 \mem_reg[38][0]  ( .D(n295), .E(n64), .CLK(n388), .Q(\mem[38][0] )
         );
  fdef1a3 \mem_reg[36][7]  ( .D(n358), .E(n62), .CLK(n389), .Q(\mem[36][7] )
         );
  fdef1a3 \mem_reg[36][6]  ( .D(n349), .E(n62), .CLK(n389), .Q(\mem[36][6] )
         );
  fdef1a3 \mem_reg[36][5]  ( .D(n340), .E(n62), .CLK(n389), .Q(\mem[36][5] )
         );
  fdef1a3 \mem_reg[36][4]  ( .D(n331), .E(n62), .CLK(n389), .Q(\mem[36][4] )
         );
  fdef1a3 \mem_reg[36][3]  ( .D(n322), .E(n62), .CLK(n389), .Q(\mem[36][3] )
         );
  fdef1a3 \mem_reg[36][2]  ( .D(n313), .E(n62), .CLK(n389), .Q(\mem[36][2] )
         );
  fdef1a3 \mem_reg[36][1]  ( .D(n304), .E(n62), .CLK(n389), .Q(\mem[36][1] )
         );
  fdef1a3 \mem_reg[36][0]  ( .D(n295), .E(n62), .CLK(n389), .Q(\mem[36][0] )
         );
  fdef1a3 \mem_reg[34][7]  ( .D(n358), .E(n60), .CLK(n390), .Q(\mem[34][7] )
         );
  fdef1a3 \mem_reg[34][6]  ( .D(n349), .E(n60), .CLK(n390), .Q(\mem[34][6] )
         );
  fdef1a3 \mem_reg[34][5]  ( .D(n340), .E(n60), .CLK(n391), .Q(\mem[34][5] )
         );
  fdef1a3 \mem_reg[34][4]  ( .D(n331), .E(n60), .CLK(n391), .Q(\mem[34][4] )
         );
  fdef1a3 \mem_reg[34][3]  ( .D(n322), .E(n60), .CLK(n391), .Q(\mem[34][3] )
         );
  fdef1a3 \mem_reg[34][2]  ( .D(n313), .E(n60), .CLK(n391), .Q(\mem[34][2] )
         );
  fdef1a3 \mem_reg[34][1]  ( .D(n304), .E(n60), .CLK(n391), .Q(\mem[34][1] )
         );
  fdef1a3 \mem_reg[34][0]  ( .D(n295), .E(n60), .CLK(n391), .Q(\mem[34][0] )
         );
  fdef1a3 \mem_reg[32][7]  ( .D(n358), .E(n58), .CLK(n392), .Q(\mem[32][7] )
         );
  fdef1a3 \mem_reg[32][6]  ( .D(n349), .E(n58), .CLK(n392), .Q(\mem[32][6] )
         );
  fdef1a3 \mem_reg[32][5]  ( .D(n340), .E(n58), .CLK(n392), .Q(\mem[32][5] )
         );
  fdef1a3 \mem_reg[32][4]  ( .D(n331), .E(n58), .CLK(n392), .Q(\mem[32][4] )
         );
  fdef1a3 \mem_reg[32][3]  ( .D(n322), .E(n58), .CLK(n393), .Q(\mem[32][3] )
         );
  fdef1a3 \mem_reg[32][2]  ( .D(n313), .E(n58), .CLK(n393), .Q(\mem[32][2] )
         );
  fdef1a3 \mem_reg[32][1]  ( .D(n304), .E(n58), .CLK(n393), .Q(\mem[32][1] )
         );
  fdef1a3 \mem_reg[32][0]  ( .D(n295), .E(n58), .CLK(n393), .Q(\mem[32][0] )
         );
  fdef1a3 \mem_reg[30][7]  ( .D(n359), .E(n56), .CLK(n394), .Q(\mem[30][7] )
         );
  fdef1a3 \mem_reg[30][6]  ( .D(n350), .E(n56), .CLK(n394), .Q(\mem[30][6] )
         );
  fdef1a3 \mem_reg[30][5]  ( .D(n341), .E(n56), .CLK(n394), .Q(\mem[30][5] )
         );
  fdef1a3 \mem_reg[30][4]  ( .D(n332), .E(n56), .CLK(n394), .Q(\mem[30][4] )
         );
  fdef1a3 \mem_reg[30][3]  ( .D(n323), .E(n56), .CLK(n394), .Q(\mem[30][3] )
         );
  fdef1a3 \mem_reg[30][2]  ( .D(n314), .E(n56), .CLK(n394), .Q(\mem[30][2] )
         );
  fdef1a3 \mem_reg[30][1]  ( .D(n305), .E(n56), .CLK(n395), .Q(\mem[30][1] )
         );
  fdef1a3 \mem_reg[30][0]  ( .D(n296), .E(n56), .CLK(n395), .Q(\mem[30][0] )
         );
  fdef1a3 \mem_reg[28][7]  ( .D(n359), .E(n54), .CLK(n396), .Q(\mem[28][7] )
         );
  fdef1a3 \mem_reg[28][6]  ( .D(n350), .E(n54), .CLK(n396), .Q(\mem[28][6] )
         );
  fdef1a3 \mem_reg[28][5]  ( .D(n341), .E(n54), .CLK(n396), .Q(\mem[28][5] )
         );
  fdef1a3 \mem_reg[28][4]  ( .D(n332), .E(n54), .CLK(n396), .Q(\mem[28][4] )
         );
  fdef1a3 \mem_reg[28][3]  ( .D(n323), .E(n54), .CLK(n396), .Q(\mem[28][3] )
         );
  fdef1a3 \mem_reg[28][2]  ( .D(n314), .E(n54), .CLK(n396), .Q(\mem[28][2] )
         );
  fdef1a3 \mem_reg[28][1]  ( .D(n305), .E(n54), .CLK(n396), .Q(\mem[28][1] )
         );
  fdef1a3 \mem_reg[28][0]  ( .D(n296), .E(n54), .CLK(n396), .Q(\mem[28][0] )
         );
  fdef1a3 \mem_reg[26][7]  ( .D(n359), .E(n52), .CLK(n397), .Q(\mem[26][7] )
         );
  fdef1a3 \mem_reg[26][6]  ( .D(n350), .E(n52), .CLK(n398), .Q(\mem[26][6] )
         );
  fdef1a3 \mem_reg[26][5]  ( .D(n341), .E(n52), .CLK(n398), .Q(\mem[26][5] )
         );
  fdef1a3 \mem_reg[26][4]  ( .D(n332), .E(n52), .CLK(n398), .Q(\mem[26][4] )
         );
  fdef1a3 \mem_reg[26][3]  ( .D(n323), .E(n52), .CLK(n398), .Q(\mem[26][3] )
         );
  fdef1a3 \mem_reg[26][2]  ( .D(n314), .E(n52), .CLK(n398), .Q(\mem[26][2] )
         );
  fdef1a3 \mem_reg[26][1]  ( .D(n305), .E(n52), .CLK(n398), .Q(\mem[26][1] )
         );
  fdef1a3 \mem_reg[26][0]  ( .D(n296), .E(n52), .CLK(n398), .Q(\mem[26][0] )
         );
  fdef1a3 \mem_reg[24][7]  ( .D(n359), .E(n50), .CLK(n399), .Q(\mem[24][7] )
         );
  fdef1a3 \mem_reg[24][6]  ( .D(n350), .E(n50), .CLK(n399), .Q(\mem[24][6] )
         );
  fdef1a3 \mem_reg[24][5]  ( .D(n341), .E(n50), .CLK(n399), .Q(\mem[24][5] )
         );
  fdef1a3 \mem_reg[24][4]  ( .D(n332), .E(n50), .CLK(n400), .Q(\mem[24][4] )
         );
  fdef1a3 \mem_reg[24][3]  ( .D(n323), .E(n50), .CLK(n400), .Q(\mem[24][3] )
         );
  fdef1a3 \mem_reg[24][2]  ( .D(n314), .E(n50), .CLK(n400), .Q(\mem[24][2] )
         );
  fdef1a3 \mem_reg[24][1]  ( .D(n305), .E(n50), .CLK(n400), .Q(\mem[24][1] )
         );
  fdef1a3 \mem_reg[24][0]  ( .D(n296), .E(n50), .CLK(n400), .Q(\mem[24][0] )
         );
  fdef1a3 \mem_reg[22][7]  ( .D(n359), .E(n48), .CLK(n401), .Q(\mem[22][7] )
         );
  fdef1a3 \mem_reg[22][6]  ( .D(n350), .E(n48), .CLK(n401), .Q(\mem[22][6] )
         );
  fdef1a3 \mem_reg[22][5]  ( .D(n341), .E(n48), .CLK(n401), .Q(\mem[22][5] )
         );
  fdef1a3 \mem_reg[22][4]  ( .D(n332), .E(n48), .CLK(n401), .Q(\mem[22][4] )
         );
  fdef1a3 \mem_reg[22][3]  ( .D(n323), .E(n48), .CLK(n401), .Q(\mem[22][3] )
         );
  fdef1a3 \mem_reg[22][2]  ( .D(n314), .E(n48), .CLK(n402), .Q(\mem[22][2] )
         );
  fdef1a3 \mem_reg[22][1]  ( .D(n305), .E(n48), .CLK(n402), .Q(\mem[22][1] )
         );
  fdef1a3 \mem_reg[22][0]  ( .D(n296), .E(n48), .CLK(n402), .Q(\mem[22][0] )
         );
  fdef1a3 \mem_reg[20][7]  ( .D(n359), .E(n46), .CLK(n403), .Q(\mem[20][7] )
         );
  fdef1a3 \mem_reg[20][6]  ( .D(n350), .E(n46), .CLK(n403), .Q(\mem[20][6] )
         );
  fdef1a3 \mem_reg[20][5]  ( .D(n341), .E(n46), .CLK(n403), .Q(\mem[20][5] )
         );
  fdef1a3 \mem_reg[20][4]  ( .D(n332), .E(n46), .CLK(n403), .Q(\mem[20][4] )
         );
  fdef1a3 \mem_reg[20][3]  ( .D(n323), .E(n46), .CLK(n403), .Q(\mem[20][3] )
         );
  fdef1a3 \mem_reg[20][2]  ( .D(n314), .E(n46), .CLK(n403), .Q(\mem[20][2] )
         );
  fdef1a3 \mem_reg[20][1]  ( .D(n305), .E(n46), .CLK(n403), .Q(\mem[20][1] )
         );
  fdef1a3 \mem_reg[20][0]  ( .D(n296), .E(n46), .CLK(n404), .Q(\mem[20][0] )
         );
  fdef1a3 \mem_reg[18][7]  ( .D(n360), .E(n44), .CLK(n405), .Q(\mem[18][7] )
         );
  fdef1a3 \mem_reg[18][6]  ( .D(n351), .E(n44), .CLK(n405), .Q(\mem[18][6] )
         );
  fdef1a3 \mem_reg[18][5]  ( .D(n342), .E(n44), .CLK(n405), .Q(\mem[18][5] )
         );
  fdef1a3 \mem_reg[18][4]  ( .D(n333), .E(n44), .CLK(n405), .Q(\mem[18][4] )
         );
  fdef1a3 \mem_reg[18][3]  ( .D(n324), .E(n44), .CLK(n405), .Q(\mem[18][3] )
         );
  fdef1a3 \mem_reg[18][2]  ( .D(n315), .E(n44), .CLK(n405), .Q(\mem[18][2] )
         );
  fdef1a3 \mem_reg[18][1]  ( .D(n306), .E(n44), .CLK(n405), .Q(\mem[18][1] )
         );
  fdef1a3 \mem_reg[18][0]  ( .D(n297), .E(n44), .CLK(n405), .Q(\mem[18][0] )
         );
  fdef1a3 \mem_reg[16][7]  ( .D(n360), .E(n42), .CLK(n406), .Q(\mem[16][7] )
         );
  fdef1a3 \mem_reg[16][6]  ( .D(n351), .E(n42), .CLK(n406), .Q(\mem[16][6] )
         );
  fdef1a3 \mem_reg[16][5]  ( .D(n342), .E(n42), .CLK(n407), .Q(\mem[16][5] )
         );
  fdef1a3 \mem_reg[16][4]  ( .D(n333), .E(n42), .CLK(n407), .Q(\mem[16][4] )
         );
  fdef1a3 \mem_reg[16][3]  ( .D(n324), .E(n42), .CLK(n407), .Q(\mem[16][3] )
         );
  fdef1a3 \mem_reg[16][2]  ( .D(n315), .E(n42), .CLK(n407), .Q(\mem[16][2] )
         );
  fdef1a3 \mem_reg[16][1]  ( .D(n306), .E(n42), .CLK(n407), .Q(\mem[16][1] )
         );
  fdef1a3 \mem_reg[16][0]  ( .D(n297), .E(n42), .CLK(n407), .Q(\mem[16][0] )
         );
  fdef1a3 \mem_reg[14][7]  ( .D(n360), .E(n40), .CLK(n408), .Q(\mem[14][7] )
         );
  fdef1a3 \mem_reg[14][6]  ( .D(n351), .E(n40), .CLK(n408), .Q(\mem[14][6] )
         );
  fdef1a3 \mem_reg[14][5]  ( .D(n342), .E(n40), .CLK(n408), .Q(\mem[14][5] )
         );
  fdef1a3 \mem_reg[14][4]  ( .D(n333), .E(n40), .CLK(n408), .Q(\mem[14][4] )
         );
  fdef1a3 \mem_reg[14][3]  ( .D(n324), .E(n40), .CLK(n409), .Q(\mem[14][3] )
         );
  fdef1a3 \mem_reg[14][2]  ( .D(n315), .E(n40), .CLK(n409), .Q(\mem[14][2] )
         );
  fdef1a3 \mem_reg[14][1]  ( .D(n306), .E(n40), .CLK(n409), .Q(\mem[14][1] )
         );
  fdef1a3 \mem_reg[14][0]  ( .D(n297), .E(n40), .CLK(n409), .Q(\mem[14][0] )
         );
  fdef1a3 \mem_reg[12][7]  ( .D(n360), .E(n38), .CLK(n410), .Q(\mem[12][7] )
         );
  fdef1a3 \mem_reg[12][6]  ( .D(n351), .E(n38), .CLK(n410), .Q(\mem[12][6] )
         );
  fdef1a3 \mem_reg[12][5]  ( .D(n342), .E(n38), .CLK(n410), .Q(\mem[12][5] )
         );
  fdef1a3 \mem_reg[12][4]  ( .D(n333), .E(n38), .CLK(n410), .Q(\mem[12][4] )
         );
  fdef1a3 \mem_reg[12][3]  ( .D(n324), .E(n38), .CLK(n410), .Q(\mem[12][3] )
         );
  fdef1a3 \mem_reg[12][2]  ( .D(n315), .E(n38), .CLK(n410), .Q(\mem[12][2] )
         );
  fdef1a3 \mem_reg[12][1]  ( .D(n306), .E(n38), .CLK(n411), .Q(\mem[12][1] )
         );
  fdef1a3 \mem_reg[12][0]  ( .D(n297), .E(n38), .CLK(n411), .Q(\mem[12][0] )
         );
  fdef1a3 \mem_reg[10][7]  ( .D(n360), .E(n36), .CLK(n412), .Q(\mem[10][7] )
         );
  fdef1a3 \mem_reg[10][6]  ( .D(n351), .E(n36), .CLK(n412), .Q(\mem[10][6] )
         );
  fdef1a3 \mem_reg[10][5]  ( .D(n342), .E(n36), .CLK(n412), .Q(\mem[10][5] )
         );
  fdef1a3 \mem_reg[10][4]  ( .D(n333), .E(n36), .CLK(n412), .Q(\mem[10][4] )
         );
  fdef1a3 \mem_reg[10][3]  ( .D(n324), .E(n36), .CLK(n412), .Q(\mem[10][3] )
         );
  fdef1a3 \mem_reg[10][2]  ( .D(n315), .E(n36), .CLK(n412), .Q(\mem[10][2] )
         );
  fdef1a3 \mem_reg[10][1]  ( .D(n306), .E(n36), .CLK(n412), .Q(\mem[10][1] )
         );
  fdef1a3 \mem_reg[10][0]  ( .D(n297), .E(n36), .CLK(n412), .Q(\mem[10][0] )
         );
  fdef1a3 \mem_reg[8][7]  ( .D(n361), .E(n34), .CLK(n413), .Q(\mem[8][7] ) );
  fdef1a3 \mem_reg[8][6]  ( .D(n352), .E(n34), .CLK(n414), .Q(\mem[8][6] ) );
  fdef1a3 \mem_reg[8][5]  ( .D(n343), .E(n34), .CLK(n414), .Q(\mem[8][5] ) );
  fdef1a3 \mem_reg[8][4]  ( .D(n334), .E(n34), .CLK(n414), .Q(\mem[8][4] ) );
  fdef1a3 \mem_reg[8][3]  ( .D(n325), .E(n34), .CLK(n414), .Q(\mem[8][3] ) );
  fdef1a3 \mem_reg[8][2]  ( .D(n316), .E(n34), .CLK(n414), .Q(\mem[8][2] ) );
  fdef1a3 \mem_reg[8][1]  ( .D(n307), .E(n34), .CLK(n414), .Q(\mem[8][1] ) );
  fdef1a3 \mem_reg[8][0]  ( .D(n298), .E(n34), .CLK(n414), .Q(\mem[8][0] ) );
  fdef1a3 \mem_reg[6][7]  ( .D(n361), .E(n32), .CLK(n415), .Q(\mem[6][7] ) );
  fdef1a3 \mem_reg[6][6]  ( .D(n352), .E(n32), .CLK(n415), .Q(\mem[6][6] ) );
  fdef1a3 \mem_reg[6][5]  ( .D(n343), .E(n32), .CLK(n415), .Q(\mem[6][5] ) );
  fdef1a3 \mem_reg[6][4]  ( .D(n334), .E(n32), .CLK(n416), .Q(\mem[6][4] ) );
  fdef1a3 \mem_reg[6][3]  ( .D(n325), .E(n32), .CLK(n416), .Q(\mem[6][3] ) );
  fdef1a3 \mem_reg[6][2]  ( .D(n316), .E(n32), .CLK(n416), .Q(\mem[6][2] ) );
  fdef1a3 \mem_reg[6][1]  ( .D(n307), .E(n32), .CLK(n416), .Q(\mem[6][1] ) );
  fdef1a3 \mem_reg[6][0]  ( .D(n298), .E(n32), .CLK(n416), .Q(\mem[6][0] ) );
  fdef1a3 \mem_reg[4][7]  ( .D(n361), .E(n30), .CLK(n417), .Q(\mem[4][7] ) );
  fdef1a3 \mem_reg[4][6]  ( .D(n352), .E(n30), .CLK(n417), .Q(\mem[4][6] ) );
  fdef1a3 \mem_reg[4][5]  ( .D(n343), .E(n30), .CLK(n417), .Q(\mem[4][5] ) );
  fdef1a3 \mem_reg[4][4]  ( .D(n334), .E(n30), .CLK(n417), .Q(\mem[4][4] ) );
  fdef1a3 \mem_reg[4][3]  ( .D(n325), .E(n30), .CLK(n417), .Q(\mem[4][3] ) );
  fdef1a3 \mem_reg[4][2]  ( .D(n316), .E(n30), .CLK(n418), .Q(\mem[4][2] ) );
  fdef1a3 \mem_reg[4][1]  ( .D(n307), .E(n30), .CLK(n418), .Q(\mem[4][1] ) );
  fdef1a3 \mem_reg[4][0]  ( .D(n298), .E(n30), .CLK(n418), .Q(\mem[4][0] ) );
  fdef1a3 \mem_reg[2][7]  ( .D(n361), .E(n28), .CLK(n419), .Q(\mem[2][7] ) );
  fdef1a3 \mem_reg[2][6]  ( .D(n352), .E(n28), .CLK(n419), .Q(\mem[2][6] ) );
  fdef1a3 \mem_reg[2][5]  ( .D(n343), .E(n28), .CLK(n419), .Q(\mem[2][5] ) );
  fdef1a3 \mem_reg[2][4]  ( .D(n334), .E(n28), .CLK(n419), .Q(\mem[2][4] ) );
  fdef1a3 \mem_reg[2][3]  ( .D(n325), .E(n28), .CLK(n419), .Q(\mem[2][3] ) );
  fdef1a3 \mem_reg[2][2]  ( .D(n316), .E(n28), .CLK(n419), .Q(\mem[2][2] ) );
  fdef1a3 \mem_reg[2][1]  ( .D(n307), .E(n28), .CLK(n419), .Q(\mem[2][1] ) );
  fdef1a3 \mem_reg[2][0]  ( .D(n298), .E(n28), .CLK(n420), .Q(\mem[2][0] ) );
  fdef1a3 \mem_reg[62][7]  ( .D(n356), .E(n88), .CLK(n365), .Q(\mem[62][7] )
         );
  fdef1a3 \mem_reg[61][7]  ( .D(n356), .E(n87), .CLK(n366), .Q(\mem[61][7] )
         );
  fdef1a3 \mem_reg[61][6]  ( .D(n347), .E(n87), .CLK(n366), .Q(\mem[61][6] )
         );
  fdef1a3 \mem_reg[61][5]  ( .D(n338), .E(n87), .CLK(n367), .Q(\mem[61][5] )
         );
  fdef1a3 \mem_reg[61][4]  ( .D(n329), .E(n87), .CLK(n367), .Q(\mem[61][4] )
         );
  fdef1a3 \mem_reg[61][3]  ( .D(n320), .E(n87), .CLK(n367), .Q(\mem[61][3] )
         );
  fdef1a3 \mem_reg[61][2]  ( .D(n311), .E(n87), .CLK(n367), .Q(\mem[61][2] )
         );
  fdef1a3 \mem_reg[61][1]  ( .D(n302), .E(n87), .CLK(n367), .Q(\mem[61][1] )
         );
  fdef1a3 \mem_reg[61][0]  ( .D(n293), .E(n87), .CLK(n367), .Q(\mem[61][0] )
         );
  fdef1a3 \mem_reg[57][7]  ( .D(n356), .E(n83), .CLK(n370), .Q(\mem[57][7] )
         );
  fdef1a3 \mem_reg[57][6]  ( .D(n347), .E(n83), .CLK(n370), .Q(\mem[57][6] )
         );
  fdef1a3 \mem_reg[57][5]  ( .D(n338), .E(n83), .CLK(n370), .Q(\mem[57][5] )
         );
  fdef1a3 \mem_reg[57][4]  ( .D(n329), .E(n83), .CLK(n370), .Q(\mem[57][4] )
         );
  fdef1a3 \mem_reg[57][3]  ( .D(n320), .E(n83), .CLK(n370), .Q(\mem[57][3] )
         );
  fdef1a3 \mem_reg[57][2]  ( .D(n311), .E(n83), .CLK(n370), .Q(\mem[57][2] )
         );
  fdef1a3 \mem_reg[57][1]  ( .D(n302), .E(n83), .CLK(n371), .Q(\mem[57][1] )
         );
  fdef1a3 \mem_reg[57][0]  ( .D(n293), .E(n83), .CLK(n371), .Q(\mem[57][0] )
         );
  fdef1a3 \mem_reg[53][7]  ( .D(n356), .E(n79), .CLK(n373), .Q(\mem[53][7] )
         );
  fdef1a3 \mem_reg[53][6]  ( .D(n347), .E(n79), .CLK(n374), .Q(\mem[53][6] )
         );
  fdef1a3 \mem_reg[53][5]  ( .D(n338), .E(n79), .CLK(n374), .Q(\mem[53][5] )
         );
  fdef1a3 \mem_reg[53][4]  ( .D(n329), .E(n79), .CLK(n374), .Q(\mem[53][4] )
         );
  fdef1a3 \mem_reg[53][3]  ( .D(n320), .E(n79), .CLK(n374), .Q(\mem[53][3] )
         );
  fdef1a3 \mem_reg[53][2]  ( .D(n311), .E(n79), .CLK(n374), .Q(\mem[53][2] )
         );
  fdef1a3 \mem_reg[53][1]  ( .D(n302), .E(n79), .CLK(n374), .Q(\mem[53][1] )
         );
  fdef1a3 \mem_reg[53][0]  ( .D(n293), .E(n79), .CLK(n374), .Q(\mem[53][0] )
         );
  fdef1a3 \mem_reg[49][7]  ( .D(n357), .E(n75), .CLK(n377), .Q(\mem[49][7] )
         );
  fdef1a3 \mem_reg[49][6]  ( .D(n348), .E(n75), .CLK(n377), .Q(\mem[49][6] )
         );
  fdef1a3 \mem_reg[49][5]  ( .D(n339), .E(n75), .CLK(n377), .Q(\mem[49][5] )
         );
  fdef1a3 \mem_reg[49][4]  ( .D(n330), .E(n75), .CLK(n377), .Q(\mem[49][4] )
         );
  fdef1a3 \mem_reg[49][3]  ( .D(n321), .E(n75), .CLK(n377), .Q(\mem[49][3] )
         );
  fdef1a3 \mem_reg[49][2]  ( .D(n312), .E(n75), .CLK(n378), .Q(\mem[49][2] )
         );
  fdef1a3 \mem_reg[49][1]  ( .D(n303), .E(n75), .CLK(n378), .Q(\mem[49][1] )
         );
  fdef1a3 \mem_reg[49][0]  ( .D(n294), .E(n75), .CLK(n378), .Q(\mem[49][0] )
         );
  fdef1a3 \mem_reg[45][7]  ( .D(n357), .E(n71), .CLK(n381), .Q(\mem[45][7] )
         );
  fdef1a3 \mem_reg[45][6]  ( .D(n348), .E(n71), .CLK(n381), .Q(\mem[45][6] )
         );
  fdef1a3 \mem_reg[45][5]  ( .D(n339), .E(n71), .CLK(n381), .Q(\mem[45][5] )
         );
  fdef1a3 \mem_reg[45][4]  ( .D(n330), .E(n71), .CLK(n381), .Q(\mem[45][4] )
         );
  fdef1a3 \mem_reg[45][3]  ( .D(n321), .E(n71), .CLK(n381), .Q(\mem[45][3] )
         );
  fdef1a3 \mem_reg[45][2]  ( .D(n312), .E(n71), .CLK(n381), .Q(\mem[45][2] )
         );
  fdef1a3 \mem_reg[45][1]  ( .D(n303), .E(n71), .CLK(n381), .Q(\mem[45][1] )
         );
  fdef1a3 \mem_reg[45][0]  ( .D(n294), .E(n71), .CLK(n381), .Q(\mem[45][0] )
         );
  fdef1a3 \mem_reg[41][7]  ( .D(n358), .E(n67), .CLK(n384), .Q(\mem[41][7] )
         );
  fdef1a3 \mem_reg[41][6]  ( .D(n349), .E(n67), .CLK(n384), .Q(\mem[41][6] )
         );
  fdef1a3 \mem_reg[41][5]  ( .D(n340), .E(n67), .CLK(n384), .Q(\mem[41][5] )
         );
  fdef1a3 \mem_reg[41][4]  ( .D(n331), .E(n67), .CLK(n384), .Q(\mem[41][4] )
         );
  fdef1a3 \mem_reg[41][3]  ( .D(n322), .E(n67), .CLK(n385), .Q(\mem[41][3] )
         );
  fdef1a3 \mem_reg[41][2]  ( .D(n313), .E(n67), .CLK(n385), .Q(\mem[41][2] )
         );
  fdef1a3 \mem_reg[41][1]  ( .D(n304), .E(n67), .CLK(n385), .Q(\mem[41][1] )
         );
  fdef1a3 \mem_reg[41][0]  ( .D(n295), .E(n67), .CLK(n385), .Q(\mem[41][0] )
         );
  fdef1a3 \mem_reg[37][7]  ( .D(n358), .E(n63), .CLK(n388), .Q(\mem[37][7] )
         );
  fdef1a3 \mem_reg[37][6]  ( .D(n349), .E(n63), .CLK(n388), .Q(\mem[37][6] )
         );
  fdef1a3 \mem_reg[37][5]  ( .D(n340), .E(n63), .CLK(n388), .Q(\mem[37][5] )
         );
  fdef1a3 \mem_reg[37][4]  ( .D(n331), .E(n63), .CLK(n388), .Q(\mem[37][4] )
         );
  fdef1a3 \mem_reg[37][3]  ( .D(n322), .E(n63), .CLK(n388), .Q(\mem[37][3] )
         );
  fdef1a3 \mem_reg[37][2]  ( .D(n313), .E(n63), .CLK(n388), .Q(\mem[37][2] )
         );
  fdef1a3 \mem_reg[37][1]  ( .D(n304), .E(n63), .CLK(n388), .Q(\mem[37][1] )
         );
  fdef1a3 \mem_reg[37][0]  ( .D(n295), .E(n63), .CLK(n388), .Q(\mem[37][0] )
         );
  fdef1a3 \mem_reg[33][7]  ( .D(n358), .E(n59), .CLK(n391), .Q(\mem[33][7] )
         );
  fdef1a3 \mem_reg[33][6]  ( .D(n349), .E(n59), .CLK(n391), .Q(\mem[33][6] )
         );
  fdef1a3 \mem_reg[33][5]  ( .D(n340), .E(n59), .CLK(n391), .Q(\mem[33][5] )
         );
  fdef1a3 \mem_reg[33][4]  ( .D(n331), .E(n59), .CLK(n392), .Q(\mem[33][4] )
         );
  fdef1a3 \mem_reg[33][3]  ( .D(n322), .E(n59), .CLK(n392), .Q(\mem[33][3] )
         );
  fdef1a3 \mem_reg[33][2]  ( .D(n313), .E(n59), .CLK(n392), .Q(\mem[33][2] )
         );
  fdef1a3 \mem_reg[33][1]  ( .D(n304), .E(n59), .CLK(n392), .Q(\mem[33][1] )
         );
  fdef1a3 \mem_reg[33][0]  ( .D(n295), .E(n59), .CLK(n392), .Q(\mem[33][0] )
         );
  fdef1a3 \mem_reg[29][7]  ( .D(n359), .E(n55), .CLK(n395), .Q(\mem[29][7] )
         );
  fdef1a3 \mem_reg[29][6]  ( .D(n350), .E(n55), .CLK(n395), .Q(\mem[29][6] )
         );
  fdef1a3 \mem_reg[29][5]  ( .D(n341), .E(n55), .CLK(n395), .Q(\mem[29][5] )
         );
  fdef1a3 \mem_reg[29][4]  ( .D(n332), .E(n55), .CLK(n395), .Q(\mem[29][4] )
         );
  fdef1a3 \mem_reg[29][3]  ( .D(n323), .E(n55), .CLK(n395), .Q(\mem[29][3] )
         );
  fdef1a3 \mem_reg[29][2]  ( .D(n314), .E(n55), .CLK(n395), .Q(\mem[29][2] )
         );
  fdef1a3 \mem_reg[29][1]  ( .D(n305), .E(n55), .CLK(n395), .Q(\mem[29][1] )
         );
  fdef1a3 \mem_reg[29][0]  ( .D(n296), .E(n55), .CLK(n396), .Q(\mem[29][0] )
         );
  fdef1a3 \mem_reg[25][7]  ( .D(n359), .E(n51), .CLK(n398), .Q(\mem[25][7] )
         );
  fdef1a3 \mem_reg[25][6]  ( .D(n350), .E(n51), .CLK(n398), .Q(\mem[25][6] )
         );
  fdef1a3 \mem_reg[25][5]  ( .D(n341), .E(n51), .CLK(n399), .Q(\mem[25][5] )
         );
  fdef1a3 \mem_reg[25][4]  ( .D(n332), .E(n51), .CLK(n399), .Q(\mem[25][4] )
         );
  fdef1a3 \mem_reg[25][3]  ( .D(n323), .E(n51), .CLK(n399), .Q(\mem[25][3] )
         );
  fdef1a3 \mem_reg[25][2]  ( .D(n314), .E(n51), .CLK(n399), .Q(\mem[25][2] )
         );
  fdef1a3 \mem_reg[25][1]  ( .D(n305), .E(n51), .CLK(n399), .Q(\mem[25][1] )
         );
  fdef1a3 \mem_reg[25][0]  ( .D(n296), .E(n51), .CLK(n399), .Q(\mem[25][0] )
         );
  fdef1a3 \mem_reg[21][7]  ( .D(n359), .E(n47), .CLK(n402), .Q(\mem[21][7] )
         );
  fdef1a3 \mem_reg[21][6]  ( .D(n350), .E(n47), .CLK(n402), .Q(\mem[21][6] )
         );
  fdef1a3 \mem_reg[21][5]  ( .D(n341), .E(n47), .CLK(n402), .Q(\mem[21][5] )
         );
  fdef1a3 \mem_reg[21][4]  ( .D(n332), .E(n47), .CLK(n402), .Q(\mem[21][4] )
         );
  fdef1a3 \mem_reg[21][3]  ( .D(n323), .E(n47), .CLK(n402), .Q(\mem[21][3] )
         );
  fdef1a3 \mem_reg[21][2]  ( .D(n314), .E(n47), .CLK(n402), .Q(\mem[21][2] )
         );
  fdef1a3 \mem_reg[21][1]  ( .D(n305), .E(n47), .CLK(n403), .Q(\mem[21][1] )
         );
  fdef1a3 \mem_reg[21][0]  ( .D(n296), .E(n47), .CLK(n403), .Q(\mem[21][0] )
         );
  fdef1a3 \mem_reg[17][7]  ( .D(n360), .E(n43), .CLK(n405), .Q(\mem[17][7] )
         );
  fdef1a3 \mem_reg[17][6]  ( .D(n351), .E(n43), .CLK(n406), .Q(\mem[17][6] )
         );
  fdef1a3 \mem_reg[17][5]  ( .D(n342), .E(n43), .CLK(n406), .Q(\mem[17][5] )
         );
  fdef1a3 \mem_reg[17][4]  ( .D(n333), .E(n43), .CLK(n406), .Q(\mem[17][4] )
         );
  fdef1a3 \mem_reg[17][3]  ( .D(n324), .E(n43), .CLK(n406), .Q(\mem[17][3] )
         );
  fdef1a3 \mem_reg[17][2]  ( .D(n315), .E(n43), .CLK(n406), .Q(\mem[17][2] )
         );
  fdef1a3 \mem_reg[17][1]  ( .D(n306), .E(n43), .CLK(n406), .Q(\mem[17][1] )
         );
  fdef1a3 \mem_reg[17][0]  ( .D(n297), .E(n43), .CLK(n406), .Q(\mem[17][0] )
         );
  fdef1a3 \mem_reg[13][7]  ( .D(n360), .E(n39), .CLK(n409), .Q(\mem[13][7] )
         );
  fdef1a3 \mem_reg[13][6]  ( .D(n351), .E(n39), .CLK(n409), .Q(\mem[13][6] )
         );
  fdef1a3 \mem_reg[13][5]  ( .D(n342), .E(n39), .CLK(n409), .Q(\mem[13][5] )
         );
  fdef1a3 \mem_reg[13][4]  ( .D(n333), .E(n39), .CLK(n409), .Q(\mem[13][4] )
         );
  fdef1a3 \mem_reg[13][3]  ( .D(n324), .E(n39), .CLK(n409), .Q(\mem[13][3] )
         );
  fdef1a3 \mem_reg[13][2]  ( .D(n315), .E(n39), .CLK(n410), .Q(\mem[13][2] )
         );
  fdef1a3 \mem_reg[13][1]  ( .D(n306), .E(n39), .CLK(n410), .Q(\mem[13][1] )
         );
  fdef1a3 \mem_reg[13][0]  ( .D(n297), .E(n39), .CLK(n410), .Q(\mem[13][0] )
         );
  fdef1a3 \mem_reg[9][7]  ( .D(n360), .E(n35), .CLK(n413), .Q(\mem[9][7] ) );
  fdef1a3 \mem_reg[9][6]  ( .D(n351), .E(n35), .CLK(n413), .Q(\mem[9][6] ) );
  fdef1a3 \mem_reg[9][5]  ( .D(n342), .E(n35), .CLK(n413), .Q(\mem[9][5] ) );
  fdef1a3 \mem_reg[9][4]  ( .D(n333), .E(n35), .CLK(n413), .Q(\mem[9][4] ) );
  fdef1a3 \mem_reg[9][3]  ( .D(n324), .E(n35), .CLK(n413), .Q(\mem[9][3] ) );
  fdef1a3 \mem_reg[9][2]  ( .D(n315), .E(n35), .CLK(n413), .Q(\mem[9][2] ) );
  fdef1a3 \mem_reg[9][1]  ( .D(n306), .E(n35), .CLK(n413), .Q(\mem[9][1] ) );
  fdef1a3 \mem_reg[9][0]  ( .D(n297), .E(n35), .CLK(n413), .Q(\mem[9][0] ) );
  fdef1a3 \mem_reg[5][7]  ( .D(n361), .E(n31), .CLK(n416), .Q(\mem[5][7] ) );
  fdef1a3 \mem_reg[5][6]  ( .D(n352), .E(n31), .CLK(n416), .Q(\mem[5][6] ) );
  fdef1a3 \mem_reg[5][5]  ( .D(n343), .E(n31), .CLK(n416), .Q(\mem[5][5] ) );
  fdef1a3 \mem_reg[5][4]  ( .D(n334), .E(n31), .CLK(n416), .Q(\mem[5][4] ) );
  fdef1a3 \mem_reg[5][3]  ( .D(n325), .E(n31), .CLK(n417), .Q(\mem[5][3] ) );
  fdef1a3 \mem_reg[5][2]  ( .D(n316), .E(n31), .CLK(n417), .Q(\mem[5][2] ) );
  fdef1a3 \mem_reg[5][1]  ( .D(n307), .E(n31), .CLK(n417), .Q(\mem[5][1] ) );
  fdef1a3 \mem_reg[5][0]  ( .D(n298), .E(n31), .CLK(n417), .Q(\mem[5][0] ) );
  fdef1a3 \mem_reg[1][7]  ( .D(n361), .E(n27), .CLK(n420), .Q(\mem[1][7] ) );
  fdef1a3 \mem_reg[1][6]  ( .D(n352), .E(n27), .CLK(n420), .Q(\mem[1][6] ) );
  fdef1a3 \mem_reg[1][5]  ( .D(n343), .E(n27), .CLK(n420), .Q(\mem[1][5] ) );
  fdef1a3 \mem_reg[1][4]  ( .D(n334), .E(n27), .CLK(n420), .Q(\mem[1][4] ) );
  fdef1a3 \mem_reg[1][3]  ( .D(n325), .E(n27), .CLK(n420), .Q(\mem[1][3] ) );
  fdef1a3 \mem_reg[1][2]  ( .D(n316), .E(n27), .CLK(n420), .Q(\mem[1][2] ) );
  fdef1a3 \mem_reg[1][1]  ( .D(n307), .E(n27), .CLK(n420), .Q(\mem[1][1] ) );
  fdef1a3 \mem_reg[1][0]  ( .D(n298), .E(n27), .CLK(n420), .Q(\mem[1][0] ) );
  tri1a2 \do_tri[0]  ( .A(do_reg[0]), .E(n25), .Y(do[0]) );
  tri1a2 \do_tri[1]  ( .A(do_reg[1]), .E(n25), .Y(do[1]) );
  tri1a2 \do_tri[2]  ( .A(do_reg[2]), .E(n25), .Y(do[2]) );
  tri1a2 \do_tri[3]  ( .A(do_reg[3]), .E(n25), .Y(do[3]) );
  tri1a2 \do_tri[4]  ( .A(do_reg[4]), .E(n25), .Y(do[4]) );
  tri1a2 \do_tri[5]  ( .A(do_reg[5]), .E(n25), .Y(do[5]) );
  tri1a2 \do_tri[6]  ( .A(do_reg[6]), .E(n25), .Y(do[6]) );
  tri1a2 \do_tri[7]  ( .A(do_reg[7]), .E(n25), .Y(do[7]) );
  fdef1a3 \do_reg_reg[7]  ( .D(N24), .E(rce), .CLK(n478), .Q(do_reg[7]) );
  fdef1a3 \do_reg_reg[6]  ( .D(N25), .E(rce), .CLK(n478), .Q(do_reg[6]) );
  fdef1a3 \do_reg_reg[5]  ( .D(N26), .E(rce), .CLK(n478), .Q(do_reg[5]) );
  fdef1a3 \do_reg_reg[4]  ( .D(N27), .E(rce), .CLK(n478), .Q(do_reg[4]) );
  fdef1a3 \do_reg_reg[3]  ( .D(N28), .E(rce), .CLK(n478), .Q(do_reg[3]) );
  fdef1a3 \do_reg_reg[2]  ( .D(N29), .E(rce), .CLK(n478), .Q(do_reg[2]) );
  fdef1a3 \do_reg_reg[1]  ( .D(N30), .E(rce), .CLK(n478), .Q(do_reg[1]) );
  fdef1a3 \do_reg_reg[0]  ( .D(N31), .E(rce), .CLK(n478), .Q(do_reg[0]) );
  and2b3 U38 ( .B(n16), .A(waddr[5]), .Y(n12) );
  and2a1 U57 ( .A(we), .B(wce), .Y(n16) );
  clk1a6 U67 ( .A(n279), .Y(n283) );
  clk1a6 U76 ( .A(n280), .Y(n282) );
  clk1a6 U81 ( .A(n279), .Y(n284) );
  clk1a6 U84 ( .A(n278), .Y(n286) );
  clk1a6 U87 ( .A(n278), .Y(n285) );
  clk1a6 U88 ( .A(n277), .Y(n287) );
  clk1a6 U91 ( .A(n276), .Y(n289) );
  clk1a6 U92 ( .A(n277), .Y(n288) );
  clk1a6 U93 ( .A(n276), .Y(n290) );
  clk1a6 U94 ( .A(n275), .Y(n292) );
  clk1a6 U95 ( .A(n275), .Y(n291) );
  clk1a6 U96 ( .A(N20), .Y(n246) );
  clk1a6 U97 ( .A(N20), .Y(n247) );
  clk1a3 U98 ( .A(n423), .Y(n419) );
  clk1a3 U99 ( .A(n423), .Y(n418) );
  clk1a3 U100 ( .A(n424), .Y(n417) );
  clk1a3 U101 ( .A(n424), .Y(n416) );
  clk1a3 U102 ( .A(n425), .Y(n415) );
  clk1a3 U103 ( .A(n425), .Y(n414) );
  clk1a3 U104 ( .A(n426), .Y(n413) );
  clk1a3 U105 ( .A(n426), .Y(n412) );
  clk1a3 U106 ( .A(n427), .Y(n411) );
  clk1a3 U107 ( .A(n427), .Y(n410) );
  clk1a3 U108 ( .A(n428), .Y(n409) );
  clk1a3 U109 ( .A(n428), .Y(n408) );
  clk1a3 U110 ( .A(n429), .Y(n407) );
  clk1a3 U111 ( .A(n429), .Y(n406) );
  clk1a3 U112 ( .A(n430), .Y(n405) );
  clk1a3 U113 ( .A(n430), .Y(n404) );
  clk1a3 U114 ( .A(n431), .Y(n403) );
  clk1a3 U115 ( .A(n431), .Y(n402) );
  clk1a3 U116 ( .A(n432), .Y(n401) );
  clk1a3 U117 ( .A(n432), .Y(n400) );
  clk1a3 U118 ( .A(n433), .Y(n399) );
  clk1a3 U119 ( .A(n433), .Y(n398) );
  clk1a3 U120 ( .A(n434), .Y(n397) );
  clk1a3 U121 ( .A(n434), .Y(n396) );
  clk1a3 U122 ( .A(n435), .Y(n395) );
  clk1a3 U123 ( .A(n435), .Y(n394) );
  clk1a3 U124 ( .A(n436), .Y(n393) );
  clk1a3 U125 ( .A(n436), .Y(n392) );
  clk1a3 U126 ( .A(n437), .Y(n391) );
  clk1a3 U127 ( .A(n437), .Y(n390) );
  clk1a3 U128 ( .A(n438), .Y(n389) );
  clk1a3 U129 ( .A(n438), .Y(n388) );
  clk1a3 U130 ( .A(n439), .Y(n387) );
  clk1a3 U131 ( .A(n439), .Y(n386) );
  clk1a3 U132 ( .A(n440), .Y(n385) );
  clk1a3 U133 ( .A(n440), .Y(n384) );
  clk1a3 U134 ( .A(n441), .Y(n383) );
  clk1a3 U135 ( .A(n441), .Y(n382) );
  clk1a3 U136 ( .A(n442), .Y(n381) );
  clk1a3 U137 ( .A(n442), .Y(n380) );
  clk1a3 U138 ( .A(n443), .Y(n379) );
  clk1a3 U139 ( .A(n443), .Y(n378) );
  clk1a3 U140 ( .A(n444), .Y(n377) );
  clk1a3 U141 ( .A(n444), .Y(n376) );
  clk1a3 U142 ( .A(n445), .Y(n375) );
  clk1a3 U143 ( .A(n445), .Y(n374) );
  clk1a3 U144 ( .A(n446), .Y(n373) );
  clk1a3 U145 ( .A(n446), .Y(n372) );
  clk1a3 U146 ( .A(n447), .Y(n371) );
  clk1a3 U147 ( .A(n447), .Y(n370) );
  clk1a3 U148 ( .A(n448), .Y(n369) );
  clk1a3 U149 ( .A(n448), .Y(n368) );
  clk1a3 U150 ( .A(n449), .Y(n367) );
  clk1a3 U151 ( .A(n449), .Y(n366) );
  clk1a3 U152 ( .A(n422), .Y(n420) );
  clk1a3 U153 ( .A(n422), .Y(n421) );
  clk1a3 U154 ( .A(n464), .Y(n423) );
  clk1a3 U155 ( .A(n464), .Y(n424) );
  clk1a3 U156 ( .A(n463), .Y(n425) );
  clk1a3 U157 ( .A(n463), .Y(n426) );
  clk1a3 U158 ( .A(n462), .Y(n427) );
  clk1a3 U159 ( .A(n462), .Y(n428) );
  clk1a3 U160 ( .A(n461), .Y(n429) );
  clk1a3 U161 ( .A(n461), .Y(n430) );
  clk1a3 U162 ( .A(n460), .Y(n431) );
  clk1a3 U163 ( .A(n460), .Y(n432) );
  clk1a3 U164 ( .A(n459), .Y(n433) );
  clk1a3 U165 ( .A(n459), .Y(n434) );
  clk1a3 U166 ( .A(n458), .Y(n435) );
  clk1a3 U167 ( .A(n458), .Y(n436) );
  clk1a3 U168 ( .A(n457), .Y(n437) );
  clk1a3 U169 ( .A(n457), .Y(n438) );
  clk1a3 U170 ( .A(n456), .Y(n439) );
  clk1a3 U171 ( .A(n456), .Y(n440) );
  clk1a3 U172 ( .A(n455), .Y(n441) );
  clk1a3 U173 ( .A(n455), .Y(n442) );
  clk1a3 U174 ( .A(n454), .Y(n443) );
  clk1a3 U175 ( .A(n454), .Y(n444) );
  clk1a3 U176 ( .A(n453), .Y(n445) );
  clk1a3 U177 ( .A(n453), .Y(n446) );
  clk1a3 U178 ( .A(n452), .Y(n447) );
  clk1a3 U179 ( .A(n452), .Y(n448) );
  clk1a6 U180 ( .A(n280), .Y(n281) );
  clk1a3 U181 ( .A(n450), .Y(n365) );
  clk1a3 U182 ( .A(n451), .Y(n450) );
  clk1a3 U183 ( .A(n465), .Y(n422) );
  clk1a3 U184 ( .A(n466), .Y(n465) );
  clk1a3 U185 ( .A(n466), .Y(n464) );
  clk1a3 U186 ( .A(n467), .Y(n463) );
  clk1a3 U187 ( .A(n467), .Y(n462) );
  clk1a3 U188 ( .A(n468), .Y(n461) );
  clk1a3 U189 ( .A(n468), .Y(n460) );
  clk1a3 U190 ( .A(n469), .Y(n459) );
  clk1a3 U191 ( .A(n469), .Y(n458) );
  clk1a3 U192 ( .A(n470), .Y(n457) );
  clk1a3 U193 ( .A(n470), .Y(n456) );
  clk1a3 U194 ( .A(n471), .Y(n455) );
  clk1a3 U195 ( .A(n471), .Y(n454) );
  clk1a3 U196 ( .A(n472), .Y(n453) );
  clk1a3 U197 ( .A(n472), .Y(n452) );
  clk1a3 U198 ( .A(n451), .Y(n449) );
  clk1a3 U199 ( .A(n473), .Y(n451) );
  clk1a3 U200 ( .A(n474), .Y(n473) );
  clk1a3 U201 ( .A(n272), .Y(n280) );
  clk1a3 U202 ( .A(n272), .Y(n279) );
  clk1a3 U203 ( .A(n273), .Y(n278) );
  clk1a3 U204 ( .A(n273), .Y(n277) );
  clk1a3 U205 ( .A(n274), .Y(n276) );
  clk1a3 U206 ( .A(n274), .Y(n275) );
  clk1a3 U207 ( .A(n477), .Y(n466) );
  clk1a3 U208 ( .A(n477), .Y(n467) );
  clk1a3 U209 ( .A(n476), .Y(n468) );
  clk1a3 U210 ( .A(n476), .Y(n469) );
  clk1a3 U211 ( .A(n475), .Y(n470) );
  clk1a3 U212 ( .A(n475), .Y(n471) );
  clk1a3 U213 ( .A(n474), .Y(n472) );
  clk1a6 U214 ( .A(N20), .Y(n245) );
  clk1a6 U215 ( .A(n258), .Y(n262) );
  clk1a6 U216 ( .A(n259), .Y(n261) );
  clk1a6 U217 ( .A(n258), .Y(n263) );
  clk1a6 U218 ( .A(n257), .Y(n265) );
  clk1a6 U219 ( .A(n257), .Y(n264) );
  clk1a6 U220 ( .A(n256), .Y(n266) );
  clk1a6 U221 ( .A(n255), .Y(n268) );
  clk1a6 U222 ( .A(n256), .Y(n267) );
  clk1a6 U223 ( .A(n255), .Y(n269) );
  clk1a6 U224 ( .A(n254), .Y(n271) );
  clk1a6 U225 ( .A(n254), .Y(n270) );
  clk1a6 U226 ( .A(n259), .Y(n260) );
  clk1a3 U227 ( .A(rclk), .Y(n478) );
  clk1a3 U228 ( .A(wclk), .Y(n477) );
  clk1a3 U229 ( .A(wclk), .Y(n476) );
  clk1a3 U230 ( .A(wclk), .Y(n475) );
  clk1a3 U231 ( .A(wclk), .Y(n474) );
  clk1a3 U232 ( .A(N17), .Y(n272) );
  clk1a3 U233 ( .A(N17), .Y(n273) );
  clk1a3 U234 ( .A(N17), .Y(n274) );
  buf1a9 U235 ( .A(n299), .Y(n297) );
  buf1a9 U236 ( .A(n308), .Y(n306) );
  buf1a9 U237 ( .A(n317), .Y(n315) );
  buf1a9 U238 ( .A(n326), .Y(n324) );
  buf1a9 U239 ( .A(n335), .Y(n333) );
  buf1a9 U240 ( .A(n344), .Y(n342) );
  buf1a9 U241 ( .A(n353), .Y(n351) );
  buf1a9 U242 ( .A(n362), .Y(n360) );
  buf1a9 U243 ( .A(n300), .Y(n296) );
  buf1a9 U244 ( .A(n309), .Y(n305) );
  buf1a9 U245 ( .A(n318), .Y(n314) );
  buf1a9 U246 ( .A(n327), .Y(n323) );
  buf1a9 U247 ( .A(n336), .Y(n332) );
  buf1a9 U248 ( .A(n345), .Y(n341) );
  buf1a9 U249 ( .A(n354), .Y(n350) );
  buf1a9 U250 ( .A(n363), .Y(n359) );
  buf1a9 U251 ( .A(n300), .Y(n295) );
  buf1a9 U252 ( .A(n309), .Y(n304) );
  buf1a9 U253 ( .A(n318), .Y(n313) );
  buf1a9 U254 ( .A(n327), .Y(n322) );
  buf1a9 U255 ( .A(n336), .Y(n331) );
  buf1a9 U256 ( .A(n345), .Y(n340) );
  buf1a9 U257 ( .A(n354), .Y(n349) );
  buf1a9 U258 ( .A(n363), .Y(n358) );
  buf1a9 U259 ( .A(n301), .Y(n294) );
  buf1a9 U260 ( .A(n310), .Y(n303) );
  buf1a9 U261 ( .A(n319), .Y(n312) );
  buf1a9 U262 ( .A(n328), .Y(n321) );
  buf1a9 U263 ( .A(n337), .Y(n330) );
  buf1a9 U264 ( .A(n346), .Y(n339) );
  buf1a9 U265 ( .A(n355), .Y(n348) );
  buf1a9 U266 ( .A(n364), .Y(n357) );
  buf1a9 U267 ( .A(n301), .Y(n293) );
  buf1a9 U268 ( .A(n310), .Y(n302) );
  buf1a9 U269 ( .A(n319), .Y(n311) );
  buf1a9 U270 ( .A(n328), .Y(n320) );
  buf1a9 U271 ( .A(n337), .Y(n329) );
  buf1a9 U272 ( .A(n346), .Y(n338) );
  buf1a9 U273 ( .A(n355), .Y(n347) );
  buf1a9 U274 ( .A(n364), .Y(n356) );
  clk1a6 U275 ( .A(n299), .Y(n298) );
  clk1a6 U276 ( .A(n308), .Y(n307) );
  clk1a6 U277 ( .A(n317), .Y(n316) );
  clk1a6 U278 ( .A(n326), .Y(n325) );
  clk1a6 U279 ( .A(n335), .Y(n334) );
  clk1a6 U280 ( .A(n344), .Y(n343) );
  clk1a6 U281 ( .A(n353), .Y(n352) );
  clk1a6 U282 ( .A(n362), .Y(n361) );
  clk1a3 U283 ( .A(n251), .Y(n259) );
  clk1a3 U284 ( .A(n251), .Y(n258) );
  clk1a3 U285 ( .A(n252), .Y(n257) );
  clk1a3 U286 ( .A(n252), .Y(n256) );
  clk1a3 U287 ( .A(n253), .Y(n255) );
  clk1a3 U288 ( .A(n253), .Y(n254) );
  inv1a3 U289 ( .A(waddr[2]), .Y(n481) );
  inv1a3 U290 ( .A(waddr[4]), .Y(n483) );
  inv1a3 U291 ( .A(waddr[1]), .Y(n480) );
  inv1a3 U292 ( .A(waddr[3]), .Y(n482) );
  inv1a3 U293 ( .A(waddr[0]), .Y(n479) );
  and2a3 U294 ( .A(waddr[5]), .B(n16), .Y(n18) );
  mx4e3 U295 ( .D0(\mem[40][0] ), .D1(\mem[41][0] ), .D2(\mem[42][0] ), .D3(
        \mem[43][0] ), .S0(n281), .S1(n260), .Y(n92) );
  mx4e3 U296 ( .D0(\mem[56][0] ), .D1(\mem[57][0] ), .D2(\mem[58][0] ), .D3(
        \mem[59][0] ), .S0(n281), .S1(n260), .Y(n22) );
  mx4e3 U297 ( .D0(\mem[8][0] ), .D1(\mem[9][0] ), .D2(\mem[10][0] ), .D3(
        \mem[11][0] ), .S0(n282), .S1(n261), .Y(n102) );
  mx4e3 U298 ( .D0(\mem[24][0] ), .D1(\mem[25][0] ), .D2(\mem[26][0] ), .D3(
        \mem[27][0] ), .S0(n282), .S1(n261), .Y(n97) );
  mx4e3 U299 ( .D0(\mem[40][1] ), .D1(\mem[41][1] ), .D2(\mem[42][1] ), .D3(
        \mem[43][1] ), .S0(n283), .S1(n262), .Y(n112) );
  mx4e3 U300 ( .D0(\mem[8][1] ), .D1(\mem[9][1] ), .D2(\mem[10][1] ), .D3(
        \mem[11][1] ), .S0(n284), .S1(n263), .Y(n122) );
  mx4e3 U301 ( .D0(\mem[24][1] ), .D1(\mem[25][1] ), .D2(\mem[26][1] ), .D3(
        \mem[27][1] ), .S0(n283), .S1(n262), .Y(n117) );
  mx4e3 U302 ( .D0(\mem[56][1] ), .D1(\mem[57][1] ), .D2(\mem[58][1] ), .D3(
        \mem[59][1] ), .S0(n282), .S1(n261), .Y(n107) );
  mx4e3 U303 ( .D0(\mem[40][2] ), .D1(\mem[41][2] ), .D2(\mem[42][2] ), .D3(
        \mem[43][2] ), .S0(n284), .S1(n263), .Y(n132) );
  mx4e3 U304 ( .D0(\mem[8][2] ), .D1(\mem[9][2] ), .D2(\mem[10][2] ), .D3(
        \mem[11][2] ), .S0(n285), .S1(n264), .Y(n142) );
  mx4e3 U305 ( .D0(\mem[24][2] ), .D1(\mem[25][2] ), .D2(\mem[26][2] ), .D3(
        \mem[27][2] ), .S0(n285), .S1(n264), .Y(n137) );
  mx4e3 U306 ( .D0(\mem[56][2] ), .D1(\mem[57][2] ), .D2(\mem[58][2] ), .D3(
        \mem[59][2] ), .S0(n284), .S1(n263), .Y(n127) );
  mx4e3 U307 ( .D0(\mem[40][3] ), .D1(\mem[41][3] ), .D2(\mem[42][3] ), .D3(
        \mem[43][3] ), .S0(n286), .S1(n265), .Y(n152) );
  mx4e3 U308 ( .D0(\mem[8][3] ), .D1(\mem[9][3] ), .D2(\mem[10][3] ), .D3(
        \mem[11][3] ), .S0(n286), .S1(n265), .Y(n162) );
  mx4e3 U309 ( .D0(\mem[24][3] ), .D1(\mem[25][3] ), .D2(\mem[26][3] ), .D3(
        \mem[27][3] ), .S0(n286), .S1(n265), .Y(n157) );
  mx4e3 U310 ( .D0(\mem[56][3] ), .D1(\mem[57][3] ), .D2(\mem[58][3] ), .D3(
        \mem[59][3] ), .S0(n285), .S1(n264), .Y(n147) );
  mx4e3 U311 ( .D0(\mem[40][4] ), .D1(\mem[41][4] ), .D2(\mem[42][4] ), .D3(
        \mem[43][4] ), .S0(n287), .S1(n266), .Y(n172) );
  mx4e3 U312 ( .D0(\mem[8][4] ), .D1(\mem[9][4] ), .D2(\mem[10][4] ), .D3(
        \mem[11][4] ), .S0(n288), .S1(n267), .Y(n182) );
  mx4e3 U313 ( .D0(\mem[24][4] ), .D1(\mem[25][4] ), .D2(\mem[26][4] ), .D3(
        \mem[27][4] ), .S0(n288), .S1(n267), .Y(n177) );
  mx4e3 U314 ( .D0(\mem[56][4] ), .D1(\mem[57][4] ), .D2(\mem[58][4] ), .D3(
        \mem[59][4] ), .S0(n287), .S1(n266), .Y(n167) );
  mx4e3 U315 ( .D0(\mem[40][5] ), .D1(\mem[41][5] ), .D2(\mem[42][5] ), .D3(
        \mem[43][5] ), .S0(n289), .S1(n268), .Y(n192) );
  mx4e3 U316 ( .D0(\mem[8][5] ), .D1(\mem[9][5] ), .D2(\mem[10][5] ), .D3(
        \mem[11][5] ), .S0(n289), .S1(n268), .Y(n202) );
  mx4e3 U317 ( .D0(\mem[24][5] ), .D1(\mem[25][5] ), .D2(\mem[26][5] ), .D3(
        \mem[27][5] ), .S0(n289), .S1(n268), .Y(n197) );
  mx4e3 U318 ( .D0(\mem[56][5] ), .D1(\mem[57][5] ), .D2(\mem[58][5] ), .D3(
        \mem[59][5] ), .S0(n288), .S1(n267), .Y(n187) );
  mx4e3 U319 ( .D0(\mem[40][6] ), .D1(\mem[41][6] ), .D2(\mem[42][6] ), .D3(
        \mem[43][6] ), .S0(n290), .S1(n269), .Y(n212) );
  mx4e3 U320 ( .D0(\mem[8][6] ), .D1(\mem[9][6] ), .D2(\mem[10][6] ), .D3(
        \mem[11][6] ), .S0(n291), .S1(n270), .Y(n222) );
  mx4e3 U321 ( .D0(\mem[24][6] ), .D1(\mem[25][6] ), .D2(\mem[26][6] ), .D3(
        \mem[27][6] ), .S0(n290), .S1(n269), .Y(n217) );
  mx4e3 U322 ( .D0(\mem[56][6] ), .D1(\mem[57][6] ), .D2(\mem[58][6] ), .D3(
        \mem[59][6] ), .S0(n290), .S1(n269), .Y(n207) );
  mx4e3 U323 ( .D0(\mem[40][7] ), .D1(\mem[41][7] ), .D2(\mem[42][7] ), .D3(
        \mem[43][7] ), .S0(n292), .S1(n271), .Y(n232) );
  mx4e3 U324 ( .D0(\mem[8][7] ), .D1(\mem[9][7] ), .D2(\mem[10][7] ), .D3(
        \mem[11][7] ), .S0(n292), .S1(n271), .Y(n242) );
  mx4e3 U325 ( .D0(\mem[24][7] ), .D1(\mem[25][7] ), .D2(\mem[26][7] ), .D3(
        \mem[27][7] ), .S0(n292), .S1(n271), .Y(n237) );
  mx4e3 U326 ( .D0(\mem[56][7] ), .D1(\mem[57][7] ), .D2(\mem[58][7] ), .D3(
        \mem[59][7] ), .S0(n291), .S1(n270), .Y(n227) );
  mx4e3 U327 ( .D0(\mem[4][0] ), .D1(\mem[5][0] ), .D2(\mem[6][0] ), .D3(
        \mem[7][0] ), .S0(n282), .S1(n261), .Y(n103) );
  mx4e3 U328 ( .D0(\mem[0][0] ), .D1(\mem[1][0] ), .D2(\mem[2][0] ), .D3(
        \mem[3][0] ), .S0(n282), .S1(n261), .Y(n101) );
  mx4e3 U329 ( .D0(\mem[20][0] ), .D1(\mem[21][0] ), .D2(\mem[22][0] ), .D3(
        \mem[23][0] ), .S0(n282), .S1(n261), .Y(n98) );
  mx4e3 U330 ( .D0(\mem[16][0] ), .D1(\mem[17][0] ), .D2(\mem[18][0] ), .D3(
        \mem[19][0] ), .S0(n282), .S1(n261), .Y(n96) );
  mx4e3 U331 ( .D0(\mem[52][0] ), .D1(\mem[53][0] ), .D2(\mem[54][0] ), .D3(
        \mem[55][0] ), .S0(n281), .S1(n260), .Y(n23) );
  mx4e3 U332 ( .D0(\mem[48][0] ), .D1(\mem[49][0] ), .D2(\mem[50][0] ), .D3(
        \mem[51][0] ), .S0(n281), .S1(n260), .Y(n11) );
  mx4e3 U333 ( .D0(\mem[4][1] ), .D1(\mem[5][1] ), .D2(\mem[6][1] ), .D3(
        \mem[7][1] ), .S0(n284), .S1(n263), .Y(n123) );
  mx4e3 U334 ( .D0(\mem[0][1] ), .D1(\mem[1][1] ), .D2(\mem[2][1] ), .D3(
        \mem[3][1] ), .S0(n284), .S1(n263), .Y(n121) );
  mx4e3 U335 ( .D0(\mem[20][1] ), .D1(\mem[21][1] ), .D2(\mem[22][1] ), .D3(
        \mem[23][1] ), .S0(n283), .S1(n262), .Y(n118) );
  mx4e3 U336 ( .D0(\mem[16][1] ), .D1(\mem[17][1] ), .D2(\mem[18][1] ), .D3(
        \mem[19][1] ), .S0(n283), .S1(n262), .Y(n116) );
  mx4e3 U337 ( .D0(\mem[52][1] ), .D1(\mem[53][1] ), .D2(\mem[54][1] ), .D3(
        \mem[55][1] ), .S0(n283), .S1(n262), .Y(n108) );
  mx4e3 U338 ( .D0(\mem[48][1] ), .D1(\mem[49][1] ), .D2(\mem[50][1] ), .D3(
        \mem[51][1] ), .S0(n283), .S1(n262), .Y(n106) );
  mx4e3 U339 ( .D0(\mem[4][2] ), .D1(\mem[5][2] ), .D2(\mem[6][2] ), .D3(
        \mem[7][2] ), .S0(n285), .S1(n264), .Y(n143) );
  mx4e3 U340 ( .D0(\mem[0][2] ), .D1(\mem[1][2] ), .D2(\mem[2][2] ), .D3(
        \mem[3][2] ), .S0(n285), .S1(n264), .Y(n141) );
  mx4e3 U341 ( .D0(\mem[20][2] ), .D1(\mem[21][2] ), .D2(\mem[22][2] ), .D3(
        \mem[23][2] ), .S0(n285), .S1(n264), .Y(n138) );
  mx4e3 U342 ( .D0(\mem[16][2] ), .D1(\mem[17][2] ), .D2(\mem[18][2] ), .D3(
        \mem[19][2] ), .S0(n285), .S1(n264), .Y(n136) );
  mx4e3 U343 ( .D0(\mem[52][2] ), .D1(\mem[53][2] ), .D2(\mem[54][2] ), .D3(
        \mem[55][2] ), .S0(n284), .S1(n263), .Y(n128) );
  mx4e3 U344 ( .D0(\mem[48][2] ), .D1(\mem[49][2] ), .D2(\mem[50][2] ), .D3(
        \mem[51][2] ), .S0(n284), .S1(n263), .Y(n126) );
  mx4e3 U345 ( .D0(\mem[4][3] ), .D1(\mem[5][3] ), .D2(\mem[6][3] ), .D3(
        \mem[7][3] ), .S0(n287), .S1(n266), .Y(n163) );
  mx4e3 U346 ( .D0(\mem[0][3] ), .D1(\mem[1][3] ), .D2(\mem[2][3] ), .D3(
        \mem[3][3] ), .S0(n287), .S1(n266), .Y(n161) );
  mx4e3 U347 ( .D0(\mem[20][3] ), .D1(\mem[21][3] ), .D2(\mem[22][3] ), .D3(
        \mem[23][3] ), .S0(n286), .S1(n265), .Y(n158) );
  mx4e3 U348 ( .D0(\mem[16][3] ), .D1(\mem[17][3] ), .D2(\mem[18][3] ), .D3(
        \mem[19][3] ), .S0(n286), .S1(n265), .Y(n156) );
  mx4e3 U349 ( .D0(\mem[52][3] ), .D1(\mem[53][3] ), .D2(\mem[54][3] ), .D3(
        \mem[55][3] ), .S0(n285), .S1(n264), .Y(n148) );
  mx4e3 U350 ( .D0(\mem[48][3] ), .D1(\mem[49][3] ), .D2(\mem[50][3] ), .D3(
        \mem[51][3] ), .S0(n286), .S1(n265), .Y(n146) );
  mx4e3 U351 ( .D0(\mem[4][4] ), .D1(\mem[5][4] ), .D2(\mem[6][4] ), .D3(
        \mem[7][4] ), .S0(n288), .S1(n267), .Y(n183) );
  mx4e3 U352 ( .D0(\mem[0][4] ), .D1(\mem[1][4] ), .D2(\mem[2][4] ), .D3(
        \mem[3][4] ), .S0(n288), .S1(n267), .Y(n181) );
  mx4e3 U353 ( .D0(\mem[20][4] ), .D1(\mem[21][4] ), .D2(\mem[22][4] ), .D3(
        \mem[23][4] ), .S0(n288), .S1(n267), .Y(n178) );
  mx4e3 U354 ( .D0(\mem[16][4] ), .D1(\mem[17][4] ), .D2(\mem[18][4] ), .D3(
        \mem[19][4] ), .S0(n288), .S1(n267), .Y(n176) );
  mx4e3 U355 ( .D0(\mem[52][4] ), .D1(\mem[53][4] ), .D2(\mem[54][4] ), .D3(
        \mem[55][4] ), .S0(n287), .S1(n266), .Y(n168) );
  mx4e3 U356 ( .D0(\mem[48][4] ), .D1(\mem[49][4] ), .D2(\mem[50][4] ), .D3(
        \mem[51][4] ), .S0(n287), .S1(n266), .Y(n166) );
  mx4e3 U357 ( .D0(\mem[4][5] ), .D1(\mem[5][5] ), .D2(\mem[6][5] ), .D3(
        \mem[7][5] ), .S0(n289), .S1(n268), .Y(n203) );
  mx4e3 U358 ( .D0(\mem[0][5] ), .D1(\mem[1][5] ), .D2(\mem[2][5] ), .D3(
        \mem[3][5] ), .S0(n290), .S1(n269), .Y(n201) );
  mx4e3 U359 ( .D0(\mem[20][5] ), .D1(\mem[21][5] ), .D2(\mem[22][5] ), .D3(
        \mem[23][5] ), .S0(n289), .S1(n268), .Y(n198) );
  mx4e3 U360 ( .D0(\mem[16][5] ), .D1(\mem[17][5] ), .D2(\mem[18][5] ), .D3(
        \mem[19][5] ), .S0(n289), .S1(n268), .Y(n196) );
  mx4e3 U361 ( .D0(\mem[52][5] ), .D1(\mem[53][5] ), .D2(\mem[54][5] ), .D3(
        \mem[55][5] ), .S0(n288), .S1(n267), .Y(n188) );
  mx4e3 U362 ( .D0(\mem[48][5] ), .D1(\mem[49][5] ), .D2(\mem[50][5] ), .D3(
        \mem[51][5] ), .S0(n288), .S1(n267), .Y(n186) );
  mx4e3 U363 ( .D0(\mem[4][6] ), .D1(\mem[5][6] ), .D2(\mem[6][6] ), .D3(
        \mem[7][6] ), .S0(n291), .S1(n270), .Y(n223) );
  mx4e3 U364 ( .D0(\mem[0][6] ), .D1(\mem[1][6] ), .D2(\mem[2][6] ), .D3(
        \mem[3][6] ), .S0(n291), .S1(n270), .Y(n221) );
  mx4e3 U365 ( .D0(\mem[20][6] ), .D1(\mem[21][6] ), .D2(\mem[22][6] ), .D3(
        \mem[23][6] ), .S0(n291), .S1(n270), .Y(n218) );
  mx4e3 U366 ( .D0(\mem[16][6] ), .D1(\mem[17][6] ), .D2(\mem[18][6] ), .D3(
        \mem[19][6] ), .S0(n291), .S1(n270), .Y(n216) );
  mx4e3 U367 ( .D0(\mem[52][6] ), .D1(\mem[53][6] ), .D2(\mem[54][6] ), .D3(
        \mem[55][6] ), .S0(n290), .S1(n269), .Y(n208) );
  mx4e3 U368 ( .D0(\mem[48][6] ), .D1(\mem[49][6] ), .D2(\mem[50][6] ), .D3(
        \mem[51][6] ), .S0(n290), .S1(n269), .Y(n206) );
  mx4e3 U369 ( .D0(\mem[4][7] ), .D1(\mem[5][7] ), .D2(\mem[6][7] ), .D3(
        \mem[7][7] ), .S0(n292), .S1(n271), .Y(n243) );
  mx4e3 U370 ( .D0(\mem[0][7] ), .D1(\mem[1][7] ), .D2(\mem[2][7] ), .D3(
        \mem[3][7] ), .S0(n292), .S1(n271), .Y(n241) );
  mx4e3 U371 ( .D0(\mem[20][7] ), .D1(\mem[21][7] ), .D2(\mem[22][7] ), .D3(
        \mem[23][7] ), .S0(n292), .S1(n271), .Y(n238) );
  mx4e3 U372 ( .D0(\mem[16][7] ), .D1(\mem[17][7] ), .D2(\mem[18][7] ), .D3(
        \mem[19][7] ), .S0(n292), .S1(n271), .Y(n236) );
  mx4e3 U373 ( .D0(\mem[52][7] ), .D1(\mem[53][7] ), .D2(\mem[54][7] ), .D3(
        \mem[55][7] ), .S0(n291), .S1(n270), .Y(n228) );
  mx4e3 U374 ( .D0(\mem[48][7] ), .D1(\mem[49][7] ), .D2(\mem[50][7] ), .D3(
        \mem[51][7] ), .S0(n291), .S1(n270), .Y(n226) );
  mx4e3 U375 ( .D0(n91), .D1(n92), .D2(n93), .D3(n94), .S0(n245), .S1(n248), 
        .Y(n90) );
  mx4e3 U376 ( .D0(\mem[44][0] ), .D1(\mem[45][0] ), .D2(\mem[46][0] ), .D3(
        \mem[47][0] ), .S0(n281), .S1(n260), .Y(n94) );
  mx4e3 U377 ( .D0(\mem[32][0] ), .D1(\mem[33][0] ), .D2(\mem[34][0] ), .D3(
        \mem[35][0] ), .S0(n282), .S1(n261), .Y(n91) );
  mx4e3 U378 ( .D0(\mem[36][0] ), .D1(\mem[37][0] ), .D2(\mem[38][0] ), .D3(
        \mem[39][0] ), .S0(n281), .S1(n260), .Y(n93) );
  mx4e3 U379 ( .D0(n111), .D1(n112), .D2(n113), .D3(n114), .S0(n245), .S1(n248), .Y(n110) );
  mx4e3 U380 ( .D0(\mem[44][1] ), .D1(\mem[45][1] ), .D2(\mem[46][1] ), .D3(
        \mem[47][1] ), .S0(n283), .S1(n262), .Y(n114) );
  mx4e3 U381 ( .D0(\mem[32][1] ), .D1(\mem[33][1] ), .D2(\mem[34][1] ), .D3(
        \mem[35][1] ), .S0(n283), .S1(n262), .Y(n111) );
  mx4e3 U382 ( .D0(\mem[36][1] ), .D1(\mem[37][1] ), .D2(\mem[38][1] ), .D3(
        \mem[39][1] ), .S0(n283), .S1(n262), .Y(n113) );
  mx4e3 U383 ( .D0(n131), .D1(n132), .D2(n133), .D3(n134), .S0(n245), .S1(n248), .Y(n130) );
  mx4e3 U384 ( .D0(\mem[44][2] ), .D1(\mem[45][2] ), .D2(\mem[46][2] ), .D3(
        \mem[47][2] ), .S0(n284), .S1(n263), .Y(n134) );
  mx4e3 U385 ( .D0(\mem[32][2] ), .D1(\mem[33][2] ), .D2(\mem[34][2] ), .D3(
        \mem[35][2] ), .S0(n284), .S1(n263), .Y(n131) );
  mx4e3 U386 ( .D0(\mem[36][2] ), .D1(\mem[37][2] ), .D2(\mem[38][2] ), .D3(
        \mem[39][2] ), .S0(n284), .S1(n263), .Y(n133) );
  mx4e3 U387 ( .D0(n151), .D1(n152), .D2(n153), .D3(n154), .S0(n246), .S1(n249), .Y(n150) );
  mx4e3 U388 ( .D0(\mem[44][3] ), .D1(\mem[45][3] ), .D2(\mem[46][3] ), .D3(
        \mem[47][3] ), .S0(n286), .S1(n265), .Y(n154) );
  mx4e3 U389 ( .D0(\mem[32][3] ), .D1(\mem[33][3] ), .D2(\mem[34][3] ), .D3(
        \mem[35][3] ), .S0(n286), .S1(n265), .Y(n151) );
  mx4e3 U390 ( .D0(\mem[36][3] ), .D1(\mem[37][3] ), .D2(\mem[38][3] ), .D3(
        \mem[39][3] ), .S0(n286), .S1(n265), .Y(n153) );
  mx4e3 U391 ( .D0(n171), .D1(n172), .D2(n173), .D3(n174), .S0(n246), .S1(n249), .Y(n170) );
  mx4e3 U392 ( .D0(\mem[44][4] ), .D1(\mem[45][4] ), .D2(\mem[46][4] ), .D3(
        \mem[47][4] ), .S0(n287), .S1(n266), .Y(n174) );
  mx4e3 U393 ( .D0(\mem[32][4] ), .D1(\mem[33][4] ), .D2(\mem[34][4] ), .D3(
        \mem[35][4] ), .S0(n287), .S1(n266), .Y(n171) );
  mx4e3 U394 ( .D0(\mem[36][4] ), .D1(\mem[37][4] ), .D2(\mem[38][4] ), .D3(
        \mem[39][4] ), .S0(n287), .S1(n266), .Y(n173) );
  mx4e3 U395 ( .D0(n191), .D1(n192), .D2(n193), .D3(n194), .S0(n247), .S1(n250), .Y(n190) );
  mx4e3 U396 ( .D0(\mem[44][5] ), .D1(\mem[45][5] ), .D2(\mem[46][5] ), .D3(
        \mem[47][5] ), .S0(n289), .S1(n268), .Y(n194) );
  mx4e3 U397 ( .D0(\mem[32][5] ), .D1(\mem[33][5] ), .D2(\mem[34][5] ), .D3(
        \mem[35][5] ), .S0(n289), .S1(n268), .Y(n191) );
  mx4e3 U398 ( .D0(\mem[36][5] ), .D1(\mem[37][5] ), .D2(\mem[38][5] ), .D3(
        \mem[39][5] ), .S0(n289), .S1(n268), .Y(n193) );
  mx4e3 U399 ( .D0(n211), .D1(n212), .D2(n213), .D3(n214), .S0(n247), .S1(n250), .Y(n210) );
  mx4e3 U400 ( .D0(\mem[44][6] ), .D1(\mem[45][6] ), .D2(\mem[46][6] ), .D3(
        \mem[47][6] ), .S0(n290), .S1(n269), .Y(n214) );
  mx4e3 U401 ( .D0(\mem[32][6] ), .D1(\mem[33][6] ), .D2(\mem[34][6] ), .D3(
        \mem[35][6] ), .S0(n290), .S1(n269), .Y(n211) );
  mx4e3 U402 ( .D0(\mem[36][6] ), .D1(\mem[37][6] ), .D2(\mem[38][6] ), .D3(
        \mem[39][6] ), .S0(n290), .S1(n269), .Y(n213) );
  mx4e3 U403 ( .D0(n231), .D1(n232), .D2(n233), .D3(n234), .S0(n247), .S1(n250), .Y(n230) );
  mx4e3 U404 ( .D0(\mem[44][7] ), .D1(\mem[45][7] ), .D2(\mem[46][7] ), .D3(
        \mem[47][7] ), .S0(n291), .S1(n270), .Y(n234) );
  mx4e3 U405 ( .D0(\mem[32][7] ), .D1(\mem[33][7] ), .D2(\mem[34][7] ), .D3(
        \mem[35][7] ), .S0(n292), .S1(n271), .Y(n231) );
  mx4e3 U406 ( .D0(\mem[36][7] ), .D1(\mem[37][7] ), .D2(\mem[38][7] ), .D3(
        \mem[39][7] ), .S0(n292), .S1(n271), .Y(n233) );
  mx4e3 U407 ( .D0(\mem[12][0] ), .D1(\mem[13][0] ), .D2(\mem[14][0] ), .D3(
        \mem[15][0] ), .S0(n282), .S1(n261), .Y(n104) );
  mx4e3 U408 ( .D0(\mem[28][0] ), .D1(\mem[29][0] ), .D2(\mem[30][0] ), .D3(
        \mem[31][0] ), .S0(n282), .S1(n261), .Y(n99) );
  mx4e3 U409 ( .D0(\mem[60][0] ), .D1(\mem[61][0] ), .D2(\mem[62][0] ), .D3(
        \mem[63][0] ), .S0(n281), .S1(n260), .Y(n24) );
  mx4e3 U410 ( .D0(\mem[12][1] ), .D1(\mem[13][1] ), .D2(\mem[14][1] ), .D3(
        \mem[15][1] ), .S0(n283), .S1(n262), .Y(n124) );
  mx4e3 U411 ( .D0(\mem[28][1] ), .D1(\mem[29][1] ), .D2(\mem[30][1] ), .D3(
        \mem[31][1] ), .S0(n283), .S1(n262), .Y(n119) );
  mx4e3 U412 ( .D0(\mem[60][1] ), .D1(\mem[61][1] ), .D2(\mem[62][1] ), .D3(
        \mem[63][1] ), .S0(n282), .S1(n261), .Y(n109) );
  mx4e3 U413 ( .D0(\mem[12][2] ), .D1(\mem[13][2] ), .D2(\mem[14][2] ), .D3(
        \mem[15][2] ), .S0(n285), .S1(n264), .Y(n144) );
  mx4e3 U414 ( .D0(\mem[28][2] ), .D1(\mem[29][2] ), .D2(\mem[30][2] ), .D3(
        \mem[31][2] ), .S0(n285), .S1(n264), .Y(n139) );
  mx4e3 U415 ( .D0(\mem[60][2] ), .D1(\mem[61][2] ), .D2(\mem[62][2] ), .D3(
        \mem[63][2] ), .S0(n284), .S1(n263), .Y(n129) );
  mx4e3 U416 ( .D0(\mem[12][3] ), .D1(\mem[13][3] ), .D2(\mem[14][3] ), .D3(
        \mem[15][3] ), .S0(n286), .S1(n265), .Y(n164) );
  mx4e3 U417 ( .D0(\mem[28][3] ), .D1(\mem[29][3] ), .D2(\mem[30][3] ), .D3(
        \mem[31][3] ), .S0(n286), .S1(n265), .Y(n159) );
  mx4e3 U418 ( .D0(\mem[60][3] ), .D1(\mem[61][3] ), .D2(\mem[62][3] ), .D3(
        \mem[63][3] ), .S0(n285), .S1(n264), .Y(n149) );
  mx4e3 U419 ( .D0(\mem[12][4] ), .D1(\mem[13][4] ), .D2(\mem[14][4] ), .D3(
        \mem[15][4] ), .S0(n288), .S1(n267), .Y(n184) );
  mx4e3 U420 ( .D0(\mem[28][4] ), .D1(\mem[29][4] ), .D2(\mem[30][4] ), .D3(
        \mem[31][4] ), .S0(n287), .S1(n266), .Y(n179) );
  mx4e3 U421 ( .D0(\mem[60][4] ), .D1(\mem[61][4] ), .D2(\mem[62][4] ), .D3(
        \mem[63][4] ), .S0(n287), .S1(n266), .Y(n169) );
  mx4e3 U422 ( .D0(\mem[12][5] ), .D1(\mem[13][5] ), .D2(\mem[14][5] ), .D3(
        \mem[15][5] ), .S0(n289), .S1(n268), .Y(n204) );
  mx4e3 U423 ( .D0(\mem[28][5] ), .D1(\mem[29][5] ), .D2(\mem[30][5] ), .D3(
        \mem[31][5] ), .S0(n289), .S1(n268), .Y(n199) );
  mx4e3 U424 ( .D0(\mem[60][5] ), .D1(\mem[61][5] ), .D2(\mem[62][5] ), .D3(
        \mem[63][5] ), .S0(n288), .S1(n267), .Y(n189) );
  mx4e3 U425 ( .D0(\mem[12][6] ), .D1(\mem[13][6] ), .D2(\mem[14][6] ), .D3(
        \mem[15][6] ), .S0(n291), .S1(n270), .Y(n224) );
  mx4e3 U426 ( .D0(\mem[28][6] ), .D1(\mem[29][6] ), .D2(\mem[30][6] ), .D3(
        \mem[31][6] ), .S0(n290), .S1(n269), .Y(n219) );
  mx4e3 U427 ( .D0(\mem[60][6] ), .D1(\mem[61][6] ), .D2(\mem[62][6] ), .D3(
        \mem[63][6] ), .S0(n290), .S1(n269), .Y(n209) );
  mx4e3 U428 ( .D0(\mem[12][7] ), .D1(\mem[13][7] ), .D2(\mem[14][7] ), .D3(
        \mem[15][7] ), .S0(n292), .S1(n271), .Y(n244) );
  mx4e3 U429 ( .D0(\mem[28][7] ), .D1(\mem[29][7] ), .D2(\mem[30][7] ), .D3(
        \mem[31][7] ), .S0(n292), .S1(n271), .Y(n239) );
  mx4e3 U430 ( .D0(\mem[60][7] ), .D1(\mem[61][7] ), .D2(\mem[62][7] ), .D3(
        \mem[63][7] ), .S0(n291), .S1(n270), .Y(n229) );
  clk1a6 U431 ( .A(N19), .Y(n249) );
  clk1a6 U432 ( .A(N19), .Y(n250) );
  mx4a3 U433 ( .D0(n100), .D1(n90), .D2(n95), .D3(n10), .S0(N22), .S1(N21), 
        .Y(N31) );
  mx4e3 U434 ( .D0(n11), .D1(n22), .D2(n23), .D3(n24), .S0(n245), .S1(n248), 
        .Y(n10) );
  mx4e3 U435 ( .D0(n96), .D1(n97), .D2(n98), .D3(n99), .S0(n245), .S1(n248), 
        .Y(n95) );
  mx4e3 U436 ( .D0(n101), .D1(n102), .D2(n103), .D3(n104), .S0(n245), .S1(n248), .Y(n100) );
  mx4a3 U437 ( .D0(n120), .D1(n110), .D2(n115), .D3(n105), .S0(N22), .S1(N21), 
        .Y(N30) );
  mx4e3 U438 ( .D0(n106), .D1(n107), .D2(n108), .D3(n109), .S0(n245), .S1(n248), .Y(n105) );
  mx4e3 U439 ( .D0(n116), .D1(n117), .D2(n118), .D3(n119), .S0(n245), .S1(n248), .Y(n115) );
  mx4e3 U440 ( .D0(n121), .D1(n122), .D2(n123), .D3(n124), .S0(n245), .S1(n248), .Y(n120) );
  mx4a3 U441 ( .D0(n140), .D1(n130), .D2(n135), .D3(n125), .S0(N22), .S1(N21), 
        .Y(N29) );
  mx4e3 U442 ( .D0(n126), .D1(n127), .D2(n128), .D3(n129), .S0(n245), .S1(n248), .Y(n125) );
  mx4e3 U443 ( .D0(n136), .D1(n137), .D2(n138), .D3(n139), .S0(n246), .S1(n249), .Y(n135) );
  mx4e3 U444 ( .D0(n141), .D1(n142), .D2(n143), .D3(n144), .S0(n246), .S1(n249), .Y(n140) );
  mx4a3 U445 ( .D0(n160), .D1(n150), .D2(n155), .D3(n145), .S0(N22), .S1(N21), 
        .Y(N28) );
  mx4e3 U446 ( .D0(n146), .D1(n147), .D2(n148), .D3(n149), .S0(n246), .S1(n249), .Y(n145) );
  mx4e3 U447 ( .D0(n156), .D1(n157), .D2(n158), .D3(n159), .S0(n246), .S1(n249), .Y(n155) );
  mx4e3 U448 ( .D0(n161), .D1(n162), .D2(n163), .D3(n164), .S0(n246), .S1(n249), .Y(n160) );
  mx4a3 U449 ( .D0(n180), .D1(n170), .D2(n175), .D3(n165), .S0(N22), .S1(N21), 
        .Y(N27) );
  mx4e3 U450 ( .D0(n166), .D1(n167), .D2(n168), .D3(n169), .S0(n246), .S1(n249), .Y(n165) );
  mx4e3 U451 ( .D0(n176), .D1(n177), .D2(n178), .D3(n179), .S0(n246), .S1(n249), .Y(n175) );
  mx4e3 U452 ( .D0(n181), .D1(n182), .D2(n183), .D3(n184), .S0(n246), .S1(n249), .Y(n180) );
  mx4a3 U453 ( .D0(n200), .D1(n190), .D2(n195), .D3(n185), .S0(N22), .S1(N21), 
        .Y(N26) );
  mx4e3 U454 ( .D0(n186), .D1(n187), .D2(n188), .D3(n189), .S0(n246), .S1(n249), .Y(n185) );
  mx4e3 U455 ( .D0(n196), .D1(n197), .D2(n198), .D3(n199), .S0(n247), .S1(n250), .Y(n195) );
  mx4e3 U456 ( .D0(n201), .D1(n202), .D2(n203), .D3(n204), .S0(n247), .S1(n250), .Y(n200) );
  mx4a3 U457 ( .D0(n220), .D1(n210), .D2(n215), .D3(n205), .S0(N22), .S1(N21), 
        .Y(N25) );
  mx4e3 U458 ( .D0(n206), .D1(n207), .D2(n208), .D3(n209), .S0(n247), .S1(n250), .Y(n205) );
  mx4e3 U459 ( .D0(n216), .D1(n217), .D2(n218), .D3(n219), .S0(n247), .S1(n250), .Y(n215) );
  mx4e3 U460 ( .D0(n221), .D1(n222), .D2(n223), .D3(n224), .S0(n247), .S1(n250), .Y(n220) );
  mx4a3 U461 ( .D0(n240), .D1(n230), .D2(n235), .D3(n225), .S0(N22), .S1(N21), 
        .Y(N24) );
  mx4e3 U462 ( .D0(n226), .D1(n227), .D2(n228), .D3(n229), .S0(n247), .S1(n250), .Y(n225) );
  mx4e3 U463 ( .D0(n236), .D1(n237), .D2(n238), .D3(n239), .S0(n247), .S1(n250), .Y(n235) );
  mx4e3 U464 ( .D0(n241), .D1(n242), .D2(n243), .D3(n244), .S0(n247), .S1(n250), .Y(n240) );
  clk1a6 U465 ( .A(N19), .Y(n248) );
  clk1a3 U466 ( .A(di[0]), .Y(n299) );
  clk1a3 U467 ( .A(di[1]), .Y(n308) );
  clk1a3 U468 ( .A(di[2]), .Y(n317) );
  clk1a3 U469 ( .A(di[3]), .Y(n326) );
  clk1a3 U470 ( .A(di[4]), .Y(n335) );
  clk1a3 U471 ( .A(di[0]), .Y(n300) );
  clk1a3 U472 ( .A(di[1]), .Y(n309) );
  clk1a3 U473 ( .A(di[2]), .Y(n318) );
  clk1a3 U474 ( .A(di[3]), .Y(n327) );
  clk1a3 U475 ( .A(di[4]), .Y(n336) );
  clk1a3 U476 ( .A(di[0]), .Y(n301) );
  clk1a3 U477 ( .A(di[1]), .Y(n310) );
  clk1a3 U478 ( .A(di[2]), .Y(n319) );
  clk1a3 U479 ( .A(di[3]), .Y(n328) );
  clk1a3 U480 ( .A(di[4]), .Y(n337) );
  clk1a3 U481 ( .A(di[5]), .Y(n344) );
  clk1a3 U482 ( .A(di[6]), .Y(n353) );
  clk1a3 U483 ( .A(di[7]), .Y(n362) );
  clk1a3 U484 ( .A(di[5]), .Y(n345) );
  clk1a3 U485 ( .A(di[6]), .Y(n354) );
  clk1a3 U486 ( .A(di[7]), .Y(n363) );
  clk1a3 U487 ( .A(di[5]), .Y(n346) );
  clk1a3 U488 ( .A(di[6]), .Y(n355) );
  clk1a3 U489 ( .A(di[7]), .Y(n364) );
  clk1a3 U490 ( .A(N18), .Y(n251) );
  clk1a3 U491 ( .A(N18), .Y(n252) );
  clk1a3 U492 ( .A(N18), .Y(n253) );
endmodule


module generic_fifo_sc_a_dw8_aw6_n0_DW01_inc_0 ( A, SUM );
  input [6:0] A;
  output [6:0] SUM;

  wire   [6:2] carry;

  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[6]), .B(A[6]), .Y(SUM[6]) );
endmodule


module generic_fifo_sc_a_dw8_aw6_n0 ( clk, rst, clr, din, we, dout, re, full, 
        empty, full_r, empty_r, full_n, empty_n, full_n_r, empty_n_r, level );
  input [7:0] din;
  output [7:0] dout;
  output [1:0] level;
  input clk, rst, clr, we, re;
  output full, empty, full_r, empty_r, full_n, empty_n, full_n_r, empty_n_r;
  wire   gb, gb2, N59, N64, N65, N66, N67, N68, N69, N71, N72, N73, N74, N75,
         N76, N77, N95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
         n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
         n117, n118, n119, \add_293_S2/carry[2] , \add_293_S2/carry[3] ,
         \add_293_S2/carry[4] , \add_293_S2/carry[5] , \add_293_S2/carry[6] ,
         \add_216/carry[5] , \add_216/carry[4] , \add_216/carry[3] ,
         \add_225/carry[5] , \add_225/carry[4] , \add_225/carry[3] ,
         \add_225/carry[2] , \add_215/carry[5] , \add_215/carry[4] ,
         \add_215/carry[3] , \add_215/carry[2] , n1, n2, n3, n4, n5, n6, n7,
         n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
         n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
         n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
         n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
         n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
         n78, n79, n80, n81, n82, n83, n84, n85;
  wire   [5:0] rp;
  wire   [5:0] wp;
  wire   [5:0] wp_pl1;
  wire   [5:0] wp_pl2;
  wire   [5:0] rp_pl1;
  wire   [6:0] cnt;
  tri   [7:0] dout;
  assign empty_n_r = 1'b1;
  assign empty_n = 1'b0;

  fdf1a6 \wp_reg[0]  ( .D(n119), .CLK(n6), .Q(wp_pl2[0]) );
  fdf1a6 \wp_reg[2]  ( .D(n117), .CLK(n6), .Q(wp[2]) );
  fdf1a6 \wp_reg[3]  ( .D(n116), .CLK(n6), .Q(wp[3]) );
  fdf1a6 \wp_reg[4]  ( .D(n115), .CLK(n6), .Q(wp[4]) );
  fdf1a6 \rp_reg[1]  ( .D(n112), .CLK(n6), .Q(rp[1]) );
  fdf1a6 \rp_reg[2]  ( .D(n111), .CLK(n6), .Q(rp[2]) );
  fdf1a6 \rp_reg[4]  ( .D(n109), .CLK(n6), .Q(rp[4]) );
  fdf1a6 \rp_reg[5]  ( .D(n108), .CLK(n6), .Q(rp[5]) );
  generic_dpram_aw6_dw8 u0 ( .rclk(n6), .rrst(n5), .rce(1'b1), .oe(1'b1), 
        .raddr({rp[5:1], n2}), .do(dout), .wclk(n6), .wrst(n5), .wce(1'b1), 
        .we(we), .waddr({wp[5:1], wp_pl2[0]}), .di(din) );
  generic_fifo_sc_a_dw8_aw6_n0_DW01_inc_0 add_295_S2 ( .A(cnt), .SUM({N77, N76, 
        N75, N74, N73, N72, N71}) );
  ha1a2 \add_225/U1_1_1  ( .A(rp[1]), .B(n2), .CO(\add_225/carry[2] ), .S(
        rp_pl1[1]) );
  ha1a2 \add_225/U1_1_2  ( .A(rp[2]), .B(\add_225/carry[2] ), .CO(
        \add_225/carry[3] ), .S(rp_pl1[2]) );
  ha1a2 \add_225/U1_1_3  ( .A(rp[3]), .B(\add_225/carry[3] ), .CO(
        \add_225/carry[4] ), .S(rp_pl1[3]) );
  ha1a2 \add_225/U1_1_4  ( .A(rp[4]), .B(\add_225/carry[4] ), .CO(
        \add_225/carry[5] ), .S(rp_pl1[4]) );
  ha1a2 \add_215/U1_1_1  ( .A(wp[1]), .B(wp_pl2[0]), .CO(\add_215/carry[2] ), 
        .S(wp_pl1[1]) );
  ha1a2 \add_215/U1_1_2  ( .A(wp[2]), .B(\add_215/carry[2] ), .CO(
        \add_215/carry[3] ), .S(wp_pl1[2]) );
  ha1a2 \add_215/U1_1_3  ( .A(wp[3]), .B(\add_215/carry[3] ), .CO(
        \add_215/carry[4] ), .S(wp_pl1[3]) );
  ha1a2 \add_215/U1_1_4  ( .A(wp[4]), .B(\add_215/carry[4] ), .CO(
        \add_215/carry[5] ), .S(wp_pl1[4]) );
  fdf1a3 full_r_reg ( .D(n105), .CLK(n6), .Q(full_r) );
  fdf1a3 full_n_r_reg ( .D(n96), .CLK(n6), .Q(full_n_r) );
  fdf1a3 empty_r_reg ( .D(n104), .CLK(n6), .Q(empty_r) );
  fdf1a3 \rp_reg[3]  ( .D(n110), .CLK(n6), .Q(rp[3]) );
  fdf1a3 gb_reg ( .D(n107), .CLK(n6), .Q(gb) );
  fdf1a3 gb2_reg ( .D(n106), .CLK(n6), .Q(gb2) );
  fdf1a3 \rp_reg[0]  ( .D(n113), .CLK(n6), .Q(rp[0]) );
  fdf1a3 \cnt_reg[6]  ( .D(n97), .CLK(n6), .Q(cnt[6]) );
  fdf1a3 \cnt_reg[1]  ( .D(n102), .CLK(n6), .Q(cnt[1]) );
  fdf1a3 \cnt_reg[2]  ( .D(n101), .CLK(n6), .Q(cnt[2]) );
  fdf1a3 \cnt_reg[3]  ( .D(n100), .CLK(n6), .Q(cnt[3]) );
  fdf1a3 \cnt_reg[4]  ( .D(n99), .CLK(n6), .Q(cnt[4]) );
  fdf1a3 \cnt_reg[5]  ( .D(n98), .CLK(n6), .Q(cnt[5]) );
  fdf1a9 \wp_reg[1]  ( .D(n118), .CLK(n6), .Q(wp[1]) );
  fdf1a3 \cnt_reg[0]  ( .D(n103), .CLK(n6), .Q(cnt[0]) );
  fdf1a3 \wp_reg[5]  ( .D(n114), .CLK(n6), .Q(wp[5]) );
  inv1a3 U4 ( .A(n25), .Y(n17) );
  clk1b6 U5 ( .A(n32), .Y(n30) );
  and2c6 U6 ( .A(n34), .B(we), .Y(n1) );
  inv1a1 U7 ( .A(rp[3]), .Y(n4) );
  inv1a2 U8 ( .A(n33), .Y(n28) );
  inv1a3 U9 ( .A(cnt[6]), .Y(n21) );
  or2c3 U10 ( .A(n30), .B(n39), .Y(n25) );
  inv1a3 U11 ( .A(re), .Y(n39) );
  inv1a3 U12 ( .A(n24), .Y(n13) );
  and3d6 U13 ( .A(n1), .B(n17), .C(n28), .Y(n24) );
  or2c3 U14 ( .A(n33), .B(n32), .Y(n31) );
  and2c9 U15 ( .A(clr), .B(n5), .Y(n33) );
  or2c3 U16 ( .A(n33), .B(n34), .Y(n35) );
  or2c3 U17 ( .A(re), .B(n33), .Y(n34) );
  and2c3 U18 ( .A(gb), .B(n43), .Y(empty) );
  or3d2 U19 ( .A(n78), .B(n79), .C(n80), .Y(n43) );
  or2c2 U20 ( .A(we), .B(n33), .Y(n32) );
  xor2b1 U21 ( .A(wp[1]), .B(rp[1]), .Y(n50) );
  xor2a2 U22 ( .A(\add_215/carry[5] ), .B(wp[5]), .Y(wp_pl1[5]) );
  ao4e1 U23 ( .B(rp[0]), .A(n35), .C(rp[0]), .D(n34), .Y(n113) );
  clk1a15 U24 ( .A(clk), .Y(n6) );
  inv1a3 U25 ( .A(n3), .Y(n2) );
  or3a3 U26 ( .A(cnt[4]), .B(cnt[5]), .C(cnt[3]), .Y(n9) );
  inv1a1 U27 ( .A(cnt[0]), .Y(n12) );
  inv1a1 U28 ( .A(rst), .Y(n5) );
  inv1a3 U29 ( .A(wp_pl2[0]), .Y(wp_pl1[0]) );
  inv1a1 U30 ( .A(cnt[2]), .Y(n10) );
  inv1a1 U31 ( .A(cnt[1]), .Y(n11) );
  inv1a3 U32 ( .A(rp[0]), .Y(n3) );
  xor2b1 U33 ( .A(cnt[6]), .B(\add_293_S2/carry[6] ), .Y(N69) );
  or2a1 U34 ( .A(cnt[5]), .B(\add_293_S2/carry[5] ), .Y(\add_293_S2/carry[6] )
         );
  xor2b1 U35 ( .A(\add_293_S2/carry[5] ), .B(cnt[5]), .Y(N68) );
  or2a1 U36 ( .A(cnt[4]), .B(\add_293_S2/carry[4] ), .Y(\add_293_S2/carry[5] )
         );
  xor2b1 U37 ( .A(\add_293_S2/carry[4] ), .B(cnt[4]), .Y(N67) );
  or2a1 U38 ( .A(cnt[3]), .B(\add_293_S2/carry[3] ), .Y(\add_293_S2/carry[4] )
         );
  xor2b1 U39 ( .A(\add_293_S2/carry[3] ), .B(cnt[3]), .Y(N66) );
  or2a1 U40 ( .A(cnt[2]), .B(\add_293_S2/carry[2] ), .Y(\add_293_S2/carry[3] )
         );
  xor2b1 U41 ( .A(\add_293_S2/carry[2] ), .B(cnt[2]), .Y(N65) );
  or2a1 U42 ( .A(cnt[1]), .B(cnt[0]), .Y(\add_293_S2/carry[2] ) );
  xor2b1 U43 ( .A(cnt[0]), .B(cnt[1]), .Y(N64) );
  xor2a1 U44 ( .A(wp[5]), .B(\add_216/carry[5] ), .Y(wp_pl2[5]) );
  and2a1 U45 ( .A(wp[4]), .B(\add_216/carry[4] ), .Y(\add_216/carry[5] ) );
  xor2a1 U46 ( .A(wp[4]), .B(\add_216/carry[4] ), .Y(wp_pl2[4]) );
  and2a1 U47 ( .A(wp[3]), .B(\add_216/carry[3] ), .Y(\add_216/carry[4] ) );
  xor2a1 U48 ( .A(wp[3]), .B(\add_216/carry[3] ), .Y(wp_pl2[3]) );
  and2a1 U49 ( .A(wp[2]), .B(wp[1]), .Y(\add_216/carry[3] ) );
  xor2a1 U50 ( .A(wp[2]), .B(wp[1]), .Y(wp_pl2[2]) );
  xor2a1 U51 ( .A(\add_225/carry[5] ), .B(rp[5]), .Y(rp_pl1[5]) );
  or2c1 U52 ( .A(n11), .B(n10), .Y(n7) );
  ao1f1 U53 ( .A(n9), .B(n7), .C(cnt[6]), .Y(N95) );
  or3d1 U54 ( .A(n11), .B(n10), .C(n12), .Y(n8) );
  ao1f1 U55 ( .A(n9), .B(n8), .C(cnt[6]), .Y(N59) );
  inv1a1 U56 ( .A(N59), .Y(full_n) );
  ao2i1 U57 ( .A(n13), .B(n14), .C(n15), .D(n16), .Y(n99) );
  or2c1 U58 ( .A(N75), .B(n17), .Y(n16) );
  or2c1 U59 ( .A(N67), .B(n1), .Y(n15) );
  ao2i1 U60 ( .A(n13), .B(n18), .C(n19), .D(n20), .Y(n98) );
  or2c1 U61 ( .A(N76), .B(n17), .Y(n20) );
  or2c1 U62 ( .A(N68), .B(n1), .Y(n19) );
  ao2i1 U63 ( .A(n13), .B(n21), .C(n22), .D(n23), .Y(n97) );
  or2c1 U64 ( .A(N77), .B(n17), .Y(n23) );
  or2c1 U65 ( .A(N69), .B(n1), .Y(n22) );
  ao1f1 U66 ( .A(n25), .B(n21), .C(n26), .Y(n96) );
  or2c1 U67 ( .A(full_n_r), .B(n27), .Y(n26) );
  ao1f1 U68 ( .A(N95), .B(n28), .C(n29), .Y(n27) );
  ao4b1 U69 ( .C(wp_pl1[0]), .D(n30), .B(wp_pl2[0]), .A(n31), .Y(n119) );
  ao4b1 U70 ( .C(wp_pl1[1]), .D(n30), .B(wp[1]), .A(n31), .Y(n118) );
  ao4b1 U71 ( .C(wp_pl1[2]), .D(n30), .B(wp[2]), .A(n31), .Y(n117) );
  ao4b1 U72 ( .C(wp_pl1[3]), .D(n30), .B(wp[3]), .A(n31), .Y(n116) );
  ao4d1 U73 ( .B(wp_pl1[4]), .A(n32), .D(wp[4]), .C(n31), .Y(n115) );
  ao4b1 U74 ( .C(wp_pl1[5]), .D(n30), .B(wp[5]), .A(n31), .Y(n114) );
  ao4d1 U75 ( .B(rp_pl1[1]), .A(n34), .D(rp[1]), .C(n35), .Y(n112) );
  ao4d1 U76 ( .B(rp_pl1[2]), .A(n34), .D(rp[2]), .C(n35), .Y(n111) );
  ao4e1 U77 ( .B(rp_pl1[3]), .A(n34), .C(n35), .D(n4), .Y(n110) );
  ao4d1 U78 ( .B(rp_pl1[4]), .A(n34), .D(rp[4]), .C(n35), .Y(n109) );
  ao4e1 U79 ( .B(rp_pl1[5]), .A(n34), .C(n35), .D(n36), .Y(n108) );
  ao1f1 U80 ( .A(n32), .B(n37), .C(n38), .Y(n107) );
  or3d1 U81 ( .A(n33), .B(n39), .C(gb), .Y(n38) );
  ao1f1 U82 ( .A(n40), .B(n41), .C(n42), .Y(n106) );
  ao2h1 U83 ( .B(n43), .A(n39), .C(n33), .D(gb2), .Y(n42) );
  or3d1 U84 ( .A(n44), .B(n45), .C(n46), .Y(n41) );
  xor2b1 U85 ( .A(rp[4]), .B(wp_pl2[4]), .Y(n46) );
  xor2a1 U86 ( .A(n36), .B(wp_pl2[5]), .Y(n45) );
  inv1a1 U87 ( .A(rp[5]), .Y(n36) );
  xor2a1 U88 ( .A(n4), .B(wp_pl2[3]), .Y(n44) );
  or3d1 U89 ( .A(n47), .B(n30), .C(n48), .Y(n40) );
  and2c1 U90 ( .A(n49), .B(n50), .Y(n48) );
  xor2a1 U91 ( .A(wp_pl2[2]), .B(rp[2]), .Y(n49) );
  xor2a1 U92 ( .A(n3), .B(wp_pl2[0]), .Y(n47) );
  ao1f1 U93 ( .A(n29), .B(n51), .C(n52), .Y(n105) );
  or3d1 U94 ( .A(n53), .B(n54), .C(gb2), .Y(n52) );
  ao1f1 U95 ( .A(n28), .B(n51), .C(n25), .Y(n54) );
  inv1a1 U96 ( .A(n37), .Y(n53) );
  or3d1 U97 ( .A(n55), .B(n56), .C(n57), .Y(n37) );
  and3d1 U98 ( .A(n58), .B(n59), .C(n60), .Y(n57) );
  xor2a1 U99 ( .A(wp_pl1[0]), .B(n2), .Y(n60) );
  xor2a1 U100 ( .A(wp_pl1[2]), .B(rp[2]), .Y(n59) );
  xor2a1 U101 ( .A(wp_pl1[1]), .B(rp[1]), .Y(n58) );
  xor2b1 U102 ( .A(wp_pl1[4]), .B(rp[4]), .Y(n56) );
  and2c1 U103 ( .A(n61), .B(n62), .Y(n55) );
  xor2a1 U104 ( .A(wp_pl1[3]), .B(rp[3]), .Y(n62) );
  xor2a1 U105 ( .A(wp_pl1[5]), .B(rp[5]), .Y(n61) );
  inv1a1 U106 ( .A(full_r), .Y(n51) );
  oa1f1 U107 ( .A(n39), .B(n33), .C(n30), .Y(n29) );
  ao2i1 U108 ( .A(n63), .B(n64), .C(n65), .D(n33), .Y(n104) );
  ao1d1 U109 ( .A(n39), .B(we), .C(empty_r), .Y(n65) );
  or3d1 U110 ( .A(n66), .B(n67), .C(n68), .Y(n64) );
  and2c1 U111 ( .A(n69), .B(n70), .Y(n68) );
  xor2a1 U112 ( .A(wp[3]), .B(rp_pl1[3]), .Y(n70) );
  xor2a1 U113 ( .A(wp[2]), .B(rp_pl1[2]), .Y(n69) );
  xor2b1 U114 ( .A(rp_pl1[4]), .B(wp[4]), .Y(n67) );
  xor2b1 U115 ( .A(rp_pl1[5]), .B(wp[5]), .Y(n66) );
  or3d1 U116 ( .A(n71), .B(n72), .C(n73), .Y(n63) );
  oa1d1 U117 ( .A(empty_r), .B(n1), .C(gb2), .Y(n73) );
  xor2b1 U118 ( .A(n3), .B(wp_pl2[0]), .Y(n72) );
  xor2b1 U119 ( .A(rp_pl1[1]), .B(wp[1]), .Y(n71) );
  ao1d1 U120 ( .A(N71), .B(n17), .C(n74), .Y(n103) );
  oa4f1 U121 ( .A(cnt[0]), .B(n24), .C(n12), .D(n1), .Y(n74) );
  ao1d1 U122 ( .A(N72), .B(n17), .C(n75), .Y(n102) );
  oa4f1 U123 ( .A(cnt[1]), .B(n24), .C(N64), .D(n1), .Y(n75) );
  ao1d1 U124 ( .A(N73), .B(n17), .C(n76), .Y(n101) );
  oa4f1 U125 ( .A(cnt[2]), .B(n24), .C(N65), .D(n1), .Y(n76) );
  ao1d1 U126 ( .A(N74), .B(n17), .C(n77), .Y(n100) );
  oa4f1 U127 ( .A(cnt[3]), .B(n24), .C(N66), .D(n1), .Y(n77) );
  or2c1 U128 ( .A(n21), .B(n18), .Y(level[1]) );
  inv1a1 U129 ( .A(cnt[5]), .Y(n18) );
  or2c1 U130 ( .A(n21), .B(n14), .Y(level[0]) );
  inv1a1 U131 ( .A(cnt[4]), .Y(n14) );
  and2b1 U132 ( .B(gb), .A(n43), .Y(full) );
  and3d1 U133 ( .A(n81), .B(n82), .C(n83), .Y(n80) );
  xor2a1 U134 ( .A(wp_pl2[0]), .B(n2), .Y(n83) );
  xor2a1 U135 ( .A(wp[2]), .B(rp[2]), .Y(n82) );
  xor2a1 U136 ( .A(wp[1]), .B(rp[1]), .Y(n81) );
  xor2b1 U137 ( .A(wp[4]), .B(rp[4]), .Y(n79) );
  and2c1 U138 ( .A(n84), .B(n85), .Y(n78) );
  xor2a1 U139 ( .A(wp[3]), .B(rp[3]), .Y(n85) );
  xor2a1 U140 ( .A(wp[5]), .B(rp[5]), .Y(n84) );
endmodule


module usb1_core ( clk_i, rst_i, DataOut, TxValid, TxReady, RxValid, RxActive, 
        RxError, DataIn, LineState, phy_tx_mode, usb_rst, dropped_frame, 
        misaligned_frame, crc16_err, v_set_int, v_set_feature, wValue, wIndex, 
        vendor_data, usb_busy, ep_sel, ep1_cfg, ep1_din, ep1_we, ep1_full, 
        ep1_dout, ep1_re, ep1_empty, ep1_bf_en, ep1_bf_size, ep2_cfg, ep2_din, 
        ep2_we, ep2_full, ep2_dout, ep2_re, ep2_empty, ep2_bf_en, ep2_bf_size, 
        ep3_cfg, ep3_din, ep3_we, ep3_full, ep3_dout, ep3_re, ep3_empty, 
        ep3_bf_en, ep3_bf_size, ep4_cfg, ep4_din, ep4_we, ep4_full, ep4_dout, 
        ep4_re, ep4_empty, ep4_bf_en, ep4_bf_size, ep5_cfg, ep5_din, ep5_we, 
        ep5_full, ep5_dout, ep5_re, ep5_empty, ep5_bf_en, ep5_bf_size, ep6_cfg, 
        ep6_din, ep6_we, ep6_full, ep6_dout, ep6_re, ep6_empty, ep6_bf_en, 
        ep6_bf_size, ep7_cfg, ep7_din, ep7_we, ep7_full, ep7_dout, ep7_re, 
        ep7_empty, ep7_bf_en, ep7_bf_size, reg_addr, reg_rdwrn, reg_req, 
        reg_wdata, reg_rdata, reg_ack );
  output [7:0] DataOut;
  input [7:0] DataIn;
  input [1:0] LineState;
  output [15:0] wValue;
  output [15:0] wIndex;
  input [15:0] vendor_data;
  output [3:0] ep_sel;
  input [13:0] ep1_cfg;
  input [7:0] ep1_din;
  output [7:0] ep1_dout;
  input [6:0] ep1_bf_size;
  input [13:0] ep2_cfg;
  input [7:0] ep2_din;
  output [7:0] ep2_dout;
  input [6:0] ep2_bf_size;
  input [13:0] ep3_cfg;
  input [7:0] ep3_din;
  output [7:0] ep3_dout;
  input [6:0] ep3_bf_size;
  input [13:0] ep4_cfg;
  input [7:0] ep4_din;
  output [7:0] ep4_dout;
  input [6:0] ep4_bf_size;
  input [13:0] ep5_cfg;
  input [7:0] ep5_din;
  output [7:0] ep5_dout;
  input [6:0] ep5_bf_size;
  input [13:0] ep6_cfg;
  input [7:0] ep6_din;
  output [7:0] ep6_dout;
  input [6:0] ep6_bf_size;
  input [13:0] ep7_cfg;
  input [7:0] ep7_din;
  output [7:0] ep7_dout;
  input [6:0] ep7_bf_size;
  output [31:0] reg_addr;
  output [31:0] reg_wdata;
  input [31:0] reg_rdata;
  input clk_i, rst_i, TxReady, RxValid, RxActive, RxError, phy_tx_mode,
         usb_rst, ep1_full, ep1_empty, ep1_bf_en, ep2_full, ep2_empty,
         ep2_bf_en, ep3_full, ep3_empty, ep3_bf_en, ep4_full, ep4_empty,
         ep4_bf_en, ep5_full, ep5_empty, ep5_bf_en, ep6_full, ep6_empty,
         ep6_bf_en, ep7_full, ep7_empty, ep7_bf_en, reg_ack;
  output TxValid, dropped_frame, misaligned_frame, crc16_err, v_set_int,
         v_set_feature, usb_busy, ep1_we, ep1_re, ep2_we, ep2_re, ep3_we,
         ep3_re, ep4_we, ep4_re, ep5_we, ep5_re, ep6_we, ep6_re, ep7_we,
         ep7_re, reg_rdwrn, reg_req;
  wire   N41, rst_local, rx_valid, rx_active, rx_err, tx_valid, tx_valid_last,
         tx_ready, tx_first, ctrl_setup, ctrl_in, ctrl_out, send_stall,
         ep_bf_en, rx_ctrl_dvalid, rx_ctrl_ddone, idma_re, idma_we, ep_empty,
         ep_full, ep0_ctrl_re, ep0_ctrl_we, ep0_we, ep0_full, ep0_re,
         ep0_empty, N86, N87, N88, N89, N90, N91, N92, N93, N116, N161, N185,
         N186, N187, N188, N189, N190, N191, n12, n13, n14, n15, n16, n17, n19,
         n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
         n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
         n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61,
         n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
         n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89,
         n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
         n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113,
         n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124,
         n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
         n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146,
         n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
         n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168,
         n169, n170, n1, n3, n4, n5, n6, n7, n8, n9, n10, n11, n18, n171, n172,
         n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
         n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
         n195;
  wire   [7:0] ep0_cfg;
  wire   [7:0] rx_data;
  wire   [7:0] tx_data;
  wire   [6:0] funct_adr;
  wire   [31:0] frm_nat;
  wire   [6:0] ep_bf_size;
  wire   [13:0] cfg;
  wire   [7:0] tx_data_st;
  wire   [7:0] rx_ctrl_data;
  wire   [6:0] rom_adr;
  wire   [7:0] rom_data;
  wire   [7:0] ep0_ctrl_dout;
  wire   [7:0] ep0_ctrl_din;
  wire   [3:0] ep0_ctrl_stat;
  tri   [7:0] ep0_dout;
  wire   SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1, 
        SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3, 
        SYNOPSYS_UNCONNECTED__4, SYNOPSYS_UNCONNECTED__5, 
        SYNOPSYS_UNCONNECTED__6, SYNOPSYS_UNCONNECTED__7, 
        SYNOPSYS_UNCONNECTED__8, SYNOPSYS_UNCONNECTED__9, 
        SYNOPSYS_UNCONNECTED__10, SYNOPSYS_UNCONNECTED__11, 
        SYNOPSYS_UNCONNECTED__12, SYNOPSYS_UNCONNECTED__13, 
        SYNOPSYS_UNCONNECTED__14, SYNOPSYS_UNCONNECTED__15, 
        SYNOPSYS_UNCONNECTED__16, SYNOPSYS_UNCONNECTED__17, 
        SYNOPSYS_UNCONNECTED__18, SYNOPSYS_UNCONNECTED__19, 
        SYNOPSYS_UNCONNECTED__20, SYNOPSYS_UNCONNECTED__21;
  assign ep7_dout[7] = ep1_dout[7];
  assign ep6_dout[7] = ep1_dout[7];
  assign ep5_dout[7] = ep1_dout[7];
  assign ep4_dout[7] = ep1_dout[7];
  assign ep3_dout[7] = ep1_dout[7];
  assign ep2_dout[7] = ep1_dout[7];
  assign ep7_dout[6] = ep1_dout[6];
  assign ep6_dout[6] = ep1_dout[6];
  assign ep5_dout[6] = ep1_dout[6];
  assign ep4_dout[6] = ep1_dout[6];
  assign ep3_dout[6] = ep1_dout[6];
  assign ep2_dout[6] = ep1_dout[6];
  assign ep7_dout[5] = ep1_dout[5];
  assign ep6_dout[5] = ep1_dout[5];
  assign ep5_dout[5] = ep1_dout[5];
  assign ep4_dout[5] = ep1_dout[5];
  assign ep3_dout[5] = ep1_dout[5];
  assign ep2_dout[5] = ep1_dout[5];
  assign ep7_dout[4] = ep1_dout[4];
  assign ep6_dout[4] = ep1_dout[4];
  assign ep5_dout[4] = ep1_dout[4];
  assign ep4_dout[4] = ep1_dout[4];
  assign ep3_dout[4] = ep1_dout[4];
  assign ep2_dout[4] = ep1_dout[4];
  assign ep7_dout[3] = ep1_dout[3];
  assign ep6_dout[3] = ep1_dout[3];
  assign ep5_dout[3] = ep1_dout[3];
  assign ep4_dout[3] = ep1_dout[3];
  assign ep3_dout[3] = ep1_dout[3];
  assign ep2_dout[3] = ep1_dout[3];
  assign ep7_dout[2] = ep1_dout[2];
  assign ep6_dout[2] = ep1_dout[2];
  assign ep5_dout[2] = ep1_dout[2];
  assign ep4_dout[2] = ep1_dout[2];
  assign ep3_dout[2] = ep1_dout[2];
  assign ep2_dout[2] = ep1_dout[2];
  assign ep7_dout[1] = ep1_dout[1];
  assign ep6_dout[1] = ep1_dout[1];
  assign ep5_dout[1] = ep1_dout[1];
  assign ep4_dout[1] = ep1_dout[1];
  assign ep3_dout[1] = ep1_dout[1];
  assign ep2_dout[1] = ep1_dout[1];
  assign ep7_dout[0] = ep1_dout[0];
  assign ep6_dout[0] = ep1_dout[0];
  assign ep5_dout[0] = ep1_dout[0];
  assign ep4_dout[0] = ep1_dout[0];
  assign ep3_dout[0] = ep1_dout[0];
  assign ep2_dout[0] = ep1_dout[0];
  assign dropped_frame = 1'b0;
  assign misaligned_frame = 1'b0;

  and2b2 U5 ( .B(ep7_full), .A(n17), .Y(n16) );
  ao4a3 U6 ( .A(n176), .B(ep4_full), .C(n180), .D(ep5_full), .Y(n15) );
  oa4f3 U7 ( .A(ep3_full), .B(n18), .C(ep2_full), .D(n173), .Y(n13) );
  oa4f3 U8 ( .A(ep1_full), .B(n8), .C(ep0_full), .D(n187), .Y(n12) );
  or2c6 U24 ( .A(idma_we), .B(n195), .Y(n19) );
  or2c6 U26 ( .A(idma_re), .B(n195), .Y(n20) );
  ao4a3 U29 ( .A(ep2_cfg[9]), .B(n173), .C(ep3_cfg[9]), .D(n18), .Y(n30) );
  oa4f3 U30 ( .A(ep7_cfg[9]), .B(n179), .C(ep6_cfg[9]), .D(n6), .Y(n28) );
  oa4f3 U31 ( .A(ep5_cfg[9]), .B(n182), .C(ep4_cfg[9]), .D(n176), .Y(n27) );
  ao4a3 U34 ( .A(ep2_cfg[8]), .B(n173), .C(ep3_cfg[8]), .D(n11), .Y(n34) );
  oa4f3 U35 ( .A(ep7_cfg[8]), .B(n179), .C(ep6_cfg[8]), .D(n5), .Y(n32) );
  oa4f3 U36 ( .A(ep5_cfg[8]), .B(n182), .C(ep4_cfg[8]), .D(n176), .Y(n31) );
  oa4f3 U39 ( .A(ep7_cfg[7]), .B(n179), .C(ep6_cfg[7]), .D(n5), .Y(n39) );
  oa4f3 U40 ( .A(ep5_cfg[7]), .B(n182), .C(ep4_cfg[7]), .D(n176), .Y(n38) );
  oa4f3 U41 ( .A(ep3_cfg[7]), .B(n11), .C(ep2_cfg[7]), .D(n173), .Y(n36) );
  oa4f3 U45 ( .A(ep7_cfg[6]), .B(n179), .C(ep6_cfg[6]), .D(n5), .Y(n44) );
  oa4f3 U46 ( .A(ep5_cfg[6]), .B(n182), .C(ep4_cfg[6]), .D(n176), .Y(n43) );
  oa4f3 U47 ( .A(ep3_cfg[6]), .B(n11), .C(ep2_cfg[6]), .D(n173), .Y(n41) );
  oa4f3 U48 ( .A(ep1_cfg[6]), .B(n7), .C(ep0_cfg[6]), .D(n187), .Y(n40) );
  oa4f3 U51 ( .A(ep7_cfg[5]), .B(n179), .C(ep6_cfg[5]), .D(n5), .Y(n49) );
  oa4f3 U52 ( .A(ep5_cfg[5]), .B(n182), .C(ep4_cfg[5]), .D(n175), .Y(n48) );
  oa4f3 U53 ( .A(ep3_cfg[5]), .B(n11), .C(ep2_cfg[5]), .D(n172), .Y(n46) );
  oa4f3 U54 ( .A(ep1_cfg[5]), .B(n7), .C(ep0_cfg[5]), .D(n187), .Y(n45) );
  oa4f3 U57 ( .A(ep7_cfg[4]), .B(n179), .C(ep6_cfg[4]), .D(n5), .Y(n54) );
  oa4f3 U58 ( .A(ep5_cfg[4]), .B(n182), .C(ep4_cfg[4]), .D(n175), .Y(n53) );
  oa4f3 U59 ( .A(ep3_cfg[4]), .B(n11), .C(ep2_cfg[4]), .D(n172), .Y(n51) );
  oa4f3 U60 ( .A(ep1_cfg[4]), .B(n7), .C(ep0_cfg[4]), .D(n187), .Y(n50) );
  oa4f3 U63 ( .A(ep7_cfg[3]), .B(n179), .C(ep6_cfg[3]), .D(n5), .Y(n59) );
  oa4f3 U64 ( .A(ep5_cfg[3]), .B(n182), .C(ep4_cfg[3]), .D(n175), .Y(n58) );
  oa4f3 U65 ( .A(ep3_cfg[3]), .B(n11), .C(ep2_cfg[3]), .D(n172), .Y(n56) );
  oa4f3 U66 ( .A(ep1_cfg[3]), .B(n7), .C(ep0_cfg[3]), .D(n187), .Y(n55) );
  oa4f3 U69 ( .A(ep7_cfg[2]), .B(n179), .C(ep6_cfg[2]), .D(n5), .Y(n64) );
  oa4f3 U70 ( .A(ep5_cfg[2]), .B(n182), .C(ep4_cfg[2]), .D(n175), .Y(n63) );
  oa4f3 U71 ( .A(ep3_cfg[2]), .B(n11), .C(ep2_cfg[2]), .D(n172), .Y(n61) );
  oa4f3 U72 ( .A(ep1_cfg[2]), .B(n7), .C(ep0_cfg[2]), .D(n187), .Y(n60) );
  oa4f3 U75 ( .A(ep7_cfg[1]), .B(n179), .C(ep6_cfg[1]), .D(n5), .Y(n69) );
  oa4f3 U76 ( .A(ep5_cfg[1]), .B(n182), .C(ep4_cfg[1]), .D(n175), .Y(n68) );
  oa4f3 U77 ( .A(ep3_cfg[1]), .B(n11), .C(ep2_cfg[1]), .D(n172), .Y(n66) );
  oa4f3 U78 ( .A(ep1_cfg[1]), .B(n7), .C(ep0_cfg[1]), .D(n187), .Y(n65) );
  ao4a3 U81 ( .A(ep5_cfg[13]), .B(n182), .C(ep6_cfg[13]), .D(n5), .Y(n73) );
  oa4f3 U82 ( .A(ep4_cfg[13]), .B(n175), .C(ep3_cfg[13]), .D(n11), .Y(n71) );
  oa4f3 U83 ( .A(ep2_cfg[13]), .B(n172), .C(ep1_cfg[13]), .D(n7), .Y(n70) );
  ao4a3 U86 ( .A(ep2_cfg[12]), .B(n172), .C(ep3_cfg[12]), .D(n11), .Y(n77) );
  oa4f3 U87 ( .A(ep7_cfg[12]), .B(n178), .C(ep6_cfg[12]), .D(n5), .Y(n75) );
  oa4f3 U88 ( .A(ep5_cfg[12]), .B(n182), .C(ep4_cfg[12]), .D(n175), .Y(n74) );
  ao4a3 U91 ( .A(ep5_cfg[11]), .B(n181), .C(ep6_cfg[11]), .D(n4), .Y(n81) );
  oa4f3 U92 ( .A(ep4_cfg[11]), .B(n175), .C(ep3_cfg[11]), .D(n10), .Y(n79) );
  oa4f3 U93 ( .A(ep2_cfg[11]), .B(n172), .C(ep1_cfg[11]), .D(n8), .Y(n78) );
  ao4a3 U96 ( .A(ep2_cfg[10]), .B(n172), .C(ep3_cfg[10]), .D(n10), .Y(n85) );
  oa4f3 U97 ( .A(ep7_cfg[10]), .B(n178), .C(ep6_cfg[10]), .D(n4), .Y(n83) );
  oa4f3 U98 ( .A(ep5_cfg[10]), .B(n181), .C(ep4_cfg[10]), .D(n175), .Y(n82) );
  oa4f3 U101 ( .A(ep7_cfg[0]), .B(n178), .C(ep6_cfg[0]), .D(n4), .Y(n90) );
  oa4f3 U102 ( .A(ep5_cfg[0]), .B(n181), .C(ep4_cfg[0]), .D(n175), .Y(n89) );
  oa4f3 U103 ( .A(ep3_cfg[0]), .B(n10), .C(ep2_cfg[0]), .D(n172), .Y(n87) );
  oa4f3 U104 ( .A(ep1_cfg[0]), .B(n8), .C(ep0_cfg[0]), .D(n187), .Y(n86) );
  oa4f3 U107 ( .A(ep7_din[7]), .B(n178), .C(ep6_din[7]), .D(n4), .Y(n95) );
  oa4f3 U108 ( .A(ep5_din[7]), .B(n181), .C(ep4_din[7]), .D(n174), .Y(n94) );
  oa4f3 U109 ( .A(ep3_din[7]), .B(n10), .C(ep2_din[7]), .D(n171), .Y(n92) );
  oa4f3 U110 ( .A(ep1_din[7]), .B(n8), .C(ep0_dout[7]), .D(n187), .Y(n91) );
  oa4f3 U113 ( .A(ep7_din[6]), .B(n178), .C(ep6_din[6]), .D(n4), .Y(n100) );
  oa4f3 U114 ( .A(ep5_din[6]), .B(n181), .C(ep4_din[6]), .D(n174), .Y(n99) );
  oa4f3 U115 ( .A(ep3_din[6]), .B(n10), .C(ep2_din[6]), .D(n171), .Y(n97) );
  oa4f3 U116 ( .A(ep1_din[6]), .B(n8), .C(ep0_dout[6]), .D(n187), .Y(n96) );
  oa4f3 U119 ( .A(ep7_din[5]), .B(n178), .C(ep6_din[5]), .D(n4), .Y(n105) );
  oa4f3 U120 ( .A(ep5_din[5]), .B(n181), .C(ep4_din[5]), .D(n174), .Y(n104) );
  oa4f3 U121 ( .A(ep3_din[5]), .B(n10), .C(ep2_din[5]), .D(n171), .Y(n102) );
  oa4f3 U122 ( .A(ep1_din[5]), .B(n8), .C(ep0_dout[5]), .D(n187), .Y(n101) );
  oa4f3 U125 ( .A(ep7_din[4]), .B(n178), .C(ep6_din[4]), .D(n4), .Y(n110) );
  oa4f3 U126 ( .A(ep5_din[4]), .B(n181), .C(ep4_din[4]), .D(n174), .Y(n109) );
  oa4f3 U127 ( .A(ep3_din[4]), .B(n10), .C(ep2_din[4]), .D(n171), .Y(n107) );
  oa4f3 U128 ( .A(ep1_din[4]), .B(n8), .C(ep0_dout[4]), .D(n187), .Y(n106) );
  oa4f3 U131 ( .A(ep7_din[3]), .B(n178), .C(ep6_din[3]), .D(n4), .Y(n115) );
  oa4f3 U132 ( .A(ep5_din[3]), .B(n181), .C(ep4_din[3]), .D(n174), .Y(n114) );
  oa4f3 U133 ( .A(ep3_din[3]), .B(n10), .C(ep2_din[3]), .D(n171), .Y(n112) );
  oa4f3 U134 ( .A(ep1_din[3]), .B(n8), .C(ep0_dout[3]), .D(n187), .Y(n111) );
  oa4f3 U137 ( .A(ep7_din[2]), .B(n178), .C(ep6_din[2]), .D(n4), .Y(n120) );
  oa4f3 U138 ( .A(ep5_din[2]), .B(n181), .C(ep4_din[2]), .D(n174), .Y(n119) );
  oa4f3 U139 ( .A(ep3_din[2]), .B(n10), .C(ep2_din[2]), .D(n171), .Y(n117) );
  oa4f3 U140 ( .A(ep1_din[2]), .B(n8), .C(ep0_dout[2]), .D(n187), .Y(n116) );
  oa4f3 U143 ( .A(ep7_din[1]), .B(n177), .C(ep6_din[1]), .D(n4), .Y(n125) );
  oa4f3 U144 ( .A(ep5_din[1]), .B(n181), .C(ep4_din[1]), .D(n174), .Y(n124) );
  oa4f3 U145 ( .A(ep3_din[1]), .B(n10), .C(ep2_din[1]), .D(n171), .Y(n122) );
  oa4f3 U146 ( .A(ep1_din[1]), .B(n8), .C(ep0_dout[1]), .D(n187), .Y(n121) );
  oa4f3 U149 ( .A(ep7_din[0]), .B(n177), .C(ep6_din[0]), .D(n3), .Y(n130) );
  oa4f3 U150 ( .A(ep5_din[0]), .B(n180), .C(ep4_din[0]), .D(n174), .Y(n129) );
  oa4f3 U151 ( .A(ep3_din[0]), .B(n9), .C(ep2_din[0]), .D(n171), .Y(n127) );
  oa4f3 U152 ( .A(ep1_din[0]), .B(n8), .C(ep0_dout[0]), .D(n187), .Y(n126) );
  and2b2 U153 ( .B(rst_i), .A(usb_rst), .Y(N41) );
  ao4a3 U156 ( .A(ep2_bf_size[6]), .B(n136), .C(ep4_bf_size[6]), .D(n137), .Y(
        n135) );
  oa4f3 U157 ( .A(ep7_bf_size[6]), .B(n177), .C(ep6_bf_size[6]), .D(n3), .Y(
        n132) );
  oa4f3 U158 ( .A(ep5_bf_size[6]), .B(n180), .C(ep3_bf_size[6]), .D(n9), .Y(
        n131) );
  ao4a3 U161 ( .A(ep2_bf_size[5]), .B(n136), .C(ep4_bf_size[5]), .D(n137), .Y(
        n141) );
  oa4f3 U162 ( .A(ep7_bf_size[5]), .B(n177), .C(ep6_bf_size[5]), .D(n3), .Y(
        n139) );
  oa4f3 U163 ( .A(ep5_bf_size[5]), .B(n180), .C(ep3_bf_size[5]), .D(n9), .Y(
        n138) );
  ao4a3 U166 ( .A(ep2_bf_size[4]), .B(n136), .C(ep4_bf_size[4]), .D(n137), .Y(
        n145) );
  oa4f3 U167 ( .A(ep7_bf_size[4]), .B(n177), .C(ep6_bf_size[4]), .D(n3), .Y(
        n143) );
  oa4f3 U168 ( .A(ep5_bf_size[4]), .B(n180), .C(ep3_bf_size[4]), .D(n9), .Y(
        n142) );
  ao4a3 U171 ( .A(ep2_bf_size[3]), .B(n136), .C(ep4_bf_size[3]), .D(n137), .Y(
        n149) );
  oa4f3 U172 ( .A(ep7_bf_size[3]), .B(n177), .C(ep6_bf_size[3]), .D(n3), .Y(
        n147) );
  oa4f3 U173 ( .A(ep5_bf_size[3]), .B(n180), .C(ep3_bf_size[3]), .D(n9), .Y(
        n146) );
  ao4a3 U176 ( .A(ep2_bf_size[2]), .B(n136), .C(ep4_bf_size[2]), .D(n137), .Y(
        n153) );
  oa4f3 U177 ( .A(ep7_bf_size[2]), .B(n177), .C(ep6_bf_size[2]), .D(n3), .Y(
        n151) );
  oa4f3 U178 ( .A(ep5_bf_size[2]), .B(n180), .C(ep3_bf_size[2]), .D(n9), .Y(
        n150) );
  ao4a3 U181 ( .A(ep2_bf_size[1]), .B(n136), .C(ep4_bf_size[1]), .D(n137), .Y(
        n157) );
  oa4f3 U182 ( .A(ep7_bf_size[1]), .B(n177), .C(ep6_bf_size[1]), .D(n3), .Y(
        n155) );
  oa4f3 U183 ( .A(ep5_bf_size[1]), .B(n180), .C(ep3_bf_size[1]), .D(n9), .Y(
        n154) );
  ao4a3 U186 ( .A(ep2_bf_size[0]), .B(n136), .C(ep4_bf_size[0]), .D(n137), .Y(
        n161) );
  oa4f3 U187 ( .A(ep7_bf_size[0]), .B(n177), .C(ep6_bf_size[0]), .D(n3), .Y(
        n159) );
  oa4f3 U188 ( .A(ep5_bf_size[0]), .B(n180), .C(ep3_bf_size[0]), .D(n9), .Y(
        n158) );
  ao4a3 U191 ( .A(ep2_bf_en), .B(n171), .C(ep3_bf_en), .D(n9), .Y(n165) );
  oa4f3 U192 ( .A(ep7_bf_en), .B(n177), .C(ep6_bf_en), .D(n3), .Y(n163) );
  oa4f3 U193 ( .A(ep5_bf_en), .B(n180), .C(ep4_bf_en), .D(n174), .Y(n162) );
  and2b2 U196 ( .B(ep7_empty), .A(n17), .Y(n170) );
  ao4a3 U198 ( .A(n174), .B(ep4_empty), .C(n180), .D(ep5_empty), .Y(n169) );
  and2c6 U201 ( .A(ep_sel[0]), .B(ep_sel[1]), .Y(n137) );
  oa4f3 U203 ( .A(ep3_empty), .B(n9), .C(ep2_empty), .D(n171), .Y(n167) );
  and2c6 U205 ( .A(ep_sel[0]), .B(ep_sel[2]), .Y(n136) );
  oa4f3 U207 ( .A(ep1_empty), .B(n7), .C(ep0_empty), .D(n187), .Y(n166) );
  usb1_utmi_if u0 ( .phy_clk(n185), .rst(rst_local), .DataOut(DataOut), 
        .TxValid(TxValid), .TxReady(TxReady), .RxValid(RxValid), .RxActive(
        RxActive), .RxError(RxError), .DataIn(DataIn), .rx_data(rx_data), 
        .rx_valid(rx_valid), .rx_active(rx_active), .rx_err(rx_err), .tx_data(
        tx_data), .tx_valid(tx_valid), .tx_valid_last(tx_valid_last), 
        .tx_ready(tx_ready), .tx_first(tx_first) );
  usb1_pl u1 ( .clk(n185), .rst(rst_local), .rx_data(rx_data), .rx_valid(
        rx_valid), .rx_active(rx_active), .rx_err(rx_err), .tx_data(tx_data), 
        .tx_valid(tx_valid), .tx_valid_last(tx_valid_last), .tx_ready(tx_ready), .tx_first(tx_first), .tx_valid_out(TxValid), .fa(funct_adr), .ep_sel(ep_sel), 
        .x_busy(usb_busy), .int_crc16_set(crc16_err), .frm_nat({
        SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1, 
        SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3, 
        SYNOPSYS_UNCONNECTED__4, frm_nat[26:16], SYNOPSYS_UNCONNECTED__5, 
        SYNOPSYS_UNCONNECTED__6, SYNOPSYS_UNCONNECTED__7, 
        SYNOPSYS_UNCONNECTED__8, SYNOPSYS_UNCONNECTED__9, 
        SYNOPSYS_UNCONNECTED__10, SYNOPSYS_UNCONNECTED__11, 
        SYNOPSYS_UNCONNECTED__12, SYNOPSYS_UNCONNECTED__13, 
        SYNOPSYS_UNCONNECTED__14, SYNOPSYS_UNCONNECTED__15, 
        SYNOPSYS_UNCONNECTED__16, SYNOPSYS_UNCONNECTED__17, 
        SYNOPSYS_UNCONNECTED__18, SYNOPSYS_UNCONNECTED__19, 
        SYNOPSYS_UNCONNECTED__20}), .ctrl_setup(ctrl_setup), .ctrl_in(ctrl_in), 
        .ctrl_out(ctrl_out), .ep_bf_en(ep_bf_en), .ep_bf_size(ep_bf_size), 
        .csr(cfg), .tx_data_st(tx_data_st), .rx_ctrl_data(rx_ctrl_data), 
        .rx_ctrl_data_d(ep1_dout), .rx_ctrl_dvalid(rx_ctrl_dvalid), 
        .rx_ctrl_ddone(rx_ctrl_ddone), .idma_re(idma_re), .idma_we(idma_we), 
        .ep_empty(ep_empty), .ep_full(ep_full), .send_stall(send_stall) );
  usb1_ctrl u4 ( .clk(n185), .rst(rst_local), .rom_adr(rom_adr), .rom_data(
        rom_data), .ctrl_setup(ctrl_setup), .ctrl_in(ctrl_in), .ctrl_out(
        ctrl_out), .rx_ctrl_data(rx_ctrl_data), .rx_ctrl_dvalid(rx_ctrl_dvalid), .rx_ctrl_ddone(rx_ctrl_ddone), .ep0_din(ep0_ctrl_dout), .ep0_dout(
        ep0_ctrl_din), .ep0_re(ep0_ctrl_re), .ep0_we(ep0_ctrl_we), .ep0_stat({
        1'b0, ep0_ctrl_stat[2:1], 1'b0}), .ep0_size({SYNOPSYS_UNCONNECTED__21, 
        ep0_cfg[6:0]}), .send_stall(send_stall), .frame_no(frm_nat[26:16]), 
        .funct_adr(funct_adr), .v_set_int(v_set_int), .v_set_feature(
        v_set_feature), .wValue(wValue), .wIndex(wIndex), .vendor_data(
        vendor_data), .reg_addr(reg_addr), .reg_rdwrn(reg_rdwrn), .reg_req(
        reg_req), .reg_wdata(reg_wdata), .reg_rdata(reg_rdata), .reg_ack(
        reg_ack) );
  usb1_rom1 rom1 ( .clk(n185), .adr(rom_adr), .dout(rom_data) );
  sync_fifo_W8_D8 u10 ( .clk(n185), .reset_n(rst_i), .clr(usb_rst), .wr_en(
        ep0_we), .wr_data(ep1_dout), .full(ep0_full), .empty(ep0_ctrl_stat[1]), 
        .rd_en(ep0_ctrl_re), .rd_data(ep0_ctrl_dout) );
  generic_fifo_sc_a_dw8_aw6_n0 u11 ( .clk(n185), .rst(rst_i), .clr(usb_rst), 
        .din(ep0_ctrl_din), .we(ep0_ctrl_we), .dout(ep0_dout), .re(ep0_re), 
        .full(ep0_ctrl_stat[2]), .empty(ep0_empty) );
  fdf1a3 rst_local_reg ( .D(N41), .CLK(n185), .Q(rst_local) );
  fdf1a3 \ep_bf_size_reg[0]  ( .D(N185), .CLK(n185), .Q(ep_bf_size[0]) );
  fdf1a3 \ep_bf_size_reg[6]  ( .D(N191), .CLK(n185), .Q(ep_bf_size[6]) );
  fdf1a3 \ep_bf_size_reg[5]  ( .D(N190), .CLK(n185), .Q(ep_bf_size[5]) );
  fdf1a3 \ep_bf_size_reg[4]  ( .D(N189), .CLK(n185), .Q(ep_bf_size[4]) );
  fdf1a3 \ep_bf_size_reg[3]  ( .D(N188), .CLK(n185), .Q(ep_bf_size[3]) );
  fdf1a3 \ep_bf_size_reg[2]  ( .D(N187), .CLK(n185), .Q(ep_bf_size[2]) );
  fdf1a3 \ep_bf_size_reg[1]  ( .D(N186), .CLK(n185), .Q(ep_bf_size[1]) );
  fdf1a3 ep_bf_en_reg ( .D(N161), .CLK(n185), .Q(ep_bf_en) );
  fdf1a3 \tx_data_st_reg[0]  ( .D(N86), .CLK(n185), .Q(tx_data_st[0]) );
  fdf1a3 \tx_data_st_reg[1]  ( .D(N87), .CLK(n185), .Q(tx_data_st[1]) );
  fdf1a3 \tx_data_st_reg[2]  ( .D(N88), .CLK(n185), .Q(tx_data_st[2]) );
  fdf1a3 \tx_data_st_reg[3]  ( .D(N89), .CLK(n185), .Q(tx_data_st[3]) );
  fdf1a3 \tx_data_st_reg[4]  ( .D(N90), .CLK(n185), .Q(tx_data_st[4]) );
  fdf1a3 \tx_data_st_reg[5]  ( .D(N91), .CLK(n185), .Q(tx_data_st[5]) );
  fdf1a3 \tx_data_st_reg[6]  ( .D(N92), .CLK(n185), .Q(tx_data_st[6]) );
  fdf1a3 \tx_data_st_reg[7]  ( .D(N93), .CLK(n185), .Q(tx_data_st[7]) );
  fdf1a3 ep_empty_reg ( .D(N116), .CLK(n185), .Q(ep_empty) );
  and2c3 U3 ( .A(n26), .B(n19), .Y(ep0_we) );
  inv1a9 U4 ( .A(n26), .Y(n187) );
  inv1a1 U9 ( .A(n25), .Y(n189) );
  or3d1 U10 ( .A(n86), .B(n87), .C(n88), .Y(cfg[0]) );
  or3d1 U11 ( .A(n70), .B(n71), .C(n72), .Y(cfg[13]) );
  inv1a1 U12 ( .A(ep_sel[2]), .Y(n194) );
  and2c3 U13 ( .A(n26), .B(n20), .Y(ep0_re) );
  buf1a9 U14 ( .A(n189), .Y(n7) );
  clk1b6 U15 ( .A(n184), .Y(n182) );
  clk1b6 U16 ( .A(n184), .Y(n181) );
  clk1b6 U17 ( .A(n183), .Y(n180) );
  clk1a6 U18 ( .A(n189), .Y(n8) );
  clk1a6 U19 ( .A(n192), .Y(n175) );
  clk1a6 U20 ( .A(n191), .Y(n172) );
  clk1a6 U21 ( .A(n191), .Y(n171) );
  clk1a6 U22 ( .A(n192), .Y(n174) );
  clk1a6 U23 ( .A(n193), .Y(n178) );
  clk1a6 U25 ( .A(n193), .Y(n179) );
  clk1a6 U27 ( .A(n193), .Y(n177) );
  clk1a6 U28 ( .A(n190), .Y(n11) );
  clk1a6 U32 ( .A(n190), .Y(n10) );
  clk1a6 U33 ( .A(n190), .Y(n9) );
  clk1a6 U37 ( .A(n186), .Y(n5) );
  clk1a6 U38 ( .A(n186), .Y(n4) );
  clk1a6 U42 ( .A(n186), .Y(n3) );
  clk1a3 U43 ( .A(n191), .Y(n173) );
  clk1a3 U44 ( .A(n192), .Y(n176) );
  clk1a3 U49 ( .A(n190), .Y(n18) );
  clk1a3 U50 ( .A(n186), .Y(n6) );
  or2c3 U55 ( .A(n134), .B(n188), .Y(n26) );
  inv1a3 U56 ( .A(n21), .Y(n186) );
  inv1a3 U61 ( .A(n23), .Y(n190) );
  inv1a3 U62 ( .A(n17), .Y(n193) );
  inv1a3 U67 ( .A(n22), .Y(n192) );
  inv1a3 U68 ( .A(n24), .Y(n191) );
  clk1a3 U73 ( .A(n1), .Y(n183) );
  clk1a3 U74 ( .A(n1), .Y(n184) );
  and2c9 U79 ( .A(ep_sel[1]), .B(ep_sel[2]), .Y(n134) );
  or3d3 U80 ( .A(ep_sel[1]), .B(ep_sel[0]), .C(ep_sel[2]), .Y(n17) );
  or3d3 U84 ( .A(n74), .B(n75), .C(n76), .Y(cfg[12]) );
  oa1f3 U85 ( .A(ep1_cfg[12]), .B(n7), .C(n77), .Y(n76) );
  or3d3 U89 ( .A(n78), .B(n79), .C(n80), .Y(cfg[11]) );
  oa2i2 U90 ( .A(ep7_cfg[11]), .B(n178), .C(n81), .D(n187), .Y(n80) );
  or3d3 U94 ( .A(ep_sel[1]), .B(n188), .C(ep_sel[2]), .Y(n21) );
  or3d3 U95 ( .A(ep_sel[0]), .B(n194), .C(ep_sel[1]), .Y(n23) );
  or2c2 U99 ( .A(n137), .B(ep_sel[2]), .Y(n22) );
  or2c2 U100 ( .A(n136), .B(ep_sel[1]), .Y(n24) );
  or3d3 U105 ( .A(n82), .B(n83), .C(n84), .Y(cfg[10]) );
  oa1f3 U106 ( .A(ep1_cfg[10]), .B(n7), .C(n85), .Y(n84) );
  or3d3 U111 ( .A(n27), .B(n28), .C(n29), .Y(cfg[9]) );
  oa1f3 U112 ( .A(ep1_cfg[9]), .B(n7), .C(n30), .Y(n29) );
  or2c3 U117 ( .A(n134), .B(ep_sel[0]), .Y(n25) );
  or3d3 U118 ( .A(n12), .B(n13), .C(n14), .Y(ep_full) );
  oa2i2 U123 ( .A(ep6_full), .B(n6), .C(n15), .D(n16), .Y(n14) );
  inv1a3 U124 ( .A(ep_sel[0]), .Y(n188) );
  and3d2 U129 ( .A(n20), .B(ep7_empty), .C(n17), .Y(ep7_re) );
  and3d2 U130 ( .A(n19), .B(ep7_full), .C(n17), .Y(ep7_we) );
  and3d2 U135 ( .A(n20), .B(ep6_empty), .C(n21), .Y(ep6_re) );
  and3d2 U136 ( .A(n19), .B(ep6_full), .C(n21), .Y(ep6_we) );
  and3d2 U141 ( .A(n20), .B(ep5_empty), .C(n183), .Y(ep5_re) );
  and3d2 U142 ( .A(n19), .B(ep5_full), .C(n183), .Y(ep5_we) );
  and3d2 U147 ( .A(n20), .B(ep4_empty), .C(n22), .Y(ep4_re) );
  and3d2 U148 ( .A(n19), .B(ep4_full), .C(n22), .Y(ep4_we) );
  and3d2 U154 ( .A(n20), .B(ep3_empty), .C(n23), .Y(ep3_re) );
  and3d2 U155 ( .A(n19), .B(ep3_full), .C(n23), .Y(ep3_we) );
  and3d2 U159 ( .A(n20), .B(ep2_empty), .C(n24), .Y(ep2_re) );
  and3d2 U160 ( .A(n19), .B(ep2_full), .C(n24), .Y(ep2_we) );
  and3d2 U164 ( .A(n20), .B(ep1_empty), .C(n25), .Y(ep1_re) );
  and3d2 U165 ( .A(n19), .B(ep1_full), .C(n25), .Y(ep1_we) );
  or3d3 U169 ( .A(n31), .B(n32), .C(n33), .Y(cfg[8]) );
  oa1f3 U170 ( .A(ep1_cfg[8]), .B(n7), .C(n34), .Y(n33) );
  or3d3 U174 ( .A(n40), .B(n41), .C(n42), .Y(cfg[6]) );
  and2a3 U175 ( .A(n43), .B(n44), .Y(n42) );
  or3d3 U179 ( .A(n60), .B(n61), .C(n62), .Y(cfg[2]) );
  and2a3 U180 ( .A(n63), .B(n64), .Y(n62) );
  or3d3 U184 ( .A(n55), .B(n56), .C(n57), .Y(cfg[3]) );
  and2a3 U185 ( .A(n58), .B(n59), .Y(n57) );
  or3d3 U189 ( .A(n65), .B(n66), .C(n67), .Y(cfg[1]) );
  and2a3 U190 ( .A(n68), .B(n69), .Y(n67) );
  or3d3 U194 ( .A(n35), .B(n36), .C(n37), .Y(cfg[7]) );
  or2c1 U195 ( .A(ep1_cfg[7]), .B(n7), .Y(n35) );
  and2a3 U197 ( .A(n38), .B(n39), .Y(n37) );
  and2a3 U199 ( .A(n89), .B(n90), .Y(n88) );
  oa2i2 U200 ( .A(ep7_cfg[13]), .B(n179), .C(n73), .D(n187), .Y(n72) );
  or3d1 U202 ( .A(n50), .B(n51), .C(n52), .Y(cfg[4]) );
  and2a3 U204 ( .A(n53), .B(n54), .Y(n52) );
  or3d1 U206 ( .A(n45), .B(n46), .C(n47), .Y(cfg[5]) );
  and2a3 U208 ( .A(n48), .B(n49), .Y(n47) );
  clk1a15 U209 ( .A(clk_i), .Y(n185) );
  inv1a3 U210 ( .A(ep_sel[3]), .Y(n195) );
  or3d1 U211 ( .A(n91), .B(n92), .C(n93), .Y(N93) );
  and2a3 U212 ( .A(n94), .B(n95), .Y(n93) );
  or3d1 U213 ( .A(n96), .B(n97), .C(n98), .Y(N92) );
  and2a3 U214 ( .A(n99), .B(n100), .Y(n98) );
  or3d1 U215 ( .A(n101), .B(n102), .C(n103), .Y(N91) );
  and2a3 U216 ( .A(n104), .B(n105), .Y(n103) );
  or3d1 U217 ( .A(n106), .B(n107), .C(n108), .Y(N90) );
  and2a3 U218 ( .A(n109), .B(n110), .Y(n108) );
  or3d1 U219 ( .A(n111), .B(n112), .C(n113), .Y(N89) );
  and2a3 U220 ( .A(n114), .B(n115), .Y(n113) );
  or3d1 U221 ( .A(n116), .B(n117), .C(n118), .Y(N88) );
  and2a3 U222 ( .A(n119), .B(n120), .Y(n118) );
  or3d1 U223 ( .A(n121), .B(n122), .C(n123), .Y(N87) );
  and2a3 U224 ( .A(n124), .B(n125), .Y(n123) );
  or3d1 U225 ( .A(n126), .B(n127), .C(n128), .Y(N86) );
  and2a3 U226 ( .A(n129), .B(n130), .Y(n128) );
  or3d1 U227 ( .A(n166), .B(n167), .C(n168), .Y(N116) );
  oa2i2 U228 ( .A(ep6_empty), .B(n3), .C(n169), .D(n170), .Y(n168) );
  or3d1 U229 ( .A(n162), .B(n163), .C(n164), .Y(N161) );
  oa1f3 U230 ( .A(ep1_bf_en), .B(n7), .C(n165), .Y(n164) );
  or3d1 U231 ( .A(n154), .B(n155), .C(n156), .Y(N186) );
  oa1f3 U232 ( .A(ep1_bf_size[1]), .B(n134), .C(n157), .Y(n156) );
  or3d1 U233 ( .A(n150), .B(n151), .C(n152), .Y(N187) );
  oa1f3 U234 ( .A(ep1_bf_size[2]), .B(n134), .C(n153), .Y(n152) );
  or3d1 U235 ( .A(n146), .B(n147), .C(n148), .Y(N188) );
  oa1f3 U236 ( .A(ep1_bf_size[3]), .B(n134), .C(n149), .Y(n148) );
  or3d1 U237 ( .A(n142), .B(n143), .C(n144), .Y(N189) );
  oa1f3 U238 ( .A(ep1_bf_size[4]), .B(n134), .C(n145), .Y(n144) );
  or3d1 U239 ( .A(n138), .B(n139), .C(n140), .Y(N190) );
  oa1f3 U240 ( .A(ep1_bf_size[5]), .B(n134), .C(n141), .Y(n140) );
  or3d1 U241 ( .A(n131), .B(n132), .C(n133), .Y(N191) );
  oa1f3 U242 ( .A(ep1_bf_size[6]), .B(n134), .C(n135), .Y(n133) );
  or3d1 U243 ( .A(n158), .B(n159), .C(n160), .Y(N185) );
  oa1f3 U244 ( .A(ep1_bf_size[0]), .B(n134), .C(n161), .Y(n160) );
  or3a3 U245 ( .A(n188), .B(ep_sel[1]), .C(n194), .Y(n1) );
endmodule


module bit_register_RESET_DEFAULT0_0 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_16 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_15 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_14 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_13 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module generic_register_WD5_RESET_DEFAULT0 ( we, data_in, reset_n, clk, 
        data_out );
  input [4:0] we;
  input [4:0] data_in;
  output [4:0] data_out;
  input reset_n, clk;
  wire   n1, n2;

  bit_register_RESET_DEFAULT0_0 \gen_bit_reg[0].u_bit_reg  ( .we(we[0]), .clk(
        n2), .reset_n(n1), .data_in(data_in[0]), .data_out(data_out[0]) );
  bit_register_RESET_DEFAULT0_16 \gen_bit_reg[1].u_bit_reg  ( .we(we[1]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[1]), .data_out(data_out[1])
         );
  bit_register_RESET_DEFAULT0_15 \gen_bit_reg[2].u_bit_reg  ( .we(we[2]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[2]), .data_out(data_out[2])
         );
  bit_register_RESET_DEFAULT0_14 \gen_bit_reg[3].u_bit_reg  ( .we(we[3]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[3]), .data_out(data_out[3])
         );
  bit_register_RESET_DEFAULT0_13 \gen_bit_reg[4].u_bit_reg  ( .we(we[4]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[4]), .data_out(data_out[4])
         );
  clk1a3 U1 ( .A(reset_n), .Y(n1) );
  clk1a3 U2 ( .A(clk), .Y(n2) );
endmodule


module stat_register_0 ( clk, reset_n, cpu_we, cpu_ack, hware_req, data_out );
  input clk, reset_n, cpu_we, cpu_ack, hware_req;
  output data_out;
  wire   n2, n3, n1;

  fdf2a3 data_out_reg ( .D(n1), .CLK(clk), .CLR(reset_n), .Q(data_out) );
  inv1a1 U2 ( .A(n2), .Y(n1) );
  oa1f3 U3 ( .A(data_out), .B(n3), .C(hware_req), .Y(n2) );
  or2c1 U4 ( .A(cpu_we), .B(cpu_ack), .Y(n3) );
endmodule


module stat_register_2 ( clk, reset_n, cpu_we, cpu_ack, hware_req, data_out );
  input clk, reset_n, cpu_we, cpu_ack, hware_req;
  output data_out;
  wire   n1, n4, n5;

  fdf2a3 data_out_reg ( .D(n1), .CLK(clk), .CLR(reset_n), .Q(data_out) );
  inv1a1 U2 ( .A(n5), .Y(n1) );
  oa1f3 U3 ( .A(data_out), .B(n4), .C(hware_req), .Y(n5) );
  or2c1 U4 ( .A(cpu_we), .B(cpu_ack), .Y(n4) );
endmodule


module stat_register_1 ( clk, reset_n, cpu_we, cpu_ack, hware_req, data_out );
  input clk, reset_n, cpu_we, cpu_ack, hware_req;
  output data_out;
  wire   n1, n4, n5;

  fdf2a3 data_out_reg ( .D(n1), .CLK(clk), .CLR(reset_n), .Q(data_out) );
  inv1a1 U2 ( .A(n5), .Y(n1) );
  oa1f3 U3 ( .A(data_out), .B(n4), .C(hware_req), .Y(n5) );
  or2c1 U4 ( .A(cpu_we), .B(cpu_ack), .Y(n4) );
endmodule


module bit_register_RESET_DEFAULT0_12 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_11 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_10 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_9 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_8 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_7 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_6 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_5 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_4 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_3 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_2 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module bit_register_RESET_DEFAULT0_1 ( we, clk, reset_n, data_in, data_out );
  input we, clk, reset_n, data_in;
  output data_out;


  fdef2a3 data_out_reg ( .D(data_in), .E(we), .CLK(clk), .CLR(reset_n), .Q(
        data_out) );
endmodule


module generic_register_WD12_RESET_DEFAULT0 ( we, data_in, reset_n, clk, 
        data_out );
  input [11:0] we;
  input [11:0] data_in;
  output [11:0] data_out;
  input reset_n, clk;
  wire   n1, n2;

  bit_register_RESET_DEFAULT0_12 \gen_bit_reg[0].u_bit_reg  ( .we(we[0]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[0]), .data_out(data_out[0])
         );
  bit_register_RESET_DEFAULT0_11 \gen_bit_reg[1].u_bit_reg  ( .we(we[1]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[1]), .data_out(data_out[1])
         );
  bit_register_RESET_DEFAULT0_10 \gen_bit_reg[2].u_bit_reg  ( .we(we[2]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[2]), .data_out(data_out[2])
         );
  bit_register_RESET_DEFAULT0_9 \gen_bit_reg[3].u_bit_reg  ( .we(we[3]), .clk(
        n2), .reset_n(n1), .data_in(data_in[3]), .data_out(data_out[3]) );
  bit_register_RESET_DEFAULT0_8 \gen_bit_reg[4].u_bit_reg  ( .we(we[4]), .clk(
        n2), .reset_n(n1), .data_in(data_in[4]), .data_out(data_out[4]) );
  bit_register_RESET_DEFAULT0_7 \gen_bit_reg[5].u_bit_reg  ( .we(we[5]), .clk(
        n2), .reset_n(n1), .data_in(data_in[5]), .data_out(data_out[5]) );
  bit_register_RESET_DEFAULT0_6 \gen_bit_reg[6].u_bit_reg  ( .we(we[6]), .clk(
        n2), .reset_n(n1), .data_in(data_in[6]), .data_out(data_out[6]) );
  bit_register_RESET_DEFAULT0_5 \gen_bit_reg[7].u_bit_reg  ( .we(we[7]), .clk(
        n2), .reset_n(n1), .data_in(data_in[7]), .data_out(data_out[7]) );
  bit_register_RESET_DEFAULT0_4 \gen_bit_reg[8].u_bit_reg  ( .we(we[8]), .clk(
        n2), .reset_n(n1), .data_in(data_in[8]), .data_out(data_out[8]) );
  bit_register_RESET_DEFAULT0_3 \gen_bit_reg[9].u_bit_reg  ( .we(we[9]), .clk(
        n2), .reset_n(n1), .data_in(data_in[9]), .data_out(data_out[9]) );
  bit_register_RESET_DEFAULT0_2 \gen_bit_reg[10].u_bit_reg  ( .we(we[10]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[10]), .data_out(data_out[10])
         );
  bit_register_RESET_DEFAULT0_1 \gen_bit_reg[11].u_bit_reg  ( .we(we[11]), 
        .clk(n2), .reset_n(n1), .data_in(data_in[11]), .data_out(data_out[11])
         );
  buf1a9 U1 ( .A(reset_n), .Y(n1) );
  clk1a6 U2 ( .A(clk), .Y(n2) );
endmodule


module uart_cfg ( mclk, reset_n, reg_cs, reg_wr, reg_addr, reg_wdata, reg_be, 
        reg_rdata, reg_ack, tx_fifo_full, tx_fifo_wr_en, tx_fifo_data, 
        rx_fifo_empty, rx_fifo_rd_en, rx_fifo_data, cfg_tx_enable, 
        cfg_rx_enable, cfg_stop_bit, cfg_pri_mod, cfg_baud_16x, frm_error_o, 
        par_error_o, rx_fifo_full_err_o );
  input [3:0] reg_addr;
  input [31:0] reg_wdata;
  input [3:0] reg_be;
  output [31:0] reg_rdata;
  output [7:0] tx_fifo_data;
  input [7:0] rx_fifo_data;
  output [1:0] cfg_pri_mod;
  output [11:0] cfg_baud_16x;
  input mclk, reset_n, reg_cs, reg_wr, tx_fifo_full, rx_fifo_empty,
         frm_error_o, par_error_o, rx_fifo_full_err_o;
  output reg_ack, tx_fifo_wr_en, rx_fifo_rd_en, cfg_tx_enable, cfg_rx_enable,
         cfg_stop_bit;
  wire   N11, N13, \_0_net_[4] , _3_net_, \_4_net_[9] , n6, n7, n8, n9, n10,
         n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24,
         n1, n2, n3, n4, n5, n25, n26;
  wire   [31:0] reg_out;
  wire   [2:0] reg_1;
  assign tx_fifo_data[7] = reg_wdata[7];
  assign tx_fifo_data[6] = reg_wdata[6];
  assign tx_fifo_data[5] = reg_wdata[5];
  assign tx_fifo_data[4] = reg_wdata[4];
  assign tx_fifo_data[3] = reg_wdata[3];
  assign tx_fifo_data[2] = reg_wdata[2];
  assign tx_fifo_data[1] = reg_wdata[1];
  assign tx_fifo_data[0] = reg_wdata[0];
  assign reg_rdata[31] = 1'b0;
  assign reg_rdata[30] = 1'b0;
  assign reg_rdata[29] = 1'b0;
  assign reg_rdata[28] = 1'b0;
  assign reg_rdata[27] = 1'b0;
  assign reg_rdata[26] = 1'b0;
  assign reg_rdata[25] = 1'b0;
  assign reg_rdata[24] = 1'b0;
  assign reg_rdata[23] = 1'b0;
  assign reg_rdata[22] = 1'b0;
  assign reg_rdata[21] = 1'b0;
  assign reg_rdata[20] = 1'b0;
  assign reg_rdata[19] = 1'b0;
  assign reg_rdata[18] = 1'b0;
  assign reg_rdata[17] = 1'b0;
  assign reg_rdata[16] = 1'b0;
  assign reg_rdata[15] = 1'b0;
  assign reg_rdata[14] = 1'b0;
  assign reg_rdata[13] = 1'b0;
  assign reg_rdata[12] = 1'b0;

  ao4a3 U27 ( .A(cfg_baud_16x[7]), .B(n8), .C(rx_fifo_data[7]), .D(n25), .Y(
        reg_out[7]) );
  ao4a3 U28 ( .A(cfg_baud_16x[6]), .B(n8), .C(rx_fifo_data[6]), .D(n25), .Y(
        reg_out[6]) );
  ao4a3 U29 ( .A(cfg_baud_16x[5]), .B(n8), .C(rx_fifo_data[5]), .D(n25), .Y(
        reg_out[5]) );
  oa4f3 U31 ( .A(rx_fifo_data[4]), .B(n25), .C(cfg_baud_16x[4]), .D(n8), .Y(
        n10) );
  oa4f3 U33 ( .A(rx_fifo_data[3]), .B(n25), .C(cfg_baud_16x[3]), .D(n8), .Y(
        n11) );
  oa4f3 U35 ( .A(rx_fifo_data[2]), .B(n25), .C(cfg_baud_16x[2]), .D(n8), .Y(
        n13) );
  oa4f3 U38 ( .A(reg_1[1]), .B(n14), .C(cfg_rx_enable), .D(n9), .Y(n17) );
  oa4f3 U40 ( .A(rx_fifo_empty), .B(n18), .C(rx_fifo_data[1]), .D(n25), .Y(n15) );
  oa4f3 U44 ( .A(reg_1[0]), .B(n14), .C(cfg_tx_enable), .D(n9), .Y(n21) );
  oa4f3 U46 ( .A(tx_fifo_full), .B(n18), .C(rx_fifo_data[0]), .D(n25), .Y(n19)
         );
  and2b2 U53 ( .B(n22), .A(reg_addr[2]), .Y(n14) );
  and2b2 U56 ( .B(n6), .A(reg_addr[2]), .Y(n9) );
  generic_register_WD5_RESET_DEFAULT0 u_uart_ctrl_be0 ( .we({\_0_net_[4] , 
        \_0_net_[4] , \_0_net_[4] , \_0_net_[4] , \_0_net_[4] }), .data_in(
        reg_wdata[4:0]), .reset_n(n2), .clk(n3), .data_out({cfg_pri_mod, 
        cfg_stop_bit, cfg_rx_enable, cfg_tx_enable}) );
  stat_register_0 u_intr_bit0 ( .clk(n3), .reset_n(n2), .cpu_we(_3_net_), 
        .cpu_ack(reg_wdata[0]), .hware_req(frm_error_o), .data_out(reg_1[0])
         );
  stat_register_2 u_intr_bit1 ( .clk(n3), .reset_n(n2), .cpu_we(_3_net_), 
        .cpu_ack(reg_wdata[1]), .hware_req(par_error_o), .data_out(reg_1[1])
         );
  stat_register_1 u_intr_bit2 ( .clk(n3), .reset_n(n2), .cpu_we(_3_net_), 
        .cpu_ack(reg_wdata[2]), .hware_req(rx_fifo_full_err_o), .data_out(
        reg_1[2]) );
  generic_register_WD12_RESET_DEFAULT0 u_uart_ctrl_reg2 ( .we({\_4_net_[9] , 
        \_4_net_[9] , \_4_net_[9] , \_4_net_[9] , \_4_net_[9] , \_4_net_[9] , 
        \_4_net_[9] , \_4_net_[9] , \_4_net_[9] , \_4_net_[9] , \_4_net_[9] , 
        \_4_net_[9] }), .data_in(reg_wdata[11:0]), .reset_n(n2), .clk(n3), 
        .data_out(cfg_baud_16x) );
  fdf2a3 reg_ack_reg ( .D(N13), .CLK(n3), .CLR(n2), .Q(reg_ack) );
  fdef2a3 \reg_rdata_reg[11]  ( .D(reg_out[11]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[11]) );
  fdef2a3 \reg_rdata_reg[10]  ( .D(reg_out[10]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[10]) );
  fdef2a3 \reg_rdata_reg[9]  ( .D(reg_out[9]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[9]) );
  fdef2a3 \reg_rdata_reg[8]  ( .D(reg_out[8]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[8]) );
  fdef2a3 \reg_rdata_reg[7]  ( .D(reg_out[7]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[7]) );
  fdef2a3 \reg_rdata_reg[6]  ( .D(reg_out[6]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[6]) );
  fdef2a3 \reg_rdata_reg[5]  ( .D(reg_out[5]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[5]) );
  fdef2a3 \reg_rdata_reg[4]  ( .D(reg_out[4]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[4]) );
  fdef2a3 \reg_rdata_reg[3]  ( .D(reg_out[3]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[3]) );
  fdef2a3 \reg_rdata_reg[2]  ( .D(reg_out[2]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[2]) );
  fdef2a3 \reg_rdata_reg[1]  ( .D(reg_out[1]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[1]) );
  fdef2a3 \reg_rdata_reg[0]  ( .D(reg_out[0]), .E(N11), .CLK(n3), .CLR(n2), 
        .Q(reg_rdata[0]) );
  or3a3 U23 ( .A(reg_ack), .B(reg_wr), .C(n5), .Y(n1) );
  oa4f1 U24 ( .A(reg_1[2]), .B(n14), .C(cfg_stop_bit), .D(n9), .Y(n12) );
  clk1b6 U25 ( .A(n1), .Y(N11) );
  or2c1 U26 ( .A(reg_wr), .B(reg_cs), .Y(n24) );
  inv1a1 U30 ( .A(reg_cs), .Y(n5) );
  inv1a1 U32 ( .A(reg_addr[0]), .Y(n26) );
  inv1a3 U34 ( .A(n24), .Y(n4) );
  clk1a15 U36 ( .A(reset_n), .Y(n2) );
  clk1a6 U37 ( .A(mclk), .Y(n3) );
  and3d2 U39 ( .A(n7), .B(reg_wr), .C(n5), .Y(rx_fifo_rd_en) );
  and3a2 U41 ( .A(n9), .B(n4), .C(reg_be[0]), .Y(\_0_net_[4] ) );
  and3a2 U42 ( .A(n14), .B(n4), .C(reg_be[0]), .Y(_3_net_) );
  and3d2 U43 ( .A(reg_addr[1]), .B(reg_addr[3]), .C(n26), .Y(n22) );
  and3d2 U45 ( .A(reg_addr[1]), .B(reg_addr[3]), .C(reg_addr[0]), .Y(n6) );
  and3a6 U47 ( .A(reg_addr[1]), .B(n26), .C(n23), .Y(n8) );
  and2c3 U48 ( .A(reg_addr[3]), .B(reg_addr[2]), .Y(n23) );
  and3a6 U49 ( .A(n8), .B(n4), .C(reg_be[0]), .Y(\_4_net_[9] ) );
  ao1f2 U50 ( .A(reg_ack), .B(n24), .C(n1), .Y(N13) );
  and3a2 U51 ( .A(reg_addr[1]), .B(reg_addr[0]), .C(n23), .Y(n18) );
  ao1d1 U52 ( .A(cfg_pri_mod[0]), .B(n9), .C(n11), .Y(reg_out[3]) );
  ao1d1 U54 ( .A(cfg_pri_mod[1]), .B(n9), .C(n10), .Y(reg_out[4]) );
  or2c3 U55 ( .A(n22), .B(reg_addr[2]), .Y(n7) );
  or3d1 U57 ( .A(n19), .B(n20), .C(n21), .Y(reg_out[0]) );
  or2c1 U58 ( .A(cfg_baud_16x[0]), .B(n8), .Y(n20) );
  or3d1 U59 ( .A(n15), .B(n16), .C(n17), .Y(reg_out[1]) );
  or2c1 U60 ( .A(cfg_baud_16x[1]), .B(n8), .Y(n16) );
  or2c1 U61 ( .A(n12), .B(n13), .Y(reg_out[2]) );
  and2a3 U62 ( .A(cfg_baud_16x[8]), .B(n8), .Y(reg_out[8]) );
  and2a3 U63 ( .A(cfg_baud_16x[9]), .B(n8), .Y(reg_out[9]) );
  and2a3 U64 ( .A(cfg_baud_16x[10]), .B(n8), .Y(reg_out[10]) );
  and2a3 U65 ( .A(cfg_baud_16x[11]), .B(n8), .Y(reg_out[11]) );
  and3a2 U66 ( .A(reg_addr[2]), .B(n6), .C(n4), .Y(tx_fifo_wr_en) );
  clk1b6 U67 ( .A(n7), .Y(n25) );
endmodule


module clk_ctl_WD11_DW01_inc_0 ( A, SUM );
  input [10:0] A;
  output [10:0] SUM;

  wire   [10:2] carry;

  ha1a2 U1_1_9 ( .A(A[9]), .B(carry[9]), .CO(carry[10]), .S(SUM[9]) );
  ha1a2 U1_1_8 ( .A(A[8]), .B(carry[8]), .CO(carry[9]), .S(SUM[8]) );
  ha1a2 U1_1_7 ( .A(A[7]), .B(carry[7]), .CO(carry[8]), .S(SUM[7]) );
  ha1a2 U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
  ha1a2 U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
  ha1a2 U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
  ha1a2 U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
  ha1a2 U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
  ha1a2 U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
  inv1a1 U1 ( .A(A[0]), .Y(SUM[0]) );
  xor2a1 U2 ( .A(carry[10]), .B(A[10]), .Y(SUM[10]) );
endmodule


module clk_ctl_WD11 ( clk_o, mclk, reset_n, clk_div_ratio );
  input [11:0] clk_div_ratio;
  input mclk, reset_n;
  output clk_o;
  wire   N4, N5, N6, N7, N8, N9, N10, N12, N13, N14, N16, N17, N18, N19, N20,
         N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, N32, N33, N34,
         N35, N36, N37, N38, N39, N40, N41, N42, N43, N44, N45, N46, N47, N48,
         N62, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
         n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
         n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
         n55, n56, n57, n58, \add_115/carry[10] , \add_115/carry[9] ,
         \add_115/carry[8] , \add_115/carry[7] , \add_115/carry[6] ,
         \add_115/carry[5] , \add_115/carry[4] , \add_115/carry[3] ,
         \add_115/carry[2] , \add_115/carry[1] , n1, n2, n3, n4, n5, n6, n7,
         n8, n9, n10, n11, n12, n13, n59, n60, n61, n62, n63, n64, n65, n66,
         n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80,
         n81, n82, n83, n84, n85, n86;
  wire   [10:0] high_count;
  wire   [10:0] low_count;

  oa4f3 U4 ( .A(N47), .B(n16), .C(N25), .D(n6), .Y(n15) );
  oa4f3 U7 ( .A(N46), .B(n16), .C(N24), .D(n14), .Y(n17) );
  oa4f3 U9 ( .A(N45), .B(n16), .C(N23), .D(n6), .Y(n18) );
  oa4f3 U11 ( .A(N44), .B(n16), .C(N22), .D(n14), .Y(n19) );
  oa4f3 U13 ( .A(N43), .B(n16), .C(N21), .D(n6), .Y(n20) );
  oa4f3 U15 ( .A(N42), .B(n16), .C(N20), .D(n14), .Y(n21) );
  oa4f3 U17 ( .A(N41), .B(n16), .C(N19), .D(n6), .Y(n22) );
  oa4f3 U19 ( .A(N40), .B(n16), .C(N18), .D(n14), .Y(n23) );
  oa4f3 U21 ( .A(N39), .B(n16), .C(N17), .D(n6), .Y(n24) );
  oa4f3 U23 ( .A(N38), .B(n16), .C(N16), .D(n14), .Y(n25) );
  oa4f3 U25 ( .A(N48), .B(n16), .C(N26), .D(n6), .Y(n26) );
  clk_ctl_WD11_DW01_inc_0 add_116 ( .A(clk_div_ratio[11:1]), .SUM({N48, N47, 
        N46, N45, N44, N43, N42, N41, N40, N39, N38}) );
  fdf2a3 \high_count_reg[10]  ( .D(n57), .CLK(n10), .CLR(n8), .Q(
        high_count[10]) );
  fdf2a3 mclk_div_reg ( .D(N62), .CLK(n11), .CLR(reset_n), .Q(clk_o) );
  fdf2a3 \high_count_reg[0]  ( .D(n58), .CLK(n9), .CLR(n7), .Q(high_count[0])
         );
  fdf2a3 \low_count_reg[1]  ( .D(n45), .CLK(n9), .CLR(n7), .Q(low_count[1]) );
  fdf2a3 \low_count_reg[2]  ( .D(n44), .CLK(n9), .CLR(n7), .Q(low_count[2]) );
  fdf2a3 \low_count_reg[3]  ( .D(n43), .CLK(n9), .CLR(n7), .Q(low_count[3]) );
  fdf2a3 \high_count_reg[1]  ( .D(n56), .CLK(n10), .CLR(n8), .Q(high_count[1])
         );
  fdf2a3 \high_count_reg[2]  ( .D(n55), .CLK(n10), .CLR(n8), .Q(high_count[2])
         );
  fdf2a3 \high_count_reg[3]  ( .D(n54), .CLK(n10), .CLR(n8), .Q(high_count[3])
         );
  fdf2a3 \high_count_reg[4]  ( .D(n53), .CLK(n10), .CLR(n8), .Q(high_count[4])
         );
  fdf2a3 \high_count_reg[5]  ( .D(n52), .CLK(n10), .CLR(n8), .Q(high_count[5])
         );
  fdf2a3 \high_count_reg[6]  ( .D(n51), .CLK(n11), .CLR(n8), .Q(high_count[6])
         );
  fdf2a3 \high_count_reg[7]  ( .D(n50), .CLK(n11), .CLR(n8), .Q(high_count[7])
         );
  fdf2a3 \high_count_reg[8]  ( .D(n49), .CLK(n11), .CLR(n8), .Q(high_count[8])
         );
  fdf2a3 \high_count_reg[9]  ( .D(n48), .CLK(n11), .CLR(n8), .Q(high_count[9])
         );
  fdf2a3 \low_count_reg[4]  ( .D(n42), .CLK(n9), .CLR(n7), .Q(low_count[4]) );
  fdf2a3 \low_count_reg[5]  ( .D(n41), .CLK(n9), .CLR(n7), .Q(low_count[5]) );
  fdf2a3 \low_count_reg[6]  ( .D(n40), .CLK(n9), .CLR(n7), .Q(low_count[6]) );
  fdf2a3 \low_count_reg[7]  ( .D(n39), .CLK(n10), .CLR(n7), .Q(low_count[7])
         );
  fdf2a3 \low_count_reg[10]  ( .D(n47), .CLK(n9), .CLR(n7), .Q(low_count[10])
         );
  fdf2a3 \low_count_reg[8]  ( .D(n38), .CLK(n10), .CLR(n7), .Q(low_count[8])
         );
  fdf2a3 \low_count_reg[9]  ( .D(n37), .CLK(n10), .CLR(n8), .Q(low_count[9])
         );
  fdf2a3 \low_count_reg[0]  ( .D(n46), .CLK(n9), .CLR(n7), .Q(low_count[0]) );
  inv1a1 U3 ( .A(high_count[8]), .Y(n66) );
  and3d2 U5 ( .A(high_count[4]), .B(high_count[6]), .C(high_count[5]), .Y(n29)
         );
  and2c1 U6 ( .A(n72), .B(low_count[6]), .Y(n1) );
  inv1a2 U8 ( .A(n1), .Y(n2) );
  and2c1 U10 ( .A(n62), .B(high_count[6]), .Y(n3) );
  inv1a2 U12 ( .A(n3), .Y(n4) );
  and2c3 U14 ( .A(low_count[9]), .B(n75), .Y(n67) );
  and2c3 U16 ( .A(high_count[9]), .B(n65), .Y(n12) );
  or2c3 U18 ( .A(n74), .B(n76), .Y(n75) );
  and2c2 U20 ( .A(n2), .B(low_count[7]), .Y(n74) );
  or2c3 U22 ( .A(n64), .B(n66), .Y(n65) );
  and2c2 U24 ( .A(n4), .B(high_count[7]), .Y(n64) );
  inv1a9 U26 ( .A(n5), .Y(n16) );
  or2a1 U27 ( .A(n27), .B(n28), .Y(n5) );
  ao1f1 U28 ( .A(n14), .B(n81), .C(n22), .Y(n43) );
  ao1f1 U29 ( .A(n6), .B(n80), .C(n23), .Y(n44) );
  ao1f1 U30 ( .A(n14), .B(n79), .C(n24), .Y(n45) );
  ao1f1 U31 ( .A(n14), .B(n86), .C(n15), .Y(n37) );
  ao1f1 U32 ( .A(n6), .B(n76), .C(n17), .Y(n38) );
  ao1f1 U33 ( .A(n14), .B(n85), .C(n18), .Y(n39) );
  ao1f1 U34 ( .A(n14), .B(n77), .C(n26), .Y(n47) );
  ao4a1 U35 ( .A(N14), .B(n28), .C(N37), .D(n16), .Y(n57) );
  ao4a1 U36 ( .A(N13), .B(n28), .C(N36), .D(n16), .Y(n48) );
  ao4a1 U37 ( .A(N12), .B(n28), .C(N35), .D(n16), .Y(n49) );
  ao4a1 U38 ( .A(N10), .B(n28), .C(N33), .D(n16), .Y(n51) );
  ao4a1 U39 ( .A(N9), .B(n28), .C(N32), .D(n16), .Y(n52) );
  ao4a1 U40 ( .A(N8), .B(n28), .C(N31), .D(n16), .Y(n53) );
  ao4a1 U41 ( .A(N7), .B(n28), .C(N30), .D(n16), .Y(n54) );
  ao4a1 U42 ( .A(N6), .B(n28), .C(N29), .D(n16), .Y(n55) );
  ao4a1 U43 ( .A(N5), .B(n28), .C(N28), .D(n16), .Y(n56) );
  ao4a1 U44 ( .A(N4), .B(n28), .C(N27), .D(n16), .Y(n58) );
  ao1b2 U45 ( .B(n16), .A(clk_o), .C(n28), .Y(N62) );
  ao4b1 U46 ( .C(N34), .D(n16), .B(n28), .A(n63), .Y(n50) );
  or3d6 U47 ( .A(n29), .B(n30), .C(n31), .Y(n28) );
  and3c1 U48 ( .C(n32), .A(high_count[10]), .B(high_count[0]), .Y(n31) );
  and3d2 U49 ( .A(high_count[7]), .B(high_count[9]), .C(high_count[8]), .Y(n30) );
  inv1a1 U50 ( .A(low_count[1]), .Y(n79) );
  inv1a1 U51 ( .A(low_count[3]), .Y(n81) );
  inv1a1 U52 ( .A(low_count[2]), .Y(n80) );
  and2b6 U53 ( .B(n27), .A(n28), .Y(n14) );
  and2b6 U54 ( .B(n27), .A(n28), .Y(n6) );
  or3d1 U55 ( .A(n80), .B(n81), .C(n79), .Y(n36) );
  clk1a6 U56 ( .A(reset_n), .Y(n8) );
  clk1a6 U57 ( .A(reset_n), .Y(n7) );
  clk1a3 U58 ( .A(mclk), .Y(n10) );
  clk1a3 U59 ( .A(mclk), .Y(n9) );
  clk1a3 U60 ( .A(mclk), .Y(n11) );
  or3d3 U61 ( .A(n33), .B(n34), .C(n35), .Y(n27) );
  and3d2 U62 ( .A(low_count[4]), .B(low_count[6]), .C(low_count[5]), .Y(n33)
         );
  and3d2 U63 ( .A(low_count[7]), .B(low_count[9]), .C(low_count[8]), .Y(n34)
         );
  and3d2 U64 ( .A(n36), .B(low_count[10]), .C(low_count[0]), .Y(n35) );
  inv1a1 U65 ( .A(low_count[9]), .Y(n86) );
  inv1a1 U66 ( .A(low_count[7]), .Y(n85) );
  inv1a1 U67 ( .A(n73), .Y(N23) );
  ao1f2 U68 ( .A(n14), .B(n83), .C(n20), .Y(n41) );
  inv1a1 U69 ( .A(low_count[5]), .Y(n83) );
  inv1a1 U70 ( .A(low_count[10]), .Y(n77) );
  ao1f2 U71 ( .A(n6), .B(n84), .C(n19), .Y(n40) );
  inv1a1 U72 ( .A(low_count[6]), .Y(n84) );
  ao1f2 U73 ( .A(n6), .B(n82), .C(n21), .Y(n42) );
  inv1a1 U74 ( .A(low_count[4]), .Y(n82) );
  ao1f2 U75 ( .A(n6), .B(n78), .C(n25), .Y(n46) );
  inv1a1 U76 ( .A(low_count[0]), .Y(n78) );
  and3d2 U77 ( .A(high_count[1]), .B(high_count[3]), .C(high_count[2]), .Y(n32) );
  inv1a1 U78 ( .A(low_count[0]), .Y(N16) );
  inv1a1 U79 ( .A(high_count[0]), .Y(N4) );
  inv1a3 U80 ( .A(low_count[8]), .Y(n76) );
  xor2a1 U81 ( .A(clk_div_ratio[11]), .B(\add_115/carry[10] ), .Y(N37) );
  and2a1 U82 ( .A(\add_115/carry[9] ), .B(clk_div_ratio[10]), .Y(
        \add_115/carry[10] ) );
  xor2a1 U83 ( .A(clk_div_ratio[10]), .B(\add_115/carry[9] ), .Y(N36) );
  and2a1 U84 ( .A(\add_115/carry[8] ), .B(clk_div_ratio[9]), .Y(
        \add_115/carry[9] ) );
  xor2a1 U85 ( .A(clk_div_ratio[9]), .B(\add_115/carry[8] ), .Y(N35) );
  and2a1 U86 ( .A(\add_115/carry[7] ), .B(clk_div_ratio[8]), .Y(
        \add_115/carry[8] ) );
  xor2a1 U87 ( .A(clk_div_ratio[8]), .B(\add_115/carry[7] ), .Y(N34) );
  and2a1 U88 ( .A(\add_115/carry[6] ), .B(clk_div_ratio[7]), .Y(
        \add_115/carry[7] ) );
  xor2a1 U89 ( .A(clk_div_ratio[7]), .B(\add_115/carry[6] ), .Y(N33) );
  and2a1 U90 ( .A(\add_115/carry[5] ), .B(clk_div_ratio[6]), .Y(
        \add_115/carry[6] ) );
  xor2a1 U91 ( .A(clk_div_ratio[6]), .B(\add_115/carry[5] ), .Y(N32) );
  and2a1 U92 ( .A(\add_115/carry[4] ), .B(clk_div_ratio[5]), .Y(
        \add_115/carry[5] ) );
  xor2a1 U93 ( .A(clk_div_ratio[5]), .B(\add_115/carry[4] ), .Y(N31) );
  and2a1 U94 ( .A(\add_115/carry[3] ), .B(clk_div_ratio[4]), .Y(
        \add_115/carry[4] ) );
  xor2a1 U95 ( .A(clk_div_ratio[4]), .B(\add_115/carry[3] ), .Y(N30) );
  and2a1 U96 ( .A(\add_115/carry[2] ), .B(clk_div_ratio[3]), .Y(
        \add_115/carry[3] ) );
  xor2a1 U97 ( .A(clk_div_ratio[3]), .B(\add_115/carry[2] ), .Y(N29) );
  and2a1 U98 ( .A(\add_115/carry[1] ), .B(clk_div_ratio[2]), .Y(
        \add_115/carry[2] ) );
  xor2a1 U99 ( .A(clk_div_ratio[2]), .B(\add_115/carry[1] ), .Y(N28) );
  and2a1 U100 ( .A(clk_div_ratio[1]), .B(clk_div_ratio[0]), .Y(
        \add_115/carry[1] ) );
  xor2a1 U101 ( .A(clk_div_ratio[0]), .B(clk_div_ratio[1]), .Y(N27) );
  or2b1 U102 ( .B(high_count[1]), .A(N4), .Y(n13) );
  or2a1 U103 ( .A(n13), .B(high_count[2]), .Y(n59) );
  or2a1 U104 ( .A(n59), .B(high_count[3]), .Y(n60) );
  or2a1 U105 ( .A(n60), .B(high_count[4]), .Y(n61) );
  or2a1 U106 ( .A(n61), .B(high_count[5]), .Y(n62) );
  xor2a1 U107 ( .A(high_count[10]), .B(n12), .Y(N14) );
  ao1d1 U108 ( .A(high_count[0]), .B(high_count[1]), .C(n13), .Y(N5) );
  ao1d1 U109 ( .A(n13), .B(high_count[2]), .C(n59), .Y(N6) );
  ao1d1 U110 ( .A(n59), .B(high_count[3]), .C(n60), .Y(N7) );
  ao1d1 U111 ( .A(n60), .B(high_count[4]), .C(n61), .Y(N8) );
  ao1d1 U112 ( .A(n61), .B(high_count[5]), .C(n62), .Y(N9) );
  ao1d1 U113 ( .A(n62), .B(high_count[6]), .C(n4), .Y(N10) );
  oa1f1 U114 ( .A(n4), .B(high_count[7]), .C(n64), .Y(n63) );
  ao1f1 U115 ( .A(n64), .B(n66), .C(n65), .Y(N12) );
  xor2b1 U116 ( .A(high_count[9]), .B(n65), .Y(N13) );
  or2b1 U117 ( .B(low_count[1]), .A(N16), .Y(n68) );
  or2a1 U118 ( .A(n68), .B(low_count[2]), .Y(n69) );
  or2a1 U119 ( .A(n69), .B(low_count[3]), .Y(n70) );
  or2a1 U120 ( .A(n70), .B(low_count[4]), .Y(n71) );
  or2a1 U121 ( .A(n71), .B(low_count[5]), .Y(n72) );
  xor2a1 U122 ( .A(low_count[10]), .B(n67), .Y(N26) );
  ao1d1 U123 ( .A(low_count[0]), .B(low_count[1]), .C(n68), .Y(N17) );
  ao1d1 U124 ( .A(n68), .B(low_count[2]), .C(n69), .Y(N18) );
  ao1d1 U125 ( .A(n69), .B(low_count[3]), .C(n70), .Y(N19) );
  ao1d1 U126 ( .A(n70), .B(low_count[4]), .C(n71), .Y(N20) );
  ao1d1 U127 ( .A(n71), .B(low_count[5]), .C(n72), .Y(N21) );
  ao1d1 U128 ( .A(n72), .B(low_count[6]), .C(n2), .Y(N22) );
  oa1f1 U129 ( .A(n2), .B(low_count[7]), .C(n74), .Y(n73) );
  ao1f1 U130 ( .A(n74), .B(n76), .C(n75), .Y(N24) );
  xor2b1 U131 ( .A(low_count[9]), .B(n75), .Y(N25) );
endmodule


module uart_txfsm ( reset_n, baud_clk_16x, cfg_tx_enable, cfg_stop_bit, 
        cfg_pri_mod, fifo_empty, fifo_rd, fifo_data, so );
  input [1:0] cfg_pri_mod;
  input [7:0] fifo_data;
  input reset_n, baud_clk_16x, cfg_tx_enable, cfg_stop_bit, fifo_empty;
  output fifo_rd, so;
  wire   N15, N16, N17, N21, N22, N23, N43, n17, n18, n19, n20, n21, n22, n23,
         n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
         n38, n39, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52,
         n54, n55, n56, n57, n58, n59, n60, n61, n62, n1, n2, n3, n4, n5, n6,
         n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n40, n53, n63, n64,
         n65, n66, n67;
  wire   [3:0] divcnt;
  wire   [2:0] txstate;
  wire   [7:0] txdata;

  xor3b3 U11 ( .A(n30), .B(n31), .C(n32), .Y(n29) );
  or2b2 U12 ( .B(cfg_pri_mod[0]), .A(cfg_pri_mod[1]), .Y(n32) );
  xor3b3 U13 ( .A(txdata[5]), .B(txdata[4]), .C(n33), .Y(n31) );
  xor2a2 U14 ( .A(txdata[7]), .B(txdata[6]), .Y(n33) );
  xor3b3 U15 ( .A(txdata[1]), .B(txdata[0]), .C(n34), .Y(n30) );
  xor2a2 U16 ( .A(txdata[3]), .B(txdata[2]), .Y(n34) );
  ao1f6 U41 ( .A(n13), .B(n21), .C(n10), .Y(n36) );
  xor2a2 U48 ( .A(divcnt[3]), .B(n54), .Y(N23) );
  and2b2 U49 ( .B(divcnt[2]), .A(n55), .Y(n54) );
  xor2b2 U50 ( .A(divcnt[2]), .B(n55), .Y(N22) );
  xor2b2 U52 ( .A(divcnt[1]), .B(n12), .Y(N21) );
  fdef2a3 \txdata_reg[7]  ( .D(fifo_data[7]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[7]) );
  fdef2a3 \txdata_reg[3]  ( .D(fifo_data[3]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[3]) );
  fdef2a3 \txdata_reg[6]  ( .D(fifo_data[6]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[6]) );
  fdef2a3 \txdata_reg[2]  ( .D(fifo_data[2]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[2]) );
  fdef2a3 \txdata_reg[4]  ( .D(fifo_data[4]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[4]) );
  fdef2a3 \txdata_reg[0]  ( .D(fifo_data[0]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[0]) );
  fdf3a3 so_reg ( .D(n57), .CLK(n3), .PRE(n5), .Q(so) );
  fdef2a3 \txdata_reg[5]  ( .D(fifo_data[5]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[5]) );
  fdef2a3 \txdata_reg[1]  ( .D(fifo_data[1]), .E(n37), .CLK(n3), .CLR(n5), .Q(
        txdata[1]) );
  fdf2a3 \divcnt_reg[3]  ( .D(N23), .CLK(n4), .CLR(n6), .Q(divcnt[3]) );
  fdef2a3 \txstate_reg[0]  ( .D(n1), .E(n38), .CLK(n4), .CLR(n5), .Q(
        txstate[0]) );
  fdf2a3 \divcnt_reg[0]  ( .D(n12), .CLK(n3), .CLR(n6), .Q(divcnt[0]) );
  fdf2a3 \divcnt_reg[1]  ( .D(N21), .CLK(n4), .CLR(n6), .Q(divcnt[1]) );
  fdf2a3 \divcnt_reg[2]  ( .D(N22), .CLK(n4), .CLR(n6), .Q(divcnt[2]) );
  fdf2a3 \txstate_reg[2]  ( .D(n59), .CLK(n4), .CLR(n6), .Q(txstate[2]) );
  fdf2a3 \cnt_reg[2]  ( .D(n62), .CLK(n4), .CLR(n6), .Q(N17) );
  fdf2a3 \cnt_reg[1]  ( .D(n60), .CLK(n4), .CLR(n6), .Q(N16) );
  fdf2a3 \cnt_reg[0]  ( .D(n61), .CLK(n4), .CLR(n6), .Q(N15) );
  fdf2a3 \txstate_reg[1]  ( .D(n58), .CLK(n4), .CLR(n6), .Q(txstate[1]) );
  fdf2a6 fifo_rd_reg ( .D(n56), .CLK(n3), .CLR(n5), .Q(fifo_rd) );
  or3d3 U3 ( .A(n64), .B(n53), .C(txstate[0]), .Y(n21) );
  ao1f3 U4 ( .A(n44), .B(n13), .C(n10), .Y(n38) );
  and2c1 U5 ( .A(cfg_pri_mod[1]), .B(cfg_pri_mod[0]), .Y(n41) );
  ao2a2 U6 ( .A(n41), .B(n40), .C(n19), .D(n15), .Y(n1) );
  oa1f3 U7 ( .A(n35), .B(n20), .C(n36), .Y(n23) );
  and3d6 U8 ( .A(n2), .B(divcnt[0]), .C(divcnt[1]), .Y(n20) );
  and2c6 U9 ( .A(n22), .B(n13), .Y(n37) );
  or3d1 U10 ( .A(n63), .B(n53), .C(txstate[1]), .Y(n28) );
  or3d1 U17 ( .A(txstate[0]), .B(n53), .C(txstate[1]), .Y(n43) );
  inv1a1 U18 ( .A(n52), .Y(n9) );
  inv1a1 U19 ( .A(txstate[0]), .Y(n63) );
  inv1a3 U20 ( .A(n37), .Y(n10) );
  and3d2 U21 ( .A(n65), .B(n21), .C(n66), .Y(n45) );
  inv1a3 U22 ( .A(n21), .Y(n40) );
  inv1a3 U23 ( .A(n20), .Y(n13) );
  ao1f2 U24 ( .A(n36), .B(n65), .C(n49), .Y(n61) );
  or3d1 U25 ( .A(n36), .B(n65), .C(n40), .Y(n49) );
  or2a2 U26 ( .A(n26), .B(n15), .Y(n35) );
  ao1f2 U27 ( .A(n64), .B(n38), .C(n39), .Y(n58) );
  ao1f2 U28 ( .A(n15), .B(n40), .C(n38), .Y(n39) );
  ao1f2 U29 ( .A(n9), .B(n66), .C(n47), .Y(n60) );
  or3d1 U30 ( .A(n36), .B(n66), .C(n48), .Y(n47) );
  and2c1 U31 ( .A(n21), .B(n65), .Y(n48) );
  inv1a3 U32 ( .A(n28), .Y(n15) );
  buf1a9 U33 ( .A(reset_n), .Y(n5) );
  clk1a6 U34 ( .A(reset_n), .Y(n6) );
  clk1a6 U35 ( .A(baud_clk_16x), .Y(n3) );
  clk1a3 U36 ( .A(baud_clk_16x), .Y(n4) );
  oa1f3 U37 ( .A(N17), .B(n45), .C(n35), .Y(n44) );
  and3d3 U38 ( .A(txstate[1]), .B(txstate[2]), .C(txstate[0]), .Y(n19) );
  or2a2 U39 ( .A(divcnt[3]), .B(divcnt[2]), .Y(n2) );
  or3d3 U40 ( .A(n19), .B(n11), .C(cfg_tx_enable), .Y(n22) );
  inv1a1 U42 ( .A(fifo_empty), .Y(n11) );
  inv1a3 U43 ( .A(N15), .Y(n65) );
  inv1a3 U44 ( .A(txstate[2]), .Y(n53) );
  ao1f2 U45 ( .A(n53), .B(n38), .C(n42), .Y(n59) );
  or3d1 U46 ( .A(n16), .B(n38), .C(cfg_stop_bit), .Y(n42) );
  inv1a1 U47 ( .A(n43), .Y(n16) );
  ao1f2 U51 ( .A(n67), .B(n17), .C(n18), .Y(n56) );
  inv1a1 U53 ( .A(fifo_rd), .Y(n67) );
  or3d1 U54 ( .A(n19), .B(n17), .C(n20), .Y(n18) );
  or3d1 U55 ( .A(n21), .B(n22), .C(n20), .Y(n17) );
  inv1a3 U56 ( .A(N16), .Y(n66) );
  inv1a3 U57 ( .A(txstate[1]), .Y(n64) );
  ao1f2 U58 ( .A(n23), .B(n24), .C(n25), .Y(n57) );
  oa2i2 U59 ( .A(N43), .B(n40), .C(n26), .D(n27), .Y(n24) );
  or2c1 U60 ( .A(so), .B(n23), .Y(n25) );
  ao1d2 U61 ( .A(n50), .B(N17), .C(n51), .Y(n62) );
  or3d1 U62 ( .A(n36), .B(n14), .C(n45), .Y(n51) );
  ao1f2 U63 ( .A(n21), .B(N16), .C(n9), .Y(n50) );
  inv1a1 U64 ( .A(N17), .Y(n14) );
  ao1f1 U65 ( .A(N15), .B(n21), .C(n36), .Y(n52) );
  and2c3 U66 ( .A(n28), .B(n29), .Y(n27) );
  mx4e3 U67 ( .D0(txdata[0]), .D1(txdata[1]), .D2(txdata[2]), .D3(txdata[3]), 
        .S0(N15), .S1(N16), .Y(n7) );
  mx4e3 U68 ( .D0(txdata[4]), .D1(txdata[5]), .D2(txdata[6]), .D3(txdata[7]), 
        .S0(N15), .S1(N16), .Y(n8) );
  or2c1 U69 ( .A(n43), .B(n46), .Y(n26) );
  or3d1 U70 ( .A(n63), .B(n64), .C(txstate[2]), .Y(n46) );
  or2c1 U71 ( .A(divcnt[1]), .B(divcnt[0]), .Y(n55) );
  inv1a3 U72 ( .A(divcnt[0]), .Y(n12) );
  mx2d2 U73 ( .D0(n7), .D1(n8), .S(N17), .Y(N43) );
endmodule


module uart_rxfsm ( reset_n, baud_clk_16x, cfg_rx_enable, cfg_stop_bit, 
        cfg_pri_mod, error_ind, fifo_aval, fifo_wr, fifo_data, si );
  input [1:0] cfg_pri_mod;
  output [1:0] error_ind;
  output [7:0] fifo_data;
  input reset_n, baud_clk_16x, cfg_rx_enable, cfg_stop_bit, fifo_aval, si;
  output fifo_wr;
  wire   \offset[3] , N40, N41, N42, N66, N67, N68, N72, N82, N101, N127, N128,
         N129, N130, n17, n18, n42, n43, n44, n45, n46, n47, n48, n49, n50,
         n51, n52, n53, n54, n55, n56, n57, n58, n60, n61, n63, n66, n67, n71,
         n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
         n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
         n100, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14,
         n15, n16, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
         n31;
  wire   [2:0] rxstate;
  wire   [2:0] cnt;
  wire   [3:0] rxpos;

  mx2d2 U3 ( .D0(n17), .D1(n18), .S(rxstate[2]), .Y(N127) );
  or2b2 U5 ( .B(rxstate[1]), .A(n21), .Y(n18) );
  ao2i3 U14 ( .A(n42), .B(n43), .C(n44), .D(n45), .Y(n95) );
  ao2i3 U16 ( .A(n46), .B(n42), .C(n45), .D(n47), .Y(n96) );
  oa1d3 U19 ( .A(n49), .B(n50), .C(n24), .Y(n42) );
  xor3b3 U22 ( .A(n53), .B(n54), .C(n55), .Y(n52) );
  xor3b3 U23 ( .A(fifo_data[1]), .B(fifo_data[0]), .C(n56), .Y(n55) );
  xor2a2 U24 ( .A(fifo_data[3]), .B(fifo_data[2]), .Y(n56) );
  xor3b3 U25 ( .A(fifo_data[5]), .B(fifo_data[4]), .C(n57), .Y(n54) );
  xor2a2 U26 ( .A(fifo_data[7]), .B(fifo_data[6]), .Y(n57) );
  xor2b2 U27 ( .A(n19), .B(cfg_pri_mod[0]), .Y(n53) );
  and2b2 U41 ( .B(N101), .A(n72), .Y(n58) );
  ao4f3 U42 ( .A(n30), .B(n75), .C(n76), .D(n15), .Y(n98) );
  ao4f3 U45 ( .A(n29), .B(n75), .C(cnt[0]), .D(n15), .Y(n99) );
  ao2i3 U50 ( .A(n81), .B(n80), .C(n22), .D(n82), .Y(n75) );
  xor2a2 U57 ( .A(\offset[3] ), .B(n86), .Y(N42) );
  and2b2 U58 ( .B(N68), .A(n87), .Y(n86) );
  xor2b2 U59 ( .A(N68), .B(n87), .Y(N41) );
  xor2b2 U61 ( .A(N67), .B(n20), .Y(N40) );
  ao4f3 U64 ( .A(n80), .B(n85), .C(n88), .D(n72), .Y(N129) );
  ao2i3 U67 ( .A(n88), .B(n72), .C(n89), .D(n84), .Y(N128) );
  xor2a2 U76 ( .A(rxpos[2]), .B(N68), .Y(n94) );
  xor2a2 U77 ( .A(rxpos[1]), .B(N67), .Y(n93) );
  xor2b2 U78 ( .A(rxpos[0]), .B(N66), .Y(n91) );
  xor2b2 U79 ( .A(\offset[3] ), .B(rxpos[3]), .Y(n90) );
  fdef2a15 \fifo_data_reg[7]  ( .D(si), .E(n58), .CLK(n9), .CLR(n11), .Q(
        fifo_data[7]) );
  fdef2a15 \fifo_data_reg[3]  ( .D(si), .E(n3), .CLK(n9), .CLR(n11), .Q(
        fifo_data[3]) );
  fdef2a15 \fifo_data_reg[2]  ( .D(si), .E(n2), .CLK(n9), .CLR(n11), .Q(
        fifo_data[2]) );
  fdef2a15 \fifo_data_reg[1]  ( .D(si), .E(n6), .CLK(n9), .CLR(n11), .Q(
        fifo_data[1]) );
  fdef2a15 \fifo_data_reg[0]  ( .D(si), .E(n1), .CLK(n10), .CLR(n11), .Q(
        fifo_data[0]) );
  fdef2a15 \fifo_data_reg[5]  ( .D(si), .E(n7), .CLK(n10), .CLR(n11), .Q(
        fifo_data[5]) );
  fdef2a15 \fifo_data_reg[4]  ( .D(si), .E(n4), .CLK(n10), .CLR(n11), .Q(
        fifo_data[4]) );
  fdef2a15 \fifo_data_reg[6]  ( .D(si), .E(n5), .CLK(n10), .CLR(n11), .Q(
        fifo_data[6]) );
  fdef2a3 \rxpos_reg[3]  ( .D(n23), .E(n14), .CLK(n8), .CLR(n12), .Q(rxpos[3])
         );
  fdef2a3 \rxpos_reg[2]  ( .D(N68), .E(n14), .CLK(n8), .CLR(n11), .Q(rxpos[2])
         );
  fdef2a3 \rxpos_reg[1]  ( .D(N67), .E(n14), .CLK(n9), .CLR(n11), .Q(rxpos[1])
         );
  fdef2a3 \rxpos_reg[0]  ( .D(N66), .E(n14), .CLK(n9), .CLR(n11), .Q(rxpos[0])
         );
  fdef2a3 \rxstate_reg[2]  ( .D(N130), .E(N127), .CLK(n8), .CLR(n12), .Q(
        rxstate[2]) );
  fdf2a3 \cnt_reg[1]  ( .D(n98), .CLK(n9), .CLR(n12), .Q(cnt[1]) );
  fdf2a3 \offset_reg[3]  ( .D(N42), .CLK(n8), .CLR(n12), .Q(\offset[3] ) );
  fdf2a3 \cnt_reg[2]  ( .D(n100), .CLK(n9), .CLR(n12), .Q(cnt[2]) );
  fdf2a3 \error_ind_reg[1]  ( .D(n95), .CLK(n10), .CLR(n13), .Q(error_ind[1])
         );
  fdf2a3 \error_ind_reg[0]  ( .D(n96), .CLK(n10), .CLR(n12), .Q(error_ind[0])
         );
  fdf2a3 \offset_reg[2]  ( .D(N41), .CLK(n8), .CLR(n12), .Q(N68) );
  fdf2a3 \offset_reg[0]  ( .D(n20), .CLK(n8), .CLR(n13), .Q(N66) );
  fdf2a3 \offset_reg[1]  ( .D(N40), .CLK(n8), .CLR(n12), .Q(N67) );
  fdef2a3 \rxstate_reg[0]  ( .D(N128), .E(N127), .CLK(n8), .CLR(n12), .Q(
        rxstate[0]) );
  fdef2a3 \rxstate_reg[1]  ( .D(N129), .E(N127), .CLK(n8), .CLR(n12), .Q(
        rxstate[1]) );
  fdf2a3 \cnt_reg[0]  ( .D(n99), .CLK(n9), .CLR(n12), .Q(cnt[0]) );
  fdf2a6 fifo_wr_reg ( .D(n97), .CLK(n10), .CLR(n12), .Q(fifo_wr) );
  inv1a1 U4 ( .A(rxstate[0]), .Y(n25) );
  inv1a3 U6 ( .A(si), .Y(n19) );
  inv1a3 U7 ( .A(cnt[1]), .Y(n30) );
  and2c3 U8 ( .A(n22), .B(cnt[2]), .Y(n66) );
  or3d3 U9 ( .A(n25), .B(n26), .C(rxstate[1]), .Y(n72) );
  or3d1 U10 ( .A(n27), .B(n26), .C(n25), .Y(n84) );
  or2c1 U11 ( .A(N72), .B(n24), .Y(n82) );
  and3d2 U12 ( .A(n31), .B(cnt[1]), .C(n22), .Y(n63) );
  or2c1 U13 ( .A(fifo_aval), .B(cfg_rx_enable), .Y(n48) );
  inv1a1 U15 ( .A(n75), .Y(n16) );
  inv1a3 U17 ( .A(n84), .Y(n24) );
  inv1a3 U18 ( .A(n61), .Y(n22) );
  inv1a3 U20 ( .A(n82), .Y(n14) );
  inv1a1 U21 ( .A(n67), .Y(n28) );
  and2a3 U28 ( .A(n83), .B(n21), .Y(N101) );
  inv1a1 U29 ( .A(n77), .Y(n15) );
  and2c3 U30 ( .A(n83), .B(n19), .Y(n81) );
  and2c3 U31 ( .A(n31), .B(n28), .Y(n83) );
  ao2h2 U32 ( .B(n88), .A(n72), .C(n43), .D(n89), .Y(N130) );
  oa1f3 U33 ( .A(n80), .B(n72), .C(n16), .Y(n77) );
  and2c3 U34 ( .A(n30), .B(n29), .Y(n67) );
  and2c3 U35 ( .A(n72), .B(n50), .Y(n61) );
  ao1f2 U36 ( .A(n78), .B(n31), .C(n79), .Y(n100) );
  or3d1 U37 ( .A(n67), .B(n31), .C(n77), .Y(n79) );
  oa1f3 U38 ( .A(n77), .B(n28), .C(n16), .Y(n78) );
  or2c1 U39 ( .A(n83), .B(n19), .Y(n85) );
  or3d1 U40 ( .A(n48), .B(n19), .C(n24), .Y(n45) );
  inv1a3 U43 ( .A(n50), .Y(n21) );
  buf1a9 U44 ( .A(reset_n), .Y(n12) );
  buf1a9 U46 ( .A(reset_n), .Y(n11) );
  and3a2 U47 ( .A(n29), .B(n30), .C(n66), .Y(n1) );
  and2a3 U48 ( .A(n66), .B(n60), .Y(n2) );
  and2a3 U49 ( .A(n66), .B(n67), .Y(n3) );
  and2a3 U51 ( .A(n63), .B(n29), .Y(n4) );
  clk1a3 U52 ( .A(baud_clk_16x), .Y(n9) );
  clk1a3 U53 ( .A(baud_clk_16x), .Y(n8) );
  clk1a3 U54 ( .A(baud_clk_16x), .Y(n10) );
  clk1a3 U55 ( .A(reset_n), .Y(n13) );
  oa1d2 U56 ( .A(n46), .B(si), .C(n51), .Y(n49) );
  and3c1 U60 ( .C(cfg_pri_mod[1]), .A(n52), .B(n43), .Y(n51) );
  and2c3 U62 ( .A(n30), .B(cnt[0]), .Y(n60) );
  mx4e3 U63 ( .D0(N72), .D1(N82), .D2(N101), .D3(n21), .S0(rxstate[0]), .S1(
        rxstate[1]), .Y(n17) );
  ao1f2 U65 ( .A(n83), .B(n19), .C(n85), .Y(N82) );
  and2c3 U66 ( .A(n48), .B(si), .Y(N72) );
  oa1f3 U68 ( .A(cnt[0]), .B(n30), .C(n60), .Y(n76) );
  or2c1 U69 ( .A(error_ind[1]), .B(n42), .Y(n44) );
  or2c1 U70 ( .A(error_ind[0]), .B(n42), .Y(n47) );
  and3d2 U71 ( .A(rxstate[0]), .B(rxstate[1]), .C(n26), .Y(n74) );
  inv1a3 U72 ( .A(rxstate[2]), .Y(n26) );
  and2c3 U73 ( .A(cfg_pri_mod[1]), .B(cfg_pri_mod[0]), .Y(n88) );
  inv1a3 U74 ( .A(cnt[2]), .Y(n31) );
  or3d3 U75 ( .A(n90), .B(n91), .C(n92), .Y(n50) );
  and2c3 U80 ( .A(n93), .B(n94), .Y(n92) );
  ao1f2 U81 ( .A(n71), .B(n72), .C(n73), .Y(n97) );
  or2c1 U82 ( .A(fifo_wr), .B(n71), .Y(n73) );
  and3c1 U83 ( .C(n43), .A(n58), .B(n74), .Y(n71) );
  or3d3 U84 ( .A(rxstate[0]), .B(n26), .C(rxstate[1]), .Y(n43) );
  or3d3 U85 ( .A(n27), .B(n26), .C(rxstate[0]), .Y(n80) );
  inv1a3 U86 ( .A(cnt[0]), .Y(n29) );
  or3d1 U87 ( .A(n74), .B(si), .C(cfg_stop_bit), .Y(n89) );
  inv1a3 U88 ( .A(rxstate[1]), .Y(n27) );
  or2c1 U89 ( .A(rxstate[2]), .B(n27), .Y(n46) );
  or2c1 U90 ( .A(N67), .B(N66), .Y(n87) );
  inv1a3 U91 ( .A(N66), .Y(n20) );
  inv1a1 U92 ( .A(\offset[3] ), .Y(n23) );
  and3a2 U93 ( .A(n60), .B(cnt[2]), .C(n61), .Y(n5) );
  and3a2 U94 ( .A(cnt[0]), .B(n30), .C(n66), .Y(n6) );
  and2a3 U95 ( .A(n63), .B(cnt[0]), .Y(n7) );
endmodule


module async_fifo_08_10_0_0_0 ( wr_clk, wr_reset_n, wr_en, wr_data, full, 
        afull, wr_total_free_space, rd_clk, rd_reset_n, rd_en, empty, aempty, 
        rd_total_aval, rd_data );
  input [7:0] wr_data;
  output [4:0] wr_total_free_space;
  output [4:0] rd_total_aval;
  output [7:0] rd_data;
  input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n, rd_en;
  output full, afull, empty, aempty;
  wire   N21, N22, N23, N24, N25, N27, N28, N29, N30, N31, N37, N38, N39, N40,
         N41, \wr_cnt[1] , N63, N64, N82, N83, \mem[15][7] , \mem[15][6] ,
         \mem[15][5] , \mem[15][4] , \mem[15][3] , \mem[15][2] , \mem[15][1] ,
         \mem[15][0] , \mem[14][7] , \mem[14][6] , \mem[14][5] , \mem[14][4] ,
         \mem[14][3] , \mem[14][2] , \mem[14][1] , \mem[14][0] , \mem[13][7] ,
         \mem[13][6] , \mem[13][5] , \mem[13][4] , \mem[13][3] , \mem[13][2] ,
         \mem[13][1] , \mem[13][0] , \mem[12][7] , \mem[12][6] , \mem[12][5] ,
         \mem[12][4] , \mem[12][3] , \mem[12][2] , \mem[12][1] , \mem[12][0] ,
         \mem[11][7] , \mem[11][6] , \mem[11][5] , \mem[11][4] , \mem[11][3] ,
         \mem[11][2] , \mem[11][1] , \mem[11][0] , \mem[10][7] , \mem[10][6] ,
         \mem[10][5] , \mem[10][4] , \mem[10][3] , \mem[10][2] , \mem[10][1] ,
         \mem[10][0] , \mem[9][7] , \mem[9][6] , \mem[9][5] , \mem[9][4] ,
         \mem[9][3] , \mem[9][2] , \mem[9][1] , \mem[9][0] , \mem[8][7] ,
         \mem[8][6] , \mem[8][5] , \mem[8][4] , \mem[8][3] , \mem[8][2] ,
         \mem[8][1] , \mem[8][0] , \mem[7][7] , \mem[7][6] , \mem[7][5] ,
         \mem[7][4] , \mem[7][3] , \mem[7][2] , \mem[7][1] , \mem[7][0] ,
         \mem[6][7] , \mem[6][6] , \mem[6][5] , \mem[6][4] , \mem[6][3] ,
         \mem[6][2] , \mem[6][1] , \mem[6][0] , \mem[5][7] , \mem[5][6] ,
         \mem[5][5] , \mem[5][4] , \mem[5][3] , \mem[5][2] , \mem[5][1] ,
         \mem[5][0] , \mem[4][7] , \mem[4][6] , \mem[4][5] , \mem[4][4] ,
         \mem[4][3] , \mem[4][2] , \mem[4][1] , \mem[4][0] , \mem[3][7] ,
         \mem[3][6] , \mem[3][5] , \mem[3][4] , \mem[3][3] , \mem[3][2] ,
         \mem[3][1] , \mem[3][0] , \mem[2][7] , \mem[2][6] , \mem[2][5] ,
         \mem[2][4] , \mem[2][3] , \mem[2][2] , \mem[2][1] , \mem[2][0] ,
         \mem[1][7] , \mem[1][6] , \mem[1][5] , \mem[1][4] , \mem[1][3] ,
         \mem[1][2] , \mem[1][1] , \mem[1][0] , \mem[0][7] , \mem[0][6] ,
         \mem[0][5] , \mem[0][4] , \mem[0][3] , \mem[0][2] , \mem[0][1] ,
         \mem[0][0] , \rd_ptr[4]1 , N136, N138, N139, N140, N141, N142, N148,
         N149, N150, N151, N152, N174, N175, N193, N194, n50, n51, n53, n54,
         n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n68, n69, n71,
         n73, n76, n79, n80, n83, n85, n91, n93, n94, N35, N34, N33, N146,
         N145, N144, \gte_316_C183/A[3] , \gte_316_C117/B[3] ,
         \sub_317_C183/carry[4] , \sub_317_C183/carry[3] ,
         \sub_317_C183/carry[2] , \sub_317_C183/carry[1] , \add_181/carry[4] ,
         \add_181/carry[3] , \add_181/carry[2] , \sub_317_C117/carry[4] ,
         \sub_317_C117/carry[3] , \sub_317_C117/carry[2] ,
         \sub_317_C117/carry[1] , \add_116/carry[4] , \add_116/carry[3] ,
         \add_116/carry[2] , \sub_320_2_C183/carry[4] ,
         \sub_320_2_C183/carry[3] , \sub_320_2_C183/carry[2] ,
         \sub_320_C183/carry[4] , \sub_320_C183/carry[3] ,
         \sub_320_C183/carry[2] , \sub_320_C183/carry[1] ,
         \sub_320_2_C117/carry[4] , \sub_320_2_C117/carry[3] ,
         \sub_320_2_C117/carry[2] , \sub_320_C117/carry[4] ,
         \sub_320_C117/carry[3] , \sub_320_C117/carry[2] ,
         \sub_320_C117/carry[1] , n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11,
         n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
         n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
         n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n52, n55, n67, n70,
         n72, n74, n75, n77, n78, n81, n82, n84, n86, n87, n88, n89, n90, n92,
         n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106,
         n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
         n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
         n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139,
         n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
         n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
         n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172,
         n173, n174, n175, n180, n181, n182, n183;
  wire   [4:0] wr_ptr;
  wire   [4:0] wr_ptr_inc;
  wire   [4:0] sync_rd_ptr;
  wire   [4:0] grey_wr_ptr;
  wire   [4:0] grey_rd_ptr_dly;
  wire   [4:0] sync_rd_ptr_1;
  wire   [4:0] sync_rd_ptr_0;
  wire   [4:0] rd_ptr_inc;
  wire   [4:0] sync_wr_ptr;
  wire   [4:0] sync_wr_ptr_1;
  wire   [4:0] sync_wr_ptr_0;

  xor2a2 U27 ( .A(sync_wr_ptr_1[2]), .B(\gte_316_C183/A[3] ), .Y(
        sync_wr_ptr[2]) );
  xor2b2 U30 ( .A(n54), .B(n53), .Y(sync_wr_ptr[1]) );
  xor2a2 U31 ( .A(sync_wr_ptr_1[2]), .B(sync_wr_ptr_1[1]), .Y(n53) );
  xor2b2 U32 ( .A(sync_wr_ptr_1[4]), .B(sync_wr_ptr_1[3]), .Y(n54) );
  xor2a2 U33 ( .A(sync_rd_ptr_1[2]), .B(\gte_316_C117/B[3] ), .Y(
        sync_rd_ptr[2]) );
  xor2b2 U36 ( .A(n57), .B(n56), .Y(sync_rd_ptr[1]) );
  xor2a2 U37 ( .A(sync_rd_ptr_1[2]), .B(sync_rd_ptr_1[1]), .Y(n56) );
  xor2b2 U38 ( .A(sync_rd_ptr_1[4]), .B(sync_rd_ptr_1[3]), .Y(n57) );
  and2b2 U50 ( .B(n80), .A(wr_ptr[0]), .Y(n69) );
  and2b2 U52 ( .B(n80), .A(wr_ptr_inc[0]), .Y(n71) );
  and2b2 U53 ( .B(wr_en), .A(wr_ptr[3]), .Y(n80) );
  and2b2 U62 ( .B(wr_ptr[2]), .A(wr_ptr[1]), .Y(n76) );
  and2b2 U64 ( .B(n91), .A(wr_ptr[0]), .Y(n83) );
  and2b2 U66 ( .B(wr_ptr[2]), .A(n181), .Y(n79) );
  and2b2 U67 ( .B(n91), .A(wr_ptr_inc[0]), .Y(n85) );
  oa4f3 U72 ( .A(N142), .B(N136), .C(N152), .D(n182), .Y(n64) );
  ao4a3 U75 ( .A(N138), .B(N136), .C(N148), .D(n182), .Y(rd_total_aval[0]) );
  ao4a3 U78 ( .A(N27), .B(N25), .C(N37), .D(n180), .Y(wr_total_free_space[0])
         );
  oa4f3 U80 ( .A(N30), .B(N25), .C(N40), .D(n180), .Y(n50) );
  oa4f3 U81 ( .A(N31), .B(N25), .C(N41), .D(n180), .Y(n66) );
  oa4f3 U82 ( .A(N29), .B(N25), .C(N39), .D(n180), .Y(n51) );
  xor2a2 U83 ( .A(wr_ptr_inc[4]), .B(wr_ptr_inc[3]), .Y(N83) );
  xor2a2 U84 ( .A(wr_ptr_inc[3]), .B(wr_ptr_inc[2]), .Y(N82) );
  xor2a2 U85 ( .A(wr_ptr_inc[2]), .B(wr_ptr_inc[1]), .Y(N64) );
  xor2a2 U86 ( .A(wr_ptr_inc[1]), .B(wr_ptr_inc[0]), .Y(N63) );
  xor2a2 U87 ( .A(rd_ptr_inc[4]), .B(rd_ptr_inc[3]), .Y(N194) );
  xor2a2 U88 ( .A(rd_ptr_inc[3]), .B(rd_ptr_inc[2]), .Y(N193) );
  xor2a2 U89 ( .A(rd_ptr_inc[2]), .B(rd_ptr_inc[1]), .Y(N175) );
  xor2a2 U90 ( .A(rd_ptr_inc[1]), .B(n87), .Y(N174) );
  fa1a2 \sub_317_C183/U2_1  ( .A(sync_wr_ptr[1]), .B(n84), .CI(
        \sub_317_C183/carry[1] ), .CO(\sub_317_C183/carry[2] ), .S(N139) );
  fa1a2 \sub_317_C183/U2_2  ( .A(sync_wr_ptr[2]), .B(n151), .CI(
        \sub_317_C183/carry[2] ), .CO(\sub_317_C183/carry[3] ), .S(N140) );
  fa1a2 \sub_317_C183/U2_3  ( .A(\gte_316_C183/A[3] ), .B(n150), .CI(
        \sub_317_C183/carry[3] ), .CO(\sub_317_C183/carry[4] ), .S(N141) );
  ha1a2 \add_181/U1_1_1  ( .A(n82), .B(n86), .CO(\add_181/carry[2] ), .S(
        rd_ptr_inc[1]) );
  ha1a2 \add_181/U1_1_2  ( .A(N23), .B(\add_181/carry[2] ), .CO(
        \add_181/carry[3] ), .S(rd_ptr_inc[2]) );
  ha1a2 \add_181/U1_1_3  ( .A(N24), .B(\add_181/carry[3] ), .CO(
        \add_181/carry[4] ), .S(rd_ptr_inc[3]) );
  fa1a2 \sub_317_C117/U2_1  ( .A(wr_ptr[1]), .B(n147), .CI(
        \sub_317_C117/carry[1] ), .CO(\sub_317_C117/carry[2] ), .S(N28) );
  fa1a2 \sub_317_C117/U2_2  ( .A(wr_ptr[2]), .B(n146), .CI(
        \sub_317_C117/carry[2] ), .CO(\sub_317_C117/carry[3] ), .S(N29) );
  fa1a2 \sub_317_C117/U2_3  ( .A(wr_ptr[3]), .B(n57), .CI(
        \sub_317_C117/carry[3] ), .CO(\sub_317_C117/carry[4] ), .S(N30) );
  ha1a2 \add_116/U1_1_1  ( .A(wr_ptr[1]), .B(wr_ptr[0]), .CO(
        \add_116/carry[2] ), .S(wr_ptr_inc[1]) );
  ha1a2 \add_116/U1_1_2  ( .A(wr_ptr[2]), .B(\add_116/carry[2] ), .CO(
        \add_116/carry[3] ), .S(wr_ptr_inc[2]) );
  ha1a2 \add_116/U1_1_3  ( .A(wr_ptr[3]), .B(\add_116/carry[3] ), .CO(
        \add_116/carry[4] ), .S(wr_ptr_inc[3]) );
  fa1a2 \sub_320_C183/U2_1  ( .A(n82), .B(n136), .CI(\sub_320_C183/carry[1] ), 
        .CO(\sub_320_C183/carry[2] ), .S(N144) );
  fa1a2 \sub_320_C183/U2_2  ( .A(N23), .B(n137), .CI(\sub_320_C183/carry[2] ), 
        .CO(\sub_320_C183/carry[3] ), .S(N145) );
  fa1a2 \sub_320_C183/U2_3  ( .A(N24), .B(n139), .CI(\sub_320_C183/carry[3] ), 
        .CO(\sub_320_C183/carry[4] ), .S(N146) );
  fa1a2 \sub_320_C117/U2_1  ( .A(sync_rd_ptr[1]), .B(n181), .CI(
        \sub_320_C117/carry[1] ), .CO(\sub_320_C117/carry[2] ), .S(N33) );
  fa1a2 \sub_320_C117/U2_2  ( .A(sync_rd_ptr[2]), .B(n131), .CI(
        \sub_320_C117/carry[2] ), .CO(\sub_320_C117/carry[3] ), .S(N34) );
  fa1a2 \sub_320_C117/U2_3  ( .A(\gte_316_C117/B[3] ), .B(n130), .CI(
        \sub_320_C117/carry[3] ), .CO(\sub_320_C117/carry[4] ), .S(N35) );
  fdef1a3 \mem_reg[15][7]  ( .D(wr_data[7]), .E(n15), .CLK(n89), .Q(
        \mem[15][7] ) );
  fdef1a3 \mem_reg[15][6]  ( .D(wr_data[6]), .E(n15), .CLK(n89), .Q(
        \mem[15][6] ) );
  fdef1a3 \mem_reg[15][5]  ( .D(wr_data[5]), .E(n15), .CLK(n89), .Q(
        \mem[15][5] ) );
  fdef1a3 \mem_reg[15][4]  ( .D(wr_data[4]), .E(n15), .CLK(n89), .Q(
        \mem[15][4] ) );
  fdef1a3 \mem_reg[15][3]  ( .D(wr_data[3]), .E(n15), .CLK(n89), .Q(
        \mem[15][3] ) );
  fdef1a3 \mem_reg[15][2]  ( .D(wr_data[2]), .E(n15), .CLK(n89), .Q(
        \mem[15][2] ) );
  fdef1a3 \mem_reg[15][1]  ( .D(wr_data[1]), .E(n15), .CLK(n89), .Q(
        \mem[15][1] ) );
  fdef1a3 \mem_reg[15][0]  ( .D(wr_data[0]), .E(n15), .CLK(n89), .Q(
        \mem[15][0] ) );
  fdef1a3 \mem_reg[11][7]  ( .D(wr_data[7]), .E(n11), .CLK(n95), .Q(
        \mem[11][7] ) );
  fdef1a3 \mem_reg[11][6]  ( .D(wr_data[6]), .E(n11), .CLK(n95), .Q(
        \mem[11][6] ) );
  fdef1a3 \mem_reg[11][5]  ( .D(wr_data[5]), .E(n11), .CLK(n95), .Q(
        \mem[11][5] ) );
  fdef1a3 \mem_reg[11][4]  ( .D(wr_data[4]), .E(n11), .CLK(n96), .Q(
        \mem[11][4] ) );
  fdef1a3 \mem_reg[11][3]  ( .D(wr_data[3]), .E(n11), .CLK(n96), .Q(
        \mem[11][3] ) );
  fdef1a3 \mem_reg[11][2]  ( .D(wr_data[2]), .E(n11), .CLK(n96), .Q(
        \mem[11][2] ) );
  fdef1a3 \mem_reg[11][1]  ( .D(wr_data[1]), .E(n11), .CLK(n96), .Q(
        \mem[11][1] ) );
  fdef1a3 \mem_reg[11][0]  ( .D(wr_data[0]), .E(n11), .CLK(n96), .Q(
        \mem[11][0] ) );
  fdef1a3 \mem_reg[7][7]  ( .D(wr_data[7]), .E(n7), .CLK(n99), .Q(\mem[7][7] )
         );
  fdef1a3 \mem_reg[7][6]  ( .D(wr_data[6]), .E(n7), .CLK(n99), .Q(\mem[7][6] )
         );
  fdef1a3 \mem_reg[7][5]  ( .D(wr_data[5]), .E(n7), .CLK(n99), .Q(\mem[7][5] )
         );
  fdef1a3 \mem_reg[7][4]  ( .D(wr_data[4]), .E(n7), .CLK(n99), .Q(\mem[7][4] )
         );
  fdef1a3 \mem_reg[7][3]  ( .D(wr_data[3]), .E(n7), .CLK(n99), .Q(\mem[7][3] )
         );
  fdef1a3 \mem_reg[7][2]  ( .D(wr_data[2]), .E(n7), .CLK(n99), .Q(\mem[7][2] )
         );
  fdef1a3 \mem_reg[7][1]  ( .D(wr_data[1]), .E(n7), .CLK(n99), .Q(\mem[7][1] )
         );
  fdef1a3 \mem_reg[7][0]  ( .D(wr_data[0]), .E(n7), .CLK(n100), .Q(\mem[7][0] ) );
  fdef1a3 \mem_reg[3][7]  ( .D(wr_data[7]), .E(n18), .CLK(n102), .Q(
        \mem[3][7] ) );
  fdef1a3 \mem_reg[3][6]  ( .D(wr_data[6]), .E(n18), .CLK(n102), .Q(
        \mem[3][6] ) );
  fdef1a3 \mem_reg[3][5]  ( .D(wr_data[5]), .E(n18), .CLK(n103), .Q(
        \mem[3][5] ) );
  fdef1a3 \mem_reg[3][4]  ( .D(wr_data[4]), .E(n18), .CLK(n103), .Q(
        \mem[3][4] ) );
  fdef1a3 \mem_reg[3][3]  ( .D(wr_data[3]), .E(n18), .CLK(n103), .Q(
        \mem[3][3] ) );
  fdef1a3 \mem_reg[3][2]  ( .D(wr_data[2]), .E(n18), .CLK(n103), .Q(
        \mem[3][2] ) );
  fdef1a3 \mem_reg[3][1]  ( .D(wr_data[1]), .E(n18), .CLK(n103), .Q(
        \mem[3][1] ) );
  fdef1a3 \mem_reg[3][0]  ( .D(wr_data[0]), .E(n18), .CLK(n103), .Q(
        \mem[3][0] ) );
  fdf2a3 \sync_rd_ptr_1_reg[1]  ( .D(sync_rd_ptr_0[1]), .CLK(n106), .CLR(n125), 
        .Q(sync_rd_ptr_1[1]) );
  fdf2a3 \sync_wr_ptr_1_reg[3]  ( .D(sync_wr_ptr_0[3]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_1[3]) );
  fdf2a3 \sync_rd_ptr_1_reg[3]  ( .D(sync_rd_ptr_0[3]), .CLK(n107), .CLR(n125), 
        .Q(sync_rd_ptr_1[3]) );
  fdf2a3 \sync_wr_ptr_1_reg[1]  ( .D(sync_wr_ptr_0[1]), .CLK(n128), .CLR(n123), 
        .Q(sync_wr_ptr_1[1]) );
  fdef2a3 \rd_ptr_reg[1]  ( .D(rd_ptr_inc[1]), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(N22) );
  fdef1a3 \mem_reg[14][7]  ( .D(wr_data[7]), .E(n14), .CLK(n90), .Q(
        \mem[14][7] ) );
  fdef1a3 \mem_reg[14][6]  ( .D(wr_data[6]), .E(n14), .CLK(n90), .Q(
        \mem[14][6] ) );
  fdef1a3 \mem_reg[14][5]  ( .D(wr_data[5]), .E(n14), .CLK(n90), .Q(
        \mem[14][5] ) );
  fdef1a3 \mem_reg[14][4]  ( .D(wr_data[4]), .E(n14), .CLK(n90), .Q(
        \mem[14][4] ) );
  fdef1a3 \mem_reg[14][3]  ( .D(wr_data[3]), .E(n14), .CLK(n90), .Q(
        \mem[14][3] ) );
  fdef1a3 \mem_reg[14][2]  ( .D(wr_data[2]), .E(n14), .CLK(n90), .Q(
        \mem[14][2] ) );
  fdef1a3 \mem_reg[14][1]  ( .D(wr_data[1]), .E(n14), .CLK(n90), .Q(
        \mem[14][1] ) );
  fdef1a3 \mem_reg[14][0]  ( .D(wr_data[0]), .E(n14), .CLK(n90), .Q(
        \mem[14][0] ) );
  fdef1a3 \mem_reg[12][7]  ( .D(wr_data[7]), .E(n12), .CLK(n92), .Q(
        \mem[12][7] ) );
  fdef1a3 \mem_reg[12][6]  ( .D(wr_data[6]), .E(n12), .CLK(n92), .Q(
        \mem[12][6] ) );
  fdef1a3 \mem_reg[12][5]  ( .D(wr_data[5]), .E(n12), .CLK(n95), .Q(
        \mem[12][5] ) );
  fdef1a3 \mem_reg[12][4]  ( .D(wr_data[4]), .E(n12), .CLK(n95), .Q(
        \mem[12][4] ) );
  fdef1a3 \mem_reg[12][3]  ( .D(wr_data[3]), .E(n12), .CLK(n95), .Q(
        \mem[12][3] ) );
  fdef1a3 \mem_reg[12][2]  ( .D(wr_data[2]), .E(n12), .CLK(n95), .Q(
        \mem[12][2] ) );
  fdef1a3 \mem_reg[12][1]  ( .D(wr_data[1]), .E(n12), .CLK(n95), .Q(
        \mem[12][1] ) );
  fdef1a3 \mem_reg[12][0]  ( .D(wr_data[0]), .E(n12), .CLK(n95), .Q(
        \mem[12][0] ) );
  fdef1a3 \mem_reg[10][7]  ( .D(wr_data[7]), .E(n10), .CLK(n96), .Q(
        \mem[10][7] ) );
  fdef1a3 \mem_reg[10][6]  ( .D(wr_data[6]), .E(n10), .CLK(n96), .Q(
        \mem[10][6] ) );
  fdef1a3 \mem_reg[10][5]  ( .D(wr_data[5]), .E(n10), .CLK(n96), .Q(
        \mem[10][5] ) );
  fdef1a3 \mem_reg[10][4]  ( .D(wr_data[4]), .E(n10), .CLK(n96), .Q(
        \mem[10][4] ) );
  fdef1a3 \mem_reg[10][3]  ( .D(wr_data[3]), .E(n10), .CLK(n97), .Q(
        \mem[10][3] ) );
  fdef1a3 \mem_reg[10][2]  ( .D(wr_data[2]), .E(n10), .CLK(n97), .Q(
        \mem[10][2] ) );
  fdef1a3 \mem_reg[10][1]  ( .D(wr_data[1]), .E(n10), .CLK(n97), .Q(
        \mem[10][1] ) );
  fdef1a3 \mem_reg[10][0]  ( .D(wr_data[0]), .E(n10), .CLK(n97), .Q(
        \mem[10][0] ) );
  fdef1a3 \mem_reg[8][7]  ( .D(wr_data[7]), .E(n8), .CLK(n98), .Q(\mem[8][7] )
         );
  fdef1a3 \mem_reg[8][6]  ( .D(wr_data[6]), .E(n8), .CLK(n98), .Q(\mem[8][6] )
         );
  fdef1a3 \mem_reg[8][5]  ( .D(wr_data[5]), .E(n8), .CLK(n98), .Q(\mem[8][5] )
         );
  fdef1a3 \mem_reg[8][4]  ( .D(wr_data[4]), .E(n8), .CLK(n98), .Q(\mem[8][4] )
         );
  fdef1a3 \mem_reg[8][3]  ( .D(wr_data[3]), .E(n8), .CLK(n98), .Q(\mem[8][3] )
         );
  fdef1a3 \mem_reg[8][2]  ( .D(wr_data[2]), .E(n8), .CLK(n98), .Q(\mem[8][2] )
         );
  fdef1a3 \mem_reg[8][1]  ( .D(wr_data[1]), .E(n8), .CLK(n99), .Q(\mem[8][1] )
         );
  fdef1a3 \mem_reg[8][0]  ( .D(wr_data[0]), .E(n8), .CLK(n99), .Q(\mem[8][0] )
         );
  fdef1a3 \mem_reg[6][7]  ( .D(wr_data[7]), .E(n6), .CLK(n100), .Q(\mem[6][7] ) );
  fdef1a3 \mem_reg[6][6]  ( .D(wr_data[6]), .E(n6), .CLK(n100), .Q(\mem[6][6] ) );
  fdef1a3 \mem_reg[6][5]  ( .D(wr_data[5]), .E(n6), .CLK(n100), .Q(\mem[6][5] ) );
  fdef1a3 \mem_reg[6][4]  ( .D(wr_data[4]), .E(n6), .CLK(n100), .Q(\mem[6][4] ) );
  fdef1a3 \mem_reg[6][3]  ( .D(wr_data[3]), .E(n6), .CLK(n100), .Q(\mem[6][3] ) );
  fdef1a3 \mem_reg[6][2]  ( .D(wr_data[2]), .E(n6), .CLK(n100), .Q(\mem[6][2] ) );
  fdef1a3 \mem_reg[6][1]  ( .D(wr_data[1]), .E(n6), .CLK(n100), .Q(\mem[6][1] ) );
  fdef1a3 \mem_reg[6][0]  ( .D(wr_data[0]), .E(n6), .CLK(n100), .Q(\mem[6][0] ) );
  fdef1a3 \mem_reg[4][7]  ( .D(wr_data[7]), .E(n4), .CLK(n101), .Q(\mem[4][7] ) );
  fdef1a3 \mem_reg[4][6]  ( .D(wr_data[6]), .E(n4), .CLK(n102), .Q(\mem[4][6] ) );
  fdef1a3 \mem_reg[4][5]  ( .D(wr_data[5]), .E(n4), .CLK(n102), .Q(\mem[4][5] ) );
  fdef1a3 \mem_reg[4][4]  ( .D(wr_data[4]), .E(n4), .CLK(n102), .Q(\mem[4][4] ) );
  fdef1a3 \mem_reg[4][3]  ( .D(wr_data[3]), .E(n4), .CLK(n102), .Q(\mem[4][3] ) );
  fdef1a3 \mem_reg[4][2]  ( .D(wr_data[2]), .E(n4), .CLK(n102), .Q(\mem[4][2] ) );
  fdef1a3 \mem_reg[4][1]  ( .D(wr_data[1]), .E(n4), .CLK(n102), .Q(\mem[4][1] ) );
  fdef1a3 \mem_reg[4][0]  ( .D(wr_data[0]), .E(n4), .CLK(n102), .Q(\mem[4][0] ) );
  fdef1a3 \mem_reg[2][7]  ( .D(wr_data[7]), .E(n17), .CLK(n103), .Q(
        \mem[2][7] ) );
  fdef1a3 \mem_reg[2][6]  ( .D(wr_data[6]), .E(n17), .CLK(n103), .Q(
        \mem[2][6] ) );
  fdef1a3 \mem_reg[2][5]  ( .D(wr_data[5]), .E(n17), .CLK(n103), .Q(
        \mem[2][5] ) );
  fdef1a3 \mem_reg[2][4]  ( .D(wr_data[4]), .E(n17), .CLK(n104), .Q(
        \mem[2][4] ) );
  fdef1a3 \mem_reg[2][3]  ( .D(wr_data[3]), .E(n17), .CLK(n104), .Q(
        \mem[2][3] ) );
  fdef1a3 \mem_reg[2][2]  ( .D(wr_data[2]), .E(n17), .CLK(n104), .Q(
        \mem[2][2] ) );
  fdef1a3 \mem_reg[2][1]  ( .D(wr_data[1]), .E(n17), .CLK(n104), .Q(
        \mem[2][1] ) );
  fdef1a3 \mem_reg[2][0]  ( .D(wr_data[0]), .E(n17), .CLK(n104), .Q(
        \mem[2][0] ) );
  fdef1a3 \mem_reg[0][7]  ( .D(wr_data[7]), .E(n16), .CLK(n105), .Q(
        \mem[0][7] ) );
  fdef1a3 \mem_reg[0][6]  ( .D(wr_data[6]), .E(n16), .CLK(n105), .Q(
        \mem[0][6] ) );
  fdef1a3 \mem_reg[0][5]  ( .D(wr_data[5]), .E(n16), .CLK(n105), .Q(
        \mem[0][5] ) );
  fdef1a3 \mem_reg[0][4]  ( .D(wr_data[4]), .E(n16), .CLK(n105), .Q(
        \mem[0][4] ) );
  fdef1a3 \mem_reg[0][3]  ( .D(wr_data[3]), .E(n16), .CLK(n105), .Q(
        \mem[0][3] ) );
  fdef1a3 \mem_reg[0][2]  ( .D(wr_data[2]), .E(n16), .CLK(n106), .Q(
        \mem[0][2] ) );
  fdef1a3 \mem_reg[0][1]  ( .D(wr_data[1]), .E(n16), .CLK(n106), .Q(
        \mem[0][1] ) );
  fdef1a3 \mem_reg[0][0]  ( .D(wr_data[0]), .E(n16), .CLK(n106), .Q(
        \mem[0][0] ) );
  fdef1a3 \mem_reg[13][7]  ( .D(wr_data[7]), .E(n13), .CLK(n90), .Q(
        \mem[13][7] ) );
  fdef1a3 \mem_reg[13][6]  ( .D(wr_data[6]), .E(n13), .CLK(n92), .Q(
        \mem[13][6] ) );
  fdef1a3 \mem_reg[13][5]  ( .D(wr_data[5]), .E(n13), .CLK(n92), .Q(
        \mem[13][5] ) );
  fdef1a3 \mem_reg[13][4]  ( .D(wr_data[4]), .E(n13), .CLK(n92), .Q(
        \mem[13][4] ) );
  fdef1a3 \mem_reg[13][3]  ( .D(wr_data[3]), .E(n13), .CLK(n92), .Q(
        \mem[13][3] ) );
  fdef1a3 \mem_reg[13][2]  ( .D(wr_data[2]), .E(n13), .CLK(n92), .Q(
        \mem[13][2] ) );
  fdef1a3 \mem_reg[13][1]  ( .D(wr_data[1]), .E(n13), .CLK(n92), .Q(
        \mem[13][1] ) );
  fdef1a3 \mem_reg[13][0]  ( .D(wr_data[0]), .E(n13), .CLK(n92), .Q(
        \mem[13][0] ) );
  fdef1a3 \mem_reg[9][7]  ( .D(wr_data[7]), .E(n9), .CLK(n97), .Q(\mem[9][7] )
         );
  fdef1a3 \mem_reg[9][6]  ( .D(wr_data[6]), .E(n9), .CLK(n97), .Q(\mem[9][6] )
         );
  fdef1a3 \mem_reg[9][5]  ( .D(wr_data[5]), .E(n9), .CLK(n97), .Q(\mem[9][5] )
         );
  fdef1a3 \mem_reg[9][4]  ( .D(wr_data[4]), .E(n9), .CLK(n97), .Q(\mem[9][4] )
         );
  fdef1a3 \mem_reg[9][3]  ( .D(wr_data[3]), .E(n9), .CLK(n97), .Q(\mem[9][3] )
         );
  fdef1a3 \mem_reg[9][2]  ( .D(wr_data[2]), .E(n9), .CLK(n98), .Q(\mem[9][2] )
         );
  fdef1a3 \mem_reg[9][1]  ( .D(wr_data[1]), .E(n9), .CLK(n98), .Q(\mem[9][1] )
         );
  fdef1a3 \mem_reg[9][0]  ( .D(wr_data[0]), .E(n9), .CLK(n98), .Q(\mem[9][0] )
         );
  fdef1a3 \mem_reg[5][7]  ( .D(wr_data[7]), .E(n5), .CLK(n101), .Q(\mem[5][7] ) );
  fdef1a3 \mem_reg[5][6]  ( .D(wr_data[6]), .E(n5), .CLK(n101), .Q(\mem[5][6] ) );
  fdef1a3 \mem_reg[5][5]  ( .D(wr_data[5]), .E(n5), .CLK(n101), .Q(\mem[5][5] ) );
  fdef1a3 \mem_reg[5][4]  ( .D(wr_data[4]), .E(n5), .CLK(n101), .Q(\mem[5][4] ) );
  fdef1a3 \mem_reg[5][3]  ( .D(wr_data[3]), .E(n5), .CLK(n101), .Q(\mem[5][3] ) );
  fdef1a3 \mem_reg[5][2]  ( .D(wr_data[2]), .E(n5), .CLK(n101), .Q(\mem[5][2] ) );
  fdef1a3 \mem_reg[5][1]  ( .D(wr_data[1]), .E(n5), .CLK(n101), .Q(\mem[5][1] ) );
  fdef1a3 \mem_reg[5][0]  ( .D(wr_data[0]), .E(n5), .CLK(n101), .Q(\mem[5][0] ) );
  fdef1a3 \mem_reg[1][7]  ( .D(wr_data[7]), .E(n3), .CLK(n104), .Q(\mem[1][7] ) );
  fdef1a3 \mem_reg[1][6]  ( .D(wr_data[6]), .E(n3), .CLK(n104), .Q(\mem[1][6] ) );
  fdef1a3 \mem_reg[1][5]  ( .D(wr_data[5]), .E(n3), .CLK(n104), .Q(\mem[1][5] ) );
  fdef1a3 \mem_reg[1][4]  ( .D(wr_data[4]), .E(n3), .CLK(n104), .Q(\mem[1][4] ) );
  fdef1a3 \mem_reg[1][3]  ( .D(wr_data[3]), .E(n3), .CLK(n105), .Q(\mem[1][3] ) );
  fdef1a3 \mem_reg[1][2]  ( .D(wr_data[2]), .E(n3), .CLK(n105), .Q(\mem[1][2] ) );
  fdef1a3 \mem_reg[1][1]  ( .D(wr_data[1]), .E(n3), .CLK(n105), .Q(\mem[1][1] ) );
  fdef1a3 \mem_reg[1][0]  ( .D(wr_data[0]), .E(n3), .CLK(n105), .Q(\mem[1][0] ) );
  fdf2a3 \sync_rd_ptr_1_reg[0]  ( .D(sync_rd_ptr_0[0]), .CLK(n106), .CLR(n125), 
        .Q(sync_rd_ptr_1[0]) );
  fdf2a3 \sync_wr_ptr_1_reg[0]  ( .D(sync_wr_ptr_0[0]), .CLK(n128), .CLR(n123), 
        .Q(sync_wr_ptr_1[0]) );
  fdef2a3 \rd_ptr_reg[0]  ( .D(n87), .E(n81), .CLK(n126), .CLR(n122), .Q(N21)
         );
  fdef2a3 full_q_reg ( .D(wr_en), .E(n174), .CLK(n107), .CLR(n124), .Q(full)
         );
  fdf2a3 \sync_rd_ptr_1_reg[2]  ( .D(sync_rd_ptr_0[2]), .CLK(n106), .CLR(n125), 
        .Q(sync_rd_ptr_1[2]) );
  fdf2a3 \sync_wr_ptr_1_reg[2]  ( .D(sync_wr_ptr_0[2]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_1[2]) );
  fdef2a3 \rd_ptr_reg[4]  ( .D(rd_ptr_inc[4]), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(\rd_ptr[4]1 ) );
  fdef2a3 \wr_ptr_reg[4]  ( .D(wr_ptr_inc[4]), .E(wr_en), .CLK(n88), .CLR(n124), .Q(wr_ptr[4]) );
  fdef3a3 empty_q_reg ( .D(n81), .E(n58), .CLK(n128), .PRE(n123), .Q(empty) );
  fdef2a6 \wr_ptr_reg[2]  ( .D(wr_ptr_inc[2]), .E(wr_en), .CLK(n88), .CLR(n124), .Q(wr_ptr[2]) );
  fdf2a3 \sync_rd_ptr_1_reg[4]  ( .D(sync_rd_ptr_0[4]), .CLK(n107), .CLR(n125), 
        .Q(sync_rd_ptr_1[4]) );
  fdf2a3 \sync_wr_ptr_1_reg[4]  ( .D(sync_wr_ptr_0[4]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_1[4]) );
  fdef2a9 \rd_ptr_reg[3]  ( .D(rd_ptr_inc[3]), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(N24) );
  fdef2a3 \grey_wr_ptr_reg[4]  ( .D(wr_ptr_inc[4]), .E(wr_en), .CLK(n88), 
        .CLR(n124), .Q(grey_wr_ptr[4]) );
  fdef2a3 \grey_rd_ptr_reg[4]  ( .D(rd_ptr_inc[4]), .E(n81), .CLK(n126), .CLR(
        n122), .Q(grey_rd_ptr_dly[4]) );
  fdef2a3 \wr_ptr_reg[3]  ( .D(wr_ptr_inc[3]), .E(wr_en), .CLK(n88), .CLR(n124), .Q(wr_ptr[3]) );
  fdef2a6 \rd_ptr_reg[2]  ( .D(rd_ptr_inc[2]), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(N23) );
  fdef2a3 \grey_wr_ptr_reg[0]  ( .D(N63), .E(wr_en), .CLK(n88), .CLR(n124), 
        .Q(grey_wr_ptr[0]) );
  fdef2a3 \grey_wr_ptr_reg[1]  ( .D(N64), .E(wr_en), .CLK(n88), .CLR(n124), 
        .Q(grey_wr_ptr[1]) );
  fdef2a3 \grey_wr_ptr_reg[2]  ( .D(N82), .E(wr_en), .CLK(n88), .CLR(n124), 
        .Q(grey_wr_ptr[2]) );
  fdef2a3 \grey_wr_ptr_reg[3]  ( .D(N83), .E(wr_en), .CLK(n89), .CLR(n124), 
        .Q(grey_wr_ptr[3]) );
  fdef2a3 \grey_rd_ptr_reg[0]  ( .D(N174), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(grey_rd_ptr_dly[0]) );
  fdef2a3 \grey_rd_ptr_reg[1]  ( .D(N175), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(grey_rd_ptr_dly[1]) );
  fdef2a3 \grey_rd_ptr_reg[2]  ( .D(N193), .E(n81), .CLK(n126), .CLR(n122), 
        .Q(grey_rd_ptr_dly[2]) );
  fdef2a3 \grey_rd_ptr_reg[3]  ( .D(N194), .E(n81), .CLK(n127), .CLR(n122), 
        .Q(grey_rd_ptr_dly[3]) );
  fdf2a3 \sync_rd_ptr_0_reg[0]  ( .D(grey_rd_ptr_dly[0]), .CLK(n106), .CLR(
        n125), .Q(sync_rd_ptr_0[0]) );
  fdf2a3 \sync_rd_ptr_0_reg[1]  ( .D(grey_rd_ptr_dly[1]), .CLK(n106), .CLR(
        n125), .Q(sync_rd_ptr_0[1]) );
  fdf2a3 \sync_rd_ptr_0_reg[2]  ( .D(grey_rd_ptr_dly[2]), .CLK(n106), .CLR(
        n125), .Q(sync_rd_ptr_0[2]) );
  fdf2a3 \sync_wr_ptr_0_reg[4]  ( .D(grey_wr_ptr[4]), .CLK(n127), .CLR(n122), 
        .Q(sync_wr_ptr_0[4]) );
  fdf2a3 \sync_wr_ptr_0_reg[3]  ( .D(grey_wr_ptr[3]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_0[3]) );
  fdf2a3 \sync_wr_ptr_0_reg[2]  ( .D(grey_wr_ptr[2]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_0[2]) );
  fdf2a3 \sync_wr_ptr_0_reg[1]  ( .D(grey_wr_ptr[1]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_0[1]) );
  fdf2a3 \sync_wr_ptr_0_reg[0]  ( .D(grey_wr_ptr[0]), .CLK(n127), .CLR(n123), 
        .Q(sync_wr_ptr_0[0]) );
  fdf2a3 \sync_rd_ptr_0_reg[4]  ( .D(grey_rd_ptr_dly[4]), .CLK(n107), .CLR(
        n125), .Q(sync_rd_ptr_0[4]) );
  fdf2a3 \sync_rd_ptr_0_reg[3]  ( .D(grey_rd_ptr_dly[3]), .CLK(n107), .CLR(
        n125), .Q(sync_rd_ptr_0[3]) );
  fdef2a3 \wr_ptr_reg[0]  ( .D(wr_ptr_inc[0]), .E(wr_en), .CLK(n88), .CLR(n124), .Q(wr_ptr[0]) );
  fdef2a3 \wr_ptr_reg[1]  ( .D(wr_ptr_inc[1]), .E(wr_en), .CLK(n88), .CLR(n124), .Q(wr_ptr[1]) );
  and2c3 U3 ( .A(wr_ptr[1]), .B(wr_ptr[2]), .Y(n68) );
  and2c3 U4 ( .A(n181), .B(wr_ptr[2]), .Y(n73) );
  xor3b3 U5 ( .A(\rd_ptr[4]1 ), .B(n140), .C(\sub_320_C183/carry[4] ), .Y(n1)
         );
  xor3b3 U6 ( .A(sync_rd_ptr_1[4]), .B(n129), .C(\sub_320_C117/carry[4] ), .Y(
        n2) );
  and2a6 U7 ( .A(n83), .B(n73), .Y(n10) );
  and2a6 U8 ( .A(n85), .B(n68), .Y(n9) );
  and2a6 U9 ( .A(n79), .B(n69), .Y(n6) );
  and2a6 U10 ( .A(n76), .B(n71), .Y(n5) );
  and2a6 U11 ( .A(n85), .B(n73), .Y(n11) );
  and2a6 U12 ( .A(n83), .B(n68), .Y(n8) );
  and2a6 U13 ( .A(n79), .B(n71), .Y(n7) );
  and2a6 U14 ( .A(n76), .B(n69), .Y(n4) );
  and2a6 U15 ( .A(n83), .B(n79), .Y(n14) );
  and2a6 U16 ( .A(n85), .B(n76), .Y(n13) );
  and2a6 U17 ( .A(n73), .B(n69), .Y(n17) );
  and2a6 U18 ( .A(n71), .B(n68), .Y(n3) );
  and2a6 U19 ( .A(n85), .B(n79), .Y(n15) );
  and2a6 U20 ( .A(n83), .B(n76), .Y(n12) );
  and2a6 U21 ( .A(n73), .B(n71), .Y(n18) );
  and2a6 U22 ( .A(n68), .B(n69), .Y(n16) );
  oa4f3 U23 ( .A(N141), .B(N136), .C(N151), .D(n182), .Y(n63) );
  oa4f2 U24 ( .A(N139), .B(N136), .C(N149), .D(n182), .Y(n62) );
  ao1f9 U25 ( .A(\rd_ptr[4]1 ), .B(n173), .C(n171), .Y(N136) );
  ao1f9 U26 ( .A(sync_rd_ptr_1[4]), .B(n161), .C(n160), .Y(N25) );
  ao1d2 U28 ( .A(n161), .B(sync_rd_ptr_1[4]), .C(n159), .Y(n160) );
  ao4a1 U29 ( .A(N140), .B(N136), .C(N150), .D(n182), .Y(rd_total_aval[2]) );
  ao4a1 U34 ( .A(N28), .B(N25), .C(N38), .D(n180), .Y(\wr_cnt[1] ) );
  xor2a2 U35 ( .A(\add_181/carry[4] ), .B(\rd_ptr[4]1 ), .Y(rd_ptr_inc[4]) );
  xor2a2 U39 ( .A(\add_116/carry[4] ), .B(wr_ptr[4]), .Y(wr_ptr_inc[4]) );
  ao4b2 U40 ( .C(sync_wr_ptr_1[0]), .D(n20), .B(sync_wr_ptr[1]), .A(
        sync_wr_ptr_1[0]), .Y(sync_wr_ptr[0]) );
  ao4b2 U41 ( .C(sync_rd_ptr_1[0]), .D(n19), .B(sync_rd_ptr[1]), .A(
        sync_rd_ptr_1[0]), .Y(sync_rd_ptr[0]) );
  or3d1 U42 ( .A(rd_total_aval[0]), .B(n62), .C(n93), .Y(n60) );
  inv1a1 U43 ( .A(N148), .Y(n141) );
  inv1a1 U44 ( .A(N144), .Y(n142) );
  clk1a3 U45 ( .A(n109), .Y(n105) );
  clk1a3 U46 ( .A(n109), .Y(n104) );
  clk1a3 U47 ( .A(n110), .Y(n103) );
  clk1a3 U48 ( .A(n110), .Y(n102) );
  clk1a3 U49 ( .A(n111), .Y(n101) );
  clk1a3 U51 ( .A(n111), .Y(n100) );
  clk1a3 U54 ( .A(n112), .Y(n99) );
  clk1a3 U55 ( .A(n112), .Y(n98) );
  clk1a3 U56 ( .A(n113), .Y(n97) );
  clk1a3 U57 ( .A(n113), .Y(n96) );
  clk1a3 U58 ( .A(n114), .Y(n95) );
  clk1a3 U59 ( .A(n114), .Y(n92) );
  clk1a3 U60 ( .A(n115), .Y(n90) );
  clk1a3 U61 ( .A(n115), .Y(n89) );
  inv1a1 U63 ( .A(sync_wr_ptr[1]), .Y(n136) );
  inv1a1 U65 ( .A(n63), .Y(rd_total_aval[3]) );
  inv1a1 U68 ( .A(N37), .Y(n132) );
  clk1a6 U69 ( .A(n86), .Y(n72) );
  clk1a6 U70 ( .A(n86), .Y(n74) );
  clk1a6 U71 ( .A(n86), .Y(n70) );
  clk1a6 U73 ( .A(n82), .Y(n77) );
  clk1a6 U74 ( .A(n82), .Y(n78) );
  clk1a6 U76 ( .A(n82), .Y(n75) );
  inv1a1 U77 ( .A(n60), .Y(aempty) );
  clk1a3 U79 ( .A(n116), .Y(n88) );
  clk1a3 U91 ( .A(n117), .Y(n116) );
  clk1a3 U92 ( .A(n108), .Y(n106) );
  clk1a3 U93 ( .A(n108), .Y(n107) );
  clk1a3 U94 ( .A(n120), .Y(n109) );
  clk1a3 U95 ( .A(n120), .Y(n110) );
  clk1a3 U96 ( .A(n119), .Y(n111) );
  clk1a3 U97 ( .A(n119), .Y(n112) );
  clk1a3 U98 ( .A(n118), .Y(n113) );
  clk1a3 U99 ( .A(n118), .Y(n114) );
  clk1a3 U100 ( .A(n117), .Y(n115) );
  inv1a3 U101 ( .A(N25), .Y(n180) );
  inv1a3 U102 ( .A(N136), .Y(n182) );
  inv1a3 U103 ( .A(n54), .Y(\gte_316_C183/A[3] ) );
  inv1a3 U104 ( .A(n57), .Y(\gte_316_C117/B[3] ) );
  and3d2 U105 ( .A(rd_total_aval[2]), .B(rd_total_aval[4]), .C(
        rd_total_aval[3]), .Y(n93) );
  and3d2 U106 ( .A(n51), .B(n175), .C(n50), .Y(n94) );
  inv1a1 U107 ( .A(n66), .Y(n175) );
  or2c1 U108 ( .A(n63), .B(n64), .Y(n61) );
  inv1a1 U109 ( .A(n64), .Y(rd_total_aval[4]) );
  inv1a1 U110 ( .A(sync_wr_ptr[0]), .Y(n138) );
  inv1a1 U111 ( .A(sync_rd_ptr[0]), .Y(n148) );
  inv1a1 U112 ( .A(N33), .Y(n133) );
  inv1a1 U113 ( .A(N34), .Y(n134) );
  inv1a1 U114 ( .A(N35), .Y(n135) );
  inv1a1 U115 ( .A(N145), .Y(n143) );
  inv1a1 U116 ( .A(N146), .Y(n144) );
  buf1a9 U117 ( .A(wr_reset_n), .Y(n124) );
  buf1a9 U118 ( .A(rd_reset_n), .Y(n122) );
  clk1a6 U119 ( .A(rd_reset_n), .Y(n123) );
  clk1a6 U120 ( .A(wr_reset_n), .Y(n125) );
  clk1a6 U121 ( .A(rd_en), .Y(n81) );
  inv1a3 U122 ( .A(n84), .Y(n82) );
  inv1a3 U123 ( .A(n87), .Y(n86) );
  clk1a3 U124 ( .A(rd_clk), .Y(n127) );
  clk1a3 U125 ( .A(rd_clk), .Y(n126) );
  clk1a3 U126 ( .A(rd_clk), .Y(n128) );
  clk1a3 U127 ( .A(wr_clk), .Y(n120) );
  clk1a3 U128 ( .A(wr_clk), .Y(n119) );
  clk1a3 U129 ( .A(wr_clk), .Y(n118) );
  clk1a3 U130 ( .A(wr_clk), .Y(n117) );
  clk1a3 U131 ( .A(n121), .Y(n108) );
  clk1a3 U132 ( .A(wr_clk), .Y(n121) );
  inv1a1 U133 ( .A(wr_ptr[4]), .Y(n161) );
  inv1a1 U134 ( .A(sync_wr_ptr_1[4]), .Y(n173) );
  xor2b2 U135 ( .A(\gte_316_C117/B[3] ), .B(n56), .Y(n19) );
  xor2b2 U136 ( .A(\gte_316_C183/A[3] ), .B(n53), .Y(n20) );
  xor3a1 U137 ( .A(sync_wr_ptr_1[4]), .B(n149), .C(\sub_317_C183/carry[4] ), 
        .Y(N142) );
  inv1a1 U138 ( .A(\rd_ptr[4]1 ), .Y(n149) );
  xor3a1 U139 ( .A(wr_ptr[4]), .B(n145), .C(\sub_317_C117/carry[4] ), .Y(N31)
         );
  inv1a1 U140 ( .A(sync_rd_ptr_1[4]), .Y(n145) );
  inv1a1 U141 ( .A(sync_wr_ptr[1]), .Y(n172) );
  inv1a1 U142 ( .A(wr_ptr[2]), .Y(n131) );
  inv1a1 U143 ( .A(N23), .Y(n151) );
  inv1a1 U144 ( .A(sync_rd_ptr[1]), .Y(n147) );
  inv1a1 U145 ( .A(N24), .Y(n150) );
  inv1a1 U146 ( .A(wr_ptr[3]), .Y(n130) );
  inv1a1 U147 ( .A(\gte_316_C183/A[3] ), .Y(n139) );
  inv1a1 U148 ( .A(sync_wr_ptr[2]), .Y(n137) );
  inv1a1 U149 ( .A(sync_rd_ptr[2]), .Y(n146) );
  ao1f2 U150 ( .A(n59), .B(n183), .C(n60), .Y(n58) );
  inv1a1 U151 ( .A(empty), .Y(n183) );
  and3d2 U152 ( .A(n61), .B(rd_total_aval[2]), .C(rd_total_aval[1]), .Y(n59)
         );
  inv1a1 U153 ( .A(n62), .Y(rd_total_aval[1]) );
  mx4e3 U154 ( .D0(n33), .D1(n34), .D2(n35), .D3(n36), .S0(N24), .S1(N23), .Y(
        rd_data[3]) );
  mx4e3 U155 ( .D0(\mem[12][3] ), .D1(\mem[13][3] ), .D2(\mem[14][3] ), .D3(
        \mem[15][3] ), .S0(n72), .S1(n77), .Y(n36) );
  mx4e3 U156 ( .D0(n37), .D1(n38), .D2(n39), .D3(n40), .S0(N24), .S1(N23), .Y(
        rd_data[4]) );
  mx4e3 U157 ( .D0(\mem[12][4] ), .D1(\mem[13][4] ), .D2(\mem[14][4] ), .D3(
        \mem[15][4] ), .S0(n72), .S1(n77), .Y(n40) );
  mx4e3 U158 ( .D0(n41), .D1(n42), .D2(n43), .D3(n44), .S0(N24), .S1(N23), .Y(
        rd_data[5]) );
  mx4e3 U159 ( .D0(\mem[12][5] ), .D1(\mem[13][5] ), .D2(\mem[14][5] ), .D3(
        \mem[15][5] ), .S0(n72), .S1(n77), .Y(n44) );
  mx4e3 U160 ( .D0(\mem[0][5] ), .D1(\mem[1][5] ), .D2(\mem[2][5] ), .D3(
        \mem[3][5] ), .S0(n74), .S1(n78), .Y(n41) );
  mx4e3 U161 ( .D0(n45), .D1(n46), .D2(n47), .D3(n48), .S0(N24), .S1(N23), .Y(
        rd_data[6]) );
  mx4e3 U162 ( .D0(\mem[12][6] ), .D1(\mem[13][6] ), .D2(\mem[14][6] ), .D3(
        \mem[15][6] ), .S0(n74), .S1(n78), .Y(n48) );
  mx4e3 U163 ( .D0(\mem[0][6] ), .D1(\mem[1][6] ), .D2(\mem[2][6] ), .D3(
        \mem[3][6] ), .S0(n74), .S1(n78), .Y(n45) );
  mx4e3 U164 ( .D0(n49), .D1(n52), .D2(n55), .D3(n67), .S0(N24), .S1(N23), .Y(
        rd_data[7]) );
  mx4e3 U165 ( .D0(\mem[12][7] ), .D1(\mem[13][7] ), .D2(\mem[14][7] ), .D3(
        \mem[15][7] ), .S0(n74), .S1(n78), .Y(n67) );
  mx4e3 U166 ( .D0(\mem[0][7] ), .D1(\mem[1][7] ), .D2(\mem[2][7] ), .D3(
        \mem[3][7] ), .S0(n74), .S1(n78), .Y(n49) );
  mx4e3 U167 ( .D0(n29), .D1(n30), .D2(n31), .D3(n32), .S0(N24), .S1(N23), .Y(
        rd_data[2]) );
  mx4e3 U168 ( .D0(\mem[8][0] ), .D1(\mem[9][0] ), .D2(\mem[10][0] ), .D3(
        \mem[11][0] ), .S0(n70), .S1(n75), .Y(n22) );
  mx4e3 U169 ( .D0(\mem[8][1] ), .D1(\mem[9][1] ), .D2(\mem[10][1] ), .D3(
        \mem[11][1] ), .S0(n70), .S1(n75), .Y(n26) );
  mx4e3 U170 ( .D0(\mem[8][2] ), .D1(\mem[9][2] ), .D2(\mem[10][2] ), .D3(
        \mem[11][2] ), .S0(n70), .S1(n75), .Y(n30) );
  mx4e3 U171 ( .D0(\mem[8][3] ), .D1(\mem[9][3] ), .D2(\mem[10][3] ), .D3(
        \mem[11][3] ), .S0(n72), .S1(n77), .Y(n34) );
  mx4e3 U172 ( .D0(\mem[8][4] ), .D1(\mem[9][4] ), .D2(\mem[10][4] ), .D3(
        \mem[11][4] ), .S0(n72), .S1(n77), .Y(n38) );
  mx4e3 U173 ( .D0(\mem[8][5] ), .D1(\mem[9][5] ), .D2(\mem[10][5] ), .D3(
        \mem[11][5] ), .S0(n74), .S1(n78), .Y(n42) );
  mx4e3 U174 ( .D0(\mem[8][6] ), .D1(\mem[9][6] ), .D2(\mem[10][6] ), .D3(
        \mem[11][6] ), .S0(n74), .S1(n78), .Y(n46) );
  mx4e3 U175 ( .D0(\mem[8][7] ), .D1(\mem[9][7] ), .D2(\mem[10][7] ), .D3(
        \mem[11][7] ), .S0(n74), .S1(n78), .Y(n52) );
  inv1a3 U176 ( .A(wr_ptr[0]), .Y(wr_ptr_inc[0]) );
  mx4e3 U177 ( .D0(\mem[4][2] ), .D1(\mem[5][2] ), .D2(\mem[6][2] ), .D3(
        \mem[7][2] ), .S0(n72), .S1(n77), .Y(n31) );
  mx4e3 U178 ( .D0(\mem[0][2] ), .D1(\mem[1][2] ), .D2(\mem[2][2] ), .D3(
        \mem[3][2] ), .S0(n72), .S1(n77), .Y(n29) );
  mx4e3 U179 ( .D0(\mem[4][3] ), .D1(\mem[5][3] ), .D2(\mem[6][3] ), .D3(
        \mem[7][3] ), .S0(n72), .S1(n77), .Y(n35) );
  mx4e3 U180 ( .D0(\mem[0][3] ), .D1(\mem[1][3] ), .D2(\mem[2][3] ), .D3(
        \mem[3][3] ), .S0(n72), .S1(n77), .Y(n33) );
  mx4e3 U181 ( .D0(\mem[4][4] ), .D1(\mem[5][4] ), .D2(\mem[6][4] ), .D3(
        \mem[7][4] ), .S0(n72), .S1(n77), .Y(n39) );
  mx4e3 U182 ( .D0(\mem[0][4] ), .D1(\mem[1][4] ), .D2(\mem[2][4] ), .D3(
        \mem[3][4] ), .S0(n72), .S1(n77), .Y(n37) );
  mx4e3 U183 ( .D0(\mem[4][5] ), .D1(\mem[5][5] ), .D2(\mem[6][5] ), .D3(
        \mem[7][5] ), .S0(n74), .S1(n78), .Y(n43) );
  mx4e3 U184 ( .D0(\mem[4][6] ), .D1(\mem[5][6] ), .D2(\mem[6][6] ), .D3(
        \mem[7][6] ), .S0(n74), .S1(n78), .Y(n47) );
  mx4e3 U185 ( .D0(\mem[4][7] ), .D1(\mem[5][7] ), .D2(\mem[6][7] ), .D3(
        \mem[7][7] ), .S0(n74), .S1(n78), .Y(n55) );
  inv1a3 U186 ( .A(wr_ptr[1]), .Y(n181) );
  mx4e3 U187 ( .D0(n21), .D1(n22), .D2(n23), .D3(n24), .S0(N24), .S1(N23), .Y(
        rd_data[0]) );
  mx4e3 U188 ( .D0(\mem[12][0] ), .D1(\mem[13][0] ), .D2(\mem[14][0] ), .D3(
        \mem[15][0] ), .S0(n70), .S1(n75), .Y(n24) );
  mx4e3 U189 ( .D0(\mem[0][0] ), .D1(\mem[1][0] ), .D2(\mem[2][0] ), .D3(
        \mem[3][0] ), .S0(n70), .S1(n75), .Y(n21) );
  mx4e3 U190 ( .D0(\mem[4][0] ), .D1(\mem[5][0] ), .D2(\mem[6][0] ), .D3(
        \mem[7][0] ), .S0(n70), .S1(n75), .Y(n23) );
  mx4e3 U191 ( .D0(n25), .D1(n26), .D2(n27), .D3(n28), .S0(N24), .S1(N23), .Y(
        rd_data[1]) );
  mx4e3 U192 ( .D0(\mem[12][1] ), .D1(\mem[13][1] ), .D2(\mem[14][1] ), .D3(
        \mem[15][1] ), .S0(n70), .S1(n75), .Y(n28) );
  mx4e3 U193 ( .D0(\mem[0][1] ), .D1(\mem[1][1] ), .D2(\mem[2][1] ), .D3(
        \mem[3][1] ), .S0(n70), .S1(n75), .Y(n25) );
  mx4e3 U194 ( .D0(\mem[4][1] ), .D1(\mem[5][1] ), .D2(\mem[6][1] ), .D3(
        \mem[7][1] ), .S0(n70), .S1(n75), .Y(n27) );
  mx4e3 U195 ( .D0(\mem[12][2] ), .D1(\mem[13][2] ), .D2(\mem[14][2] ), .D3(
        \mem[15][2] ), .S0(n70), .S1(n75), .Y(n32) );
  and2a3 U196 ( .A(wr_ptr[3]), .B(wr_en), .Y(n91) );
  inv1a1 U197 ( .A(sync_wr_ptr_1[4]), .Y(n140) );
  inv1a1 U198 ( .A(wr_ptr[4]), .Y(n129) );
  inv1a1 U199 ( .A(n65), .Y(n174) );
  oa1f3 U200 ( .A(n66), .B(full), .C(afull), .Y(n65) );
  and3a2 U201 ( .A(n94), .B(wr_total_free_space[0]), .C(\wr_cnt[1] ), .Y(afull) );
  inv1a1 U202 ( .A(wr_ptr[3]), .Y(n162) );
  inv1a3 U203 ( .A(N21), .Y(n87) );
  inv1a3 U204 ( .A(N22), .Y(n84) );
  xor2a1 U205 ( .A(n1), .B(\sub_320_2_C183/carry[4] ), .Y(N152) );
  and2a1 U206 ( .A(\sub_320_2_C183/carry[3] ), .B(n144), .Y(
        \sub_320_2_C183/carry[4] ) );
  xor2a1 U207 ( .A(n144), .B(\sub_320_2_C183/carry[3] ), .Y(N151) );
  and2a1 U208 ( .A(\sub_320_2_C183/carry[2] ), .B(n143), .Y(
        \sub_320_2_C183/carry[3] ) );
  xor2a1 U209 ( .A(n143), .B(\sub_320_2_C183/carry[2] ), .Y(N150) );
  and2a1 U210 ( .A(n141), .B(n142), .Y(\sub_320_2_C183/carry[2] ) );
  xor2a1 U211 ( .A(n142), .B(n141), .Y(N149) );
  or2a1 U212 ( .A(n138), .B(n86), .Y(\sub_320_C183/carry[1] ) );
  xor2b1 U213 ( .A(n86), .B(n138), .Y(N148) );
  or2a1 U214 ( .A(n87), .B(sync_wr_ptr[0]), .Y(\sub_317_C183/carry[1] ) );
  xor2b1 U215 ( .A(sync_wr_ptr[0]), .B(n87), .Y(N138) );
  xor2a1 U216 ( .A(n2), .B(\sub_320_2_C117/carry[4] ), .Y(N41) );
  and2a1 U217 ( .A(\sub_320_2_C117/carry[3] ), .B(n135), .Y(
        \sub_320_2_C117/carry[4] ) );
  xor2a1 U218 ( .A(n135), .B(\sub_320_2_C117/carry[3] ), .Y(N40) );
  and2a1 U219 ( .A(\sub_320_2_C117/carry[2] ), .B(n134), .Y(
        \sub_320_2_C117/carry[3] ) );
  xor2a1 U220 ( .A(n134), .B(\sub_320_2_C117/carry[2] ), .Y(N39) );
  and2a1 U221 ( .A(n132), .B(n133), .Y(\sub_320_2_C117/carry[2] ) );
  xor2a1 U222 ( .A(n133), .B(n132), .Y(N38) );
  or2a1 U223 ( .A(wr_ptr_inc[0]), .B(sync_rd_ptr[0]), .Y(
        \sub_320_C117/carry[1] ) );
  xor2b1 U224 ( .A(sync_rd_ptr[0]), .B(wr_ptr_inc[0]), .Y(N37) );
  or2a1 U225 ( .A(n148), .B(wr_ptr[0]), .Y(\sub_317_C117/carry[1] ) );
  xor2b1 U226 ( .A(wr_ptr[0]), .B(n148), .Y(N27) );
  and2b1 U227 ( .B(wr_ptr[2]), .A(sync_rd_ptr[2]), .Y(n156) );
  or2b1 U228 ( .B(\gte_316_C117/B[3] ), .A(n156), .Y(n158) );
  ao4d1 U229 ( .B(sync_rd_ptr[1]), .A(wr_ptr[1]), .D(sync_rd_ptr[0]), .C(
        wr_ptr[0]), .Y(n152) );
  ao1f1 U230 ( .A(sync_rd_ptr[1]), .B(n181), .C(n152), .Y(n155) );
  and2b1 U231 ( .B(sync_rd_ptr[2]), .A(wr_ptr[2]), .Y(n153) );
  ao4f1 U232 ( .A(n153), .B(n162), .C(\gte_316_C117/B[3] ), .D(n153), .Y(n154)
         );
  oa4f1 U233 ( .A(wr_ptr[3]), .B(n156), .C(n155), .D(n154), .Y(n157) );
  ao2i1 U234 ( .A(\gte_316_C117/B[3] ), .B(n162), .C(n158), .D(n157), .Y(n159)
         );
  and2b1 U235 ( .B(sync_wr_ptr[2]), .A(N23), .Y(n167) );
  or2b1 U236 ( .B(N24), .A(n167), .Y(n169) );
  ao4d1 U237 ( .B(n82), .A(sync_wr_ptr[1]), .D(n86), .C(sync_wr_ptr[0]), .Y(
        n163) );
  ao1f1 U238 ( .A(n82), .B(n172), .C(n163), .Y(n166) );
  and2b1 U239 ( .B(N23), .A(sync_wr_ptr[2]), .Y(n164) );
  ao4f1 U240 ( .A(n164), .B(n54), .C(N24), .D(n164), .Y(n165) );
  oa4f1 U241 ( .A(\gte_316_C183/A[3] ), .B(n167), .C(n166), .D(n165), .Y(n168)
         );
  ao2i1 U242 ( .A(N24), .B(n54), .C(n169), .D(n168), .Y(n170) );
  ao1d1 U243 ( .A(n173), .B(\rd_ptr[4]1 ), .C(n170), .Y(n171) );
endmodule


module async_fifo_08_10_0_0_1 ( wr_clk, wr_reset_n, wr_en, wr_data, full, 
        afull, wr_total_free_space, rd_clk, rd_reset_n, rd_en, empty, aempty, 
        rd_total_aval, rd_data );
  input [7:0] wr_data;
  output [4:0] wr_total_free_space;
  output [4:0] rd_total_aval;
  output [7:0] rd_data;
  input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n, rd_en;
  output full, afull, empty, aempty;
  wire   N21, N22, N23, N24, N25, N27, N28, N29, N30, N31, N37, N38, N39, N40,
         N41, \wr_cnt[1] , N63, N64, N82, N83, \mem[15][7] , \mem[15][6] ,
         \mem[15][5] , \mem[15][4] , \mem[15][3] , \mem[15][2] , \mem[15][1] ,
         \mem[15][0] , \mem[14][7] , \mem[14][6] , \mem[14][5] , \mem[14][4] ,
         \mem[14][3] , \mem[14][2] , \mem[14][1] , \mem[14][0] , \mem[13][7] ,
         \mem[13][6] , \mem[13][5] , \mem[13][4] , \mem[13][3] , \mem[13][2] ,
         \mem[13][1] , \mem[13][0] , \mem[12][7] , \mem[12][6] , \mem[12][5] ,
         \mem[12][4] , \mem[12][3] , \mem[12][2] , \mem[12][1] , \mem[12][0] ,
         \mem[11][7] , \mem[11][6] , \mem[11][5] , \mem[11][4] , \mem[11][3] ,
         \mem[11][2] , \mem[11][1] , \mem[11][0] , \mem[10][7] , \mem[10][6] ,
         \mem[10][5] , \mem[10][4] , \mem[10][3] , \mem[10][2] , \mem[10][1] ,
         \mem[10][0] , \mem[9][7] , \mem[9][6] , \mem[9][5] , \mem[9][4] ,
         \mem[9][3] , \mem[9][2] , \mem[9][1] , \mem[9][0] , \mem[8][7] ,
         \mem[8][6] , \mem[8][5] , \mem[8][4] , \mem[8][3] , \mem[8][2] ,
         \mem[8][1] , \mem[8][0] , \mem[7][7] , \mem[7][6] , \mem[7][5] ,
         \mem[7][4] , \mem[7][3] , \mem[7][2] , \mem[7][1] , \mem[7][0] ,
         \mem[6][7] , \mem[6][6] , \mem[6][5] , \mem[6][4] , \mem[6][3] ,
         \mem[6][2] , \mem[6][1] , \mem[6][0] , \mem[5][7] , \mem[5][6] ,
         \mem[5][5] , \mem[5][4] , \mem[5][3] , \mem[5][2] , \mem[5][1] ,
         \mem[5][0] , \mem[4][7] , \mem[4][6] , \mem[4][5] , \mem[4][4] ,
         \mem[4][3] , \mem[4][2] , \mem[4][1] , \mem[4][0] , \mem[3][7] ,
         \mem[3][6] , \mem[3][5] , \mem[3][4] , \mem[3][3] , \mem[3][2] ,
         \mem[3][1] , \mem[3][0] , \mem[2][7] , \mem[2][6] , \mem[2][5] ,
         \mem[2][4] , \mem[2][3] , \mem[2][2] , \mem[2][1] , \mem[2][0] ,
         \mem[1][7] , \mem[1][6] , \mem[1][5] , \mem[1][4] , \mem[1][3] ,
         \mem[1][2] , \mem[1][1] , \mem[1][0] , \mem[0][7] , \mem[0][6] ,
         \mem[0][5] , \mem[0][4] , \mem[0][3] , \mem[0][2] , \mem[0][1] ,
         \mem[0][0] , \rd_ptr[4]1 , N136, N138, N139, N140, N141, N142, N148,
         N149, N150, N151, N152, N174, N175, N193, N194, N35, N34, N33, N146,
         N145, N144, \gte_316_C183/A[3] , \gte_316_C117/B[3] ,
         \sub_317_C183/carry[4] , \sub_317_C183/carry[3] ,
         \sub_317_C183/carry[2] , \sub_317_C183/carry[1] , \add_181/carry[4] ,
         \add_181/carry[3] , \add_181/carry[2] , \sub_317_C117/carry[4] ,
         \sub_317_C117/carry[3] , \sub_317_C117/carry[2] ,
         \sub_317_C117/carry[1] , \add_116/carry[4] , \add_116/carry[3] ,
         \add_116/carry[2] , \sub_320_2_C183/carry[4] ,
         \sub_320_2_C183/carry[3] , \sub_320_2_C183/carry[2] ,
         \sub_320_C183/carry[4] , \sub_320_C183/carry[3] ,
         \sub_320_C183/carry[2] , \sub_320_C183/carry[1] ,
         \sub_320_2_C117/carry[4] , \sub_320_2_C117/carry[3] ,
         \sub_320_2_C117/carry[2] , \sub_320_C117/carry[4] ,
         \sub_320_C117/carry[3] , \sub_320_C117/carry[2] ,
         \sub_320_C117/carry[1] , n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11,
         n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
         n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
         n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n52, n55, n67, n70,
         n72, n74, n75, n77, n78, n81, n82, n84, n86, n87, n88, n89, n90, n92,
         n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106,
         n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
         n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
         n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139,
         n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
         n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
         n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172,
         n173, n174, n175, n180, n181, n182, n183, n185, n186, n187, n188,
         n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
         n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
         n211;
  wire   [4:0] wr_ptr;
  wire   [4:0] wr_ptr_inc;
  wire   [4:0] sync_rd_ptr;
  wire   [4:0] grey_wr_ptr;
  wire   [4:0] grey_rd_ptr_dly;
  wire   [4:0] sync_rd_ptr_1;
  wire   [4:0] sync_rd_ptr_0;
  wire   [4:0] rd_ptr_inc;
  wire   [4:0] sync_wr_ptr;
  wire   [4:0] sync_wr_ptr_1;
  wire   [4:0] sync_wr_ptr_0;

  xor2a2 U27 ( .A(sync_wr_ptr_1[2]), .B(\gte_316_C183/A[3] ), .Y(
        sync_wr_ptr[2]) );
  xor2b2 U30 ( .A(n208), .B(n209), .Y(sync_wr_ptr[1]) );
  xor2a2 U31 ( .A(sync_wr_ptr_1[2]), .B(sync_wr_ptr_1[1]), .Y(n209) );
  xor2b2 U32 ( .A(sync_wr_ptr_1[4]), .B(sync_wr_ptr_1[3]), .Y(n208) );
  xor2a2 U33 ( .A(sync_rd_ptr_1[2]), .B(\gte_316_C117/B[3] ), .Y(
        sync_rd_ptr[2]) );
  xor2b2 U36 ( .A(n206), .B(n207), .Y(sync_rd_ptr[1]) );
  xor2a2 U37 ( .A(sync_rd_ptr_1[2]), .B(sync_rd_ptr_1[1]), .Y(n207) );
  xor2b2 U38 ( .A(sync_rd_ptr_1[4]), .B(sync_rd_ptr_1[3]), .Y(n206) );
  and2b2 U50 ( .B(n190), .A(wr_ptr[0]), .Y(n195) );
  and2b2 U52 ( .B(n190), .A(wr_ptr_inc[0]), .Y(n194) );
  and2b2 U53 ( .B(n81), .A(wr_ptr[3]), .Y(n190) );
  and2b2 U62 ( .B(wr_ptr[2]), .A(wr_ptr[1]), .Y(n192) );
  and2b2 U64 ( .B(n187), .A(wr_ptr[0]), .Y(n189) );
  and2b2 U66 ( .B(wr_ptr[2]), .A(n181), .Y(n191) );
  and2b2 U67 ( .B(n187), .A(wr_ptr_inc[0]), .Y(n188) );
  oa4f3 U72 ( .A(N142), .B(N136), .C(N152), .D(n182), .Y(n199) );
  ao4a3 U75 ( .A(N138), .B(N136), .C(N148), .D(n182), .Y(rd_total_aval[0]) );
  ao4a3 U78 ( .A(N27), .B(N25), .C(N37), .D(n180), .Y(wr_total_free_space[0])
         );
  oa4f3 U80 ( .A(N30), .B(N25), .C(N40), .D(n180), .Y(n211) );
  oa4f3 U81 ( .A(N31), .B(N25), .C(N41), .D(n180), .Y(n197) );
  oa4f3 U82 ( .A(N29), .B(N25), .C(N39), .D(n180), .Y(n210) );
  xor2a2 U83 ( .A(wr_ptr_inc[4]), .B(wr_ptr_inc[3]), .Y(N83) );
  xor2a2 U84 ( .A(wr_ptr_inc[3]), .B(wr_ptr_inc[2]), .Y(N82) );
  xor2a2 U85 ( .A(wr_ptr_inc[2]), .B(wr_ptr_inc[1]), .Y(N64) );
  xor2a2 U86 ( .A(wr_ptr_inc[1]), .B(wr_ptr_inc[0]), .Y(N63) );
  xor2a2 U87 ( .A(rd_ptr_inc[4]), .B(rd_ptr_inc[3]), .Y(N194) );
  xor2a2 U88 ( .A(rd_ptr_inc[3]), .B(rd_ptr_inc[2]), .Y(N193) );
  xor2a2 U89 ( .A(rd_ptr_inc[2]), .B(rd_ptr_inc[1]), .Y(N175) );
  xor2a2 U90 ( .A(rd_ptr_inc[1]), .B(n87), .Y(N174) );
  fa1a2 \sub_317_C183/U2_1  ( .A(sync_wr_ptr[1]), .B(n84), .CI(
        \sub_317_C183/carry[1] ), .CO(\sub_317_C183/carry[2] ), .S(N139) );
  fa1a2 \sub_317_C183/U2_2  ( .A(sync_wr_ptr[2]), .B(n151), .CI(
        \sub_317_C183/carry[2] ), .CO(\sub_317_C183/carry[3] ), .S(N140) );
  fa1a2 \sub_317_C183/U2_3  ( .A(\gte_316_C183/A[3] ), .B(n150), .CI(
        \sub_317_C183/carry[3] ), .CO(\sub_317_C183/carry[4] ), .S(N141) );
  ha1a2 \add_181/U1_1_1  ( .A(n82), .B(n86), .CO(\add_181/carry[2] ), .S(
        rd_ptr_inc[1]) );
  ha1a2 \add_181/U1_1_2  ( .A(N23), .B(\add_181/carry[2] ), .CO(
        \add_181/carry[3] ), .S(rd_ptr_inc[2]) );
  ha1a2 \add_181/U1_1_3  ( .A(N24), .B(\add_181/carry[3] ), .CO(
        \add_181/carry[4] ), .S(rd_ptr_inc[3]) );
  fa1a2 \sub_317_C117/U2_1  ( .A(wr_ptr[1]), .B(n147), .CI(
        \sub_317_C117/carry[1] ), .CO(\sub_317_C117/carry[2] ), .S(N28) );
  fa1a2 \sub_317_C117/U2_2  ( .A(wr_ptr[2]), .B(n146), .CI(
        \sub_317_C117/carry[2] ), .CO(\sub_317_C117/carry[3] ), .S(N29) );
  fa1a2 \sub_317_C117/U2_3  ( .A(wr_ptr[3]), .B(n206), .CI(
        \sub_317_C117/carry[3] ), .CO(\sub_317_C117/carry[4] ), .S(N30) );
  ha1a2 \add_116/U1_1_1  ( .A(wr_ptr[1]), .B(wr_ptr[0]), .CO(
        \add_116/carry[2] ), .S(wr_ptr_inc[1]) );
  ha1a2 \add_116/U1_1_2  ( .A(wr_ptr[2]), .B(\add_116/carry[2] ), .CO(
        \add_116/carry[3] ), .S(wr_ptr_inc[2]) );
  ha1a2 \add_116/U1_1_3  ( .A(wr_ptr[3]), .B(\add_116/carry[3] ), .CO(
        \add_116/carry[4] ), .S(wr_ptr_inc[3]) );
  fa1a2 \sub_320_C183/U2_1  ( .A(n82), .B(n136), .CI(\sub_320_C183/carry[1] ), 
        .CO(\sub_320_C183/carry[2] ), .S(N144) );
  fa1a2 \sub_320_C183/U2_2  ( .A(N23), .B(n137), .CI(\sub_320_C183/carry[2] ), 
        .CO(\sub_320_C183/carry[3] ), .S(N145) );
  fa1a2 \sub_320_C183/U2_3  ( .A(N24), .B(n139), .CI(\sub_320_C183/carry[3] ), 
        .CO(\sub_320_C183/carry[4] ), .S(N146) );
  fa1a2 \sub_320_C117/U2_1  ( .A(sync_rd_ptr[1]), .B(n181), .CI(
        \sub_320_C117/carry[1] ), .CO(\sub_320_C117/carry[2] ), .S(N33) );
  fa1a2 \sub_320_C117/U2_2  ( .A(sync_rd_ptr[2]), .B(n131), .CI(
        \sub_320_C117/carry[2] ), .CO(\sub_320_C117/carry[3] ), .S(N34) );
  fa1a2 \sub_320_C117/U2_3  ( .A(\gte_316_C117/B[3] ), .B(n130), .CI(
        \sub_320_C117/carry[3] ), .CO(\sub_320_C117/carry[4] ), .S(N35) );
  fdef1a3 \mem_reg[15][7]  ( .D(wr_data[7]), .E(n15), .CLK(n99), .Q(
        \mem[15][7] ) );
  fdef1a3 \mem_reg[15][6]  ( .D(wr_data[6]), .E(n15), .CLK(n99), .Q(
        \mem[15][6] ) );
  fdef1a3 \mem_reg[15][5]  ( .D(wr_data[5]), .E(n15), .CLK(n99), .Q(
        \mem[15][5] ) );
  fdef1a3 \mem_reg[15][4]  ( .D(wr_data[4]), .E(n15), .CLK(n99), .Q(
        \mem[15][4] ) );
  fdef1a3 \mem_reg[15][3]  ( .D(wr_data[3]), .E(n15), .CLK(n99), .Q(
        \mem[15][3] ) );
  fdef1a3 \mem_reg[15][2]  ( .D(wr_data[2]), .E(n15), .CLK(n99), .Q(
        \mem[15][2] ) );
  fdef1a3 \mem_reg[15][1]  ( .D(wr_data[1]), .E(n15), .CLK(n99), .Q(
        \mem[15][1] ) );
  fdef1a3 \mem_reg[15][0]  ( .D(wr_data[0]), .E(n15), .CLK(n99), .Q(
        \mem[15][0] ) );
  fdef1a3 \mem_reg[11][7]  ( .D(wr_data[7]), .E(n11), .CLK(n102), .Q(
        \mem[11][7] ) );
  fdef1a3 \mem_reg[11][6]  ( .D(wr_data[6]), .E(n11), .CLK(n102), .Q(
        \mem[11][6] ) );
  fdef1a3 \mem_reg[11][5]  ( .D(wr_data[5]), .E(n11), .CLK(n102), .Q(
        \mem[11][5] ) );
  fdef1a3 \mem_reg[11][4]  ( .D(wr_data[4]), .E(n11), .CLK(n103), .Q(
        \mem[11][4] ) );
  fdef1a3 \mem_reg[11][3]  ( .D(wr_data[3]), .E(n11), .CLK(n103), .Q(
        \mem[11][3] ) );
  fdef1a3 \mem_reg[11][2]  ( .D(wr_data[2]), .E(n11), .CLK(n103), .Q(
        \mem[11][2] ) );
  fdef1a3 \mem_reg[11][1]  ( .D(wr_data[1]), .E(n11), .CLK(n103), .Q(
        \mem[11][1] ) );
  fdef1a3 \mem_reg[11][0]  ( .D(wr_data[0]), .E(n11), .CLK(n103), .Q(
        \mem[11][0] ) );
  fdef1a3 \mem_reg[7][7]  ( .D(wr_data[7]), .E(n7), .CLK(n106), .Q(\mem[7][7] ) );
  fdef1a3 \mem_reg[7][6]  ( .D(wr_data[6]), .E(n7), .CLK(n106), .Q(\mem[7][6] ) );
  fdef1a3 \mem_reg[7][5]  ( .D(wr_data[5]), .E(n7), .CLK(n106), .Q(\mem[7][5] ) );
  fdef1a3 \mem_reg[7][4]  ( .D(wr_data[4]), .E(n7), .CLK(n106), .Q(\mem[7][4] ) );
  fdef1a3 \mem_reg[7][3]  ( .D(wr_data[3]), .E(n7), .CLK(n106), .Q(\mem[7][3] ) );
  fdef1a3 \mem_reg[7][2]  ( .D(wr_data[2]), .E(n7), .CLK(n106), .Q(\mem[7][2] ) );
  fdef1a3 \mem_reg[7][1]  ( .D(wr_data[1]), .E(n7), .CLK(n106), .Q(\mem[7][1] ) );
  fdef1a3 \mem_reg[7][0]  ( .D(wr_data[0]), .E(n7), .CLK(n107), .Q(\mem[7][0] ) );
  fdef1a3 \mem_reg[3][7]  ( .D(wr_data[7]), .E(n18), .CLK(n109), .Q(
        \mem[3][7] ) );
  fdef1a3 \mem_reg[3][6]  ( .D(wr_data[6]), .E(n18), .CLK(n109), .Q(
        \mem[3][6] ) );
  fdef1a3 \mem_reg[3][5]  ( .D(wr_data[5]), .E(n18), .CLK(n110), .Q(
        \mem[3][5] ) );
  fdef1a3 \mem_reg[3][4]  ( .D(wr_data[4]), .E(n18), .CLK(n110), .Q(
        \mem[3][4] ) );
  fdef1a3 \mem_reg[3][3]  ( .D(wr_data[3]), .E(n18), .CLK(n110), .Q(
        \mem[3][3] ) );
  fdef1a3 \mem_reg[3][2]  ( .D(wr_data[2]), .E(n18), .CLK(n110), .Q(
        \mem[3][2] ) );
  fdef1a3 \mem_reg[3][1]  ( .D(wr_data[1]), .E(n18), .CLK(n110), .Q(
        \mem[3][1] ) );
  fdef1a3 \mem_reg[3][0]  ( .D(wr_data[0]), .E(n18), .CLK(n110), .Q(
        \mem[3][0] ) );
  fdf2a3 \sync_rd_ptr_1_reg[1]  ( .D(sync_rd_ptr_0[1]), .CLK(n113), .CLR(n97), 
        .Q(sync_rd_ptr_1[1]) );
  fdf2a3 \sync_wr_ptr_1_reg[3]  ( .D(sync_wr_ptr_0[3]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_1[3]) );
  fdf2a3 \sync_rd_ptr_1_reg[3]  ( .D(sync_rd_ptr_0[3]), .CLK(n114), .CLR(n97), 
        .Q(sync_rd_ptr_1[3]) );
  fdf2a3 \sync_wr_ptr_1_reg[1]  ( .D(sync_wr_ptr_0[1]), .CLK(n90), .CLR(n95), 
        .Q(sync_wr_ptr_1[1]) );
  fdef2a3 \rd_ptr_reg[1]  ( .D(rd_ptr_inc[1]), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(N22) );
  fdef1a3 \mem_reg[14][7]  ( .D(wr_data[7]), .E(n14), .CLK(n100), .Q(
        \mem[14][7] ) );
  fdef1a3 \mem_reg[14][6]  ( .D(wr_data[6]), .E(n14), .CLK(n100), .Q(
        \mem[14][6] ) );
  fdef1a3 \mem_reg[14][5]  ( .D(wr_data[5]), .E(n14), .CLK(n100), .Q(
        \mem[14][5] ) );
  fdef1a3 \mem_reg[14][4]  ( .D(wr_data[4]), .E(n14), .CLK(n100), .Q(
        \mem[14][4] ) );
  fdef1a3 \mem_reg[14][3]  ( .D(wr_data[3]), .E(n14), .CLK(n100), .Q(
        \mem[14][3] ) );
  fdef1a3 \mem_reg[14][2]  ( .D(wr_data[2]), .E(n14), .CLK(n100), .Q(
        \mem[14][2] ) );
  fdef1a3 \mem_reg[14][1]  ( .D(wr_data[1]), .E(n14), .CLK(n100), .Q(
        \mem[14][1] ) );
  fdef1a3 \mem_reg[14][0]  ( .D(wr_data[0]), .E(n14), .CLK(n100), .Q(
        \mem[14][0] ) );
  fdef1a3 \mem_reg[12][7]  ( .D(wr_data[7]), .E(n12), .CLK(n101), .Q(
        \mem[12][7] ) );
  fdef1a3 \mem_reg[12][6]  ( .D(wr_data[6]), .E(n12), .CLK(n101), .Q(
        \mem[12][6] ) );
  fdef1a3 \mem_reg[12][5]  ( .D(wr_data[5]), .E(n12), .CLK(n102), .Q(
        \mem[12][5] ) );
  fdef1a3 \mem_reg[12][4]  ( .D(wr_data[4]), .E(n12), .CLK(n102), .Q(
        \mem[12][4] ) );
  fdef1a3 \mem_reg[12][3]  ( .D(wr_data[3]), .E(n12), .CLK(n102), .Q(
        \mem[12][3] ) );
  fdef1a3 \mem_reg[12][2]  ( .D(wr_data[2]), .E(n12), .CLK(n102), .Q(
        \mem[12][2] ) );
  fdef1a3 \mem_reg[12][1]  ( .D(wr_data[1]), .E(n12), .CLK(n102), .Q(
        \mem[12][1] ) );
  fdef1a3 \mem_reg[12][0]  ( .D(wr_data[0]), .E(n12), .CLK(n102), .Q(
        \mem[12][0] ) );
  fdef1a3 \mem_reg[10][7]  ( .D(wr_data[7]), .E(n10), .CLK(n103), .Q(
        \mem[10][7] ) );
  fdef1a3 \mem_reg[10][6]  ( .D(wr_data[6]), .E(n10), .CLK(n103), .Q(
        \mem[10][6] ) );
  fdef1a3 \mem_reg[10][5]  ( .D(wr_data[5]), .E(n10), .CLK(n103), .Q(
        \mem[10][5] ) );
  fdef1a3 \mem_reg[10][4]  ( .D(wr_data[4]), .E(n10), .CLK(n103), .Q(
        \mem[10][4] ) );
  fdef1a3 \mem_reg[10][3]  ( .D(wr_data[3]), .E(n10), .CLK(n104), .Q(
        \mem[10][3] ) );
  fdef1a3 \mem_reg[10][2]  ( .D(wr_data[2]), .E(n10), .CLK(n104), .Q(
        \mem[10][2] ) );
  fdef1a3 \mem_reg[10][1]  ( .D(wr_data[1]), .E(n10), .CLK(n104), .Q(
        \mem[10][1] ) );
  fdef1a3 \mem_reg[10][0]  ( .D(wr_data[0]), .E(n10), .CLK(n104), .Q(
        \mem[10][0] ) );
  fdef1a3 \mem_reg[8][7]  ( .D(wr_data[7]), .E(n8), .CLK(n105), .Q(\mem[8][7] ) );
  fdef1a3 \mem_reg[8][6]  ( .D(wr_data[6]), .E(n8), .CLK(n105), .Q(\mem[8][6] ) );
  fdef1a3 \mem_reg[8][5]  ( .D(wr_data[5]), .E(n8), .CLK(n105), .Q(\mem[8][5] ) );
  fdef1a3 \mem_reg[8][4]  ( .D(wr_data[4]), .E(n8), .CLK(n105), .Q(\mem[8][4] ) );
  fdef1a3 \mem_reg[8][3]  ( .D(wr_data[3]), .E(n8), .CLK(n105), .Q(\mem[8][3] ) );
  fdef1a3 \mem_reg[8][2]  ( .D(wr_data[2]), .E(n8), .CLK(n105), .Q(\mem[8][2] ) );
  fdef1a3 \mem_reg[8][1]  ( .D(wr_data[1]), .E(n8), .CLK(n106), .Q(\mem[8][1] ) );
  fdef1a3 \mem_reg[8][0]  ( .D(wr_data[0]), .E(n8), .CLK(n106), .Q(\mem[8][0] ) );
  fdef1a3 \mem_reg[6][7]  ( .D(wr_data[7]), .E(n6), .CLK(n107), .Q(\mem[6][7] ) );
  fdef1a3 \mem_reg[6][6]  ( .D(wr_data[6]), .E(n6), .CLK(n107), .Q(\mem[6][6] ) );
  fdef1a3 \mem_reg[6][5]  ( .D(wr_data[5]), .E(n6), .CLK(n107), .Q(\mem[6][5] ) );
  fdef1a3 \mem_reg[6][4]  ( .D(wr_data[4]), .E(n6), .CLK(n107), .Q(\mem[6][4] ) );
  fdef1a3 \mem_reg[6][3]  ( .D(wr_data[3]), .E(n6), .CLK(n107), .Q(\mem[6][3] ) );
  fdef1a3 \mem_reg[6][2]  ( .D(wr_data[2]), .E(n6), .CLK(n107), .Q(\mem[6][2] ) );
  fdef1a3 \mem_reg[6][1]  ( .D(wr_data[1]), .E(n6), .CLK(n107), .Q(\mem[6][1] ) );
  fdef1a3 \mem_reg[6][0]  ( .D(wr_data[0]), .E(n6), .CLK(n107), .Q(\mem[6][0] ) );
  fdef1a3 \mem_reg[4][7]  ( .D(wr_data[7]), .E(n4), .CLK(n108), .Q(\mem[4][7] ) );
  fdef1a3 \mem_reg[4][6]  ( .D(wr_data[6]), .E(n4), .CLK(n109), .Q(\mem[4][6] ) );
  fdef1a3 \mem_reg[4][5]  ( .D(wr_data[5]), .E(n4), .CLK(n109), .Q(\mem[4][5] ) );
  fdef1a3 \mem_reg[4][4]  ( .D(wr_data[4]), .E(n4), .CLK(n109), .Q(\mem[4][4] ) );
  fdef1a3 \mem_reg[4][3]  ( .D(wr_data[3]), .E(n4), .CLK(n109), .Q(\mem[4][3] ) );
  fdef1a3 \mem_reg[4][2]  ( .D(wr_data[2]), .E(n4), .CLK(n109), .Q(\mem[4][2] ) );
  fdef1a3 \mem_reg[4][1]  ( .D(wr_data[1]), .E(n4), .CLK(n109), .Q(\mem[4][1] ) );
  fdef1a3 \mem_reg[4][0]  ( .D(wr_data[0]), .E(n4), .CLK(n109), .Q(\mem[4][0] ) );
  fdef1a3 \mem_reg[2][7]  ( .D(wr_data[7]), .E(n17), .CLK(n110), .Q(
        \mem[2][7] ) );
  fdef1a3 \mem_reg[2][6]  ( .D(wr_data[6]), .E(n17), .CLK(n110), .Q(
        \mem[2][6] ) );
  fdef1a3 \mem_reg[2][5]  ( .D(wr_data[5]), .E(n17), .CLK(n110), .Q(
        \mem[2][5] ) );
  fdef1a3 \mem_reg[2][4]  ( .D(wr_data[4]), .E(n17), .CLK(n111), .Q(
        \mem[2][4] ) );
  fdef1a3 \mem_reg[2][3]  ( .D(wr_data[3]), .E(n17), .CLK(n111), .Q(
        \mem[2][3] ) );
  fdef1a3 \mem_reg[2][2]  ( .D(wr_data[2]), .E(n17), .CLK(n111), .Q(
        \mem[2][2] ) );
  fdef1a3 \mem_reg[2][1]  ( .D(wr_data[1]), .E(n17), .CLK(n111), .Q(
        \mem[2][1] ) );
  fdef1a3 \mem_reg[2][0]  ( .D(wr_data[0]), .E(n17), .CLK(n111), .Q(
        \mem[2][0] ) );
  fdef1a3 \mem_reg[0][7]  ( .D(wr_data[7]), .E(n16), .CLK(n112), .Q(
        \mem[0][7] ) );
  fdef1a3 \mem_reg[0][6]  ( .D(wr_data[6]), .E(n16), .CLK(n112), .Q(
        \mem[0][6] ) );
  fdef1a3 \mem_reg[0][5]  ( .D(wr_data[5]), .E(n16), .CLK(n112), .Q(
        \mem[0][5] ) );
  fdef1a3 \mem_reg[0][4]  ( .D(wr_data[4]), .E(n16), .CLK(n112), .Q(
        \mem[0][4] ) );
  fdef1a3 \mem_reg[0][3]  ( .D(wr_data[3]), .E(n16), .CLK(n112), .Q(
        \mem[0][3] ) );
  fdef1a3 \mem_reg[0][2]  ( .D(wr_data[2]), .E(n16), .CLK(n113), .Q(
        \mem[0][2] ) );
  fdef1a3 \mem_reg[0][1]  ( .D(wr_data[1]), .E(n16), .CLK(n113), .Q(
        \mem[0][1] ) );
  fdef1a3 \mem_reg[0][0]  ( .D(wr_data[0]), .E(n16), .CLK(n113), .Q(
        \mem[0][0] ) );
  fdef1a3 \mem_reg[13][7]  ( .D(wr_data[7]), .E(n13), .CLK(n100), .Q(
        \mem[13][7] ) );
  fdef1a3 \mem_reg[13][6]  ( .D(wr_data[6]), .E(n13), .CLK(n101), .Q(
        \mem[13][6] ) );
  fdef1a3 \mem_reg[13][5]  ( .D(wr_data[5]), .E(n13), .CLK(n101), .Q(
        \mem[13][5] ) );
  fdef1a3 \mem_reg[13][4]  ( .D(wr_data[4]), .E(n13), .CLK(n101), .Q(
        \mem[13][4] ) );
  fdef1a3 \mem_reg[13][3]  ( .D(wr_data[3]), .E(n13), .CLK(n101), .Q(
        \mem[13][3] ) );
  fdef1a3 \mem_reg[13][2]  ( .D(wr_data[2]), .E(n13), .CLK(n101), .Q(
        \mem[13][2] ) );
  fdef1a3 \mem_reg[13][1]  ( .D(wr_data[1]), .E(n13), .CLK(n101), .Q(
        \mem[13][1] ) );
  fdef1a3 \mem_reg[13][0]  ( .D(wr_data[0]), .E(n13), .CLK(n101), .Q(
        \mem[13][0] ) );
  fdef1a3 \mem_reg[9][7]  ( .D(wr_data[7]), .E(n9), .CLK(n104), .Q(\mem[9][7] ) );
  fdef1a3 \mem_reg[9][6]  ( .D(wr_data[6]), .E(n9), .CLK(n104), .Q(\mem[9][6] ) );
  fdef1a3 \mem_reg[9][5]  ( .D(wr_data[5]), .E(n9), .CLK(n104), .Q(\mem[9][5] ) );
  fdef1a3 \mem_reg[9][4]  ( .D(wr_data[4]), .E(n9), .CLK(n104), .Q(\mem[9][4] ) );
  fdef1a3 \mem_reg[9][3]  ( .D(wr_data[3]), .E(n9), .CLK(n104), .Q(\mem[9][3] ) );
  fdef1a3 \mem_reg[9][2]  ( .D(wr_data[2]), .E(n9), .CLK(n105), .Q(\mem[9][2] ) );
  fdef1a3 \mem_reg[9][1]  ( .D(wr_data[1]), .E(n9), .CLK(n105), .Q(\mem[9][1] ) );
  fdef1a3 \mem_reg[9][0]  ( .D(wr_data[0]), .E(n9), .CLK(n105), .Q(\mem[9][0] ) );
  fdef1a3 \mem_reg[5][7]  ( .D(wr_data[7]), .E(n5), .CLK(n108), .Q(\mem[5][7] ) );
  fdef1a3 \mem_reg[5][6]  ( .D(wr_data[6]), .E(n5), .CLK(n108), .Q(\mem[5][6] ) );
  fdef1a3 \mem_reg[5][5]  ( .D(wr_data[5]), .E(n5), .CLK(n108), .Q(\mem[5][5] ) );
  fdef1a3 \mem_reg[5][4]  ( .D(wr_data[4]), .E(n5), .CLK(n108), .Q(\mem[5][4] ) );
  fdef1a3 \mem_reg[5][3]  ( .D(wr_data[3]), .E(n5), .CLK(n108), .Q(\mem[5][3] ) );
  fdef1a3 \mem_reg[5][2]  ( .D(wr_data[2]), .E(n5), .CLK(n108), .Q(\mem[5][2] ) );
  fdef1a3 \mem_reg[5][1]  ( .D(wr_data[1]), .E(n5), .CLK(n108), .Q(\mem[5][1] ) );
  fdef1a3 \mem_reg[5][0]  ( .D(wr_data[0]), .E(n5), .CLK(n108), .Q(\mem[5][0] ) );
  fdef1a3 \mem_reg[1][7]  ( .D(wr_data[7]), .E(n3), .CLK(n111), .Q(\mem[1][7] ) );
  fdef1a3 \mem_reg[1][6]  ( .D(wr_data[6]), .E(n3), .CLK(n111), .Q(\mem[1][6] ) );
  fdef1a3 \mem_reg[1][5]  ( .D(wr_data[5]), .E(n3), .CLK(n111), .Q(\mem[1][5] ) );
  fdef1a3 \mem_reg[1][4]  ( .D(wr_data[4]), .E(n3), .CLK(n111), .Q(\mem[1][4] ) );
  fdef1a3 \mem_reg[1][3]  ( .D(wr_data[3]), .E(n3), .CLK(n112), .Q(\mem[1][3] ) );
  fdef1a3 \mem_reg[1][2]  ( .D(wr_data[2]), .E(n3), .CLK(n112), .Q(\mem[1][2] ) );
  fdef1a3 \mem_reg[1][1]  ( .D(wr_data[1]), .E(n3), .CLK(n112), .Q(\mem[1][1] ) );
  fdef1a3 \mem_reg[1][0]  ( .D(wr_data[0]), .E(n3), .CLK(n112), .Q(\mem[1][0] ) );
  fdef2a3 full_q_reg ( .D(n81), .E(n174), .CLK(n114), .CLR(n96), .Q(full) );
  fdf2a3 \sync_rd_ptr_1_reg[0]  ( .D(sync_rd_ptr_0[0]), .CLK(n113), .CLR(n97), 
        .Q(sync_rd_ptr_1[0]) );
  fdf2a3 \sync_wr_ptr_1_reg[0]  ( .D(sync_wr_ptr_0[0]), .CLK(n90), .CLR(n95), 
        .Q(sync_wr_ptr_1[0]) );
  fdef2a3 \rd_ptr_reg[0]  ( .D(n87), .E(rd_en), .CLK(n88), .CLR(n92), .Q(N21)
         );
  fdf2a3 \sync_rd_ptr_1_reg[2]  ( .D(sync_rd_ptr_0[2]), .CLK(n113), .CLR(n97), 
        .Q(sync_rd_ptr_1[2]) );
  fdf2a3 \sync_wr_ptr_1_reg[2]  ( .D(sync_wr_ptr_0[2]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_1[2]) );
  fdef2a3 \rd_ptr_reg[4]  ( .D(rd_ptr_inc[4]), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(\rd_ptr[4]1 ) );
  fdef2a3 \wr_ptr_reg[4]  ( .D(wr_ptr_inc[4]), .E(n81), .CLK(n98), .CLR(n96), 
        .Q(wr_ptr[4]) );
  fdef3a3 empty_q_reg ( .D(rd_en), .E(n205), .CLK(n90), .PRE(n95), .Q(empty)
         );
  fdef2a6 \wr_ptr_reg[2]  ( .D(wr_ptr_inc[2]), .E(n81), .CLK(n98), .CLR(n96), 
        .Q(wr_ptr[2]) );
  fdf2a3 \sync_rd_ptr_1_reg[4]  ( .D(sync_rd_ptr_0[4]), .CLK(n114), .CLR(n97), 
        .Q(sync_rd_ptr_1[4]) );
  fdf2a3 \sync_wr_ptr_1_reg[4]  ( .D(sync_wr_ptr_0[4]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_1[4]) );
  fdef2a9 \rd_ptr_reg[3]  ( .D(rd_ptr_inc[3]), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(N24) );
  fdef2a3 \grey_wr_ptr_reg[0]  ( .D(N63), .E(n81), .CLK(n98), .CLR(n96), .Q(
        grey_wr_ptr[0]) );
  fdef2a3 \grey_wr_ptr_reg[1]  ( .D(N64), .E(n81), .CLK(n98), .CLR(n96), .Q(
        grey_wr_ptr[1]) );
  fdef2a3 \grey_wr_ptr_reg[2]  ( .D(N82), .E(n81), .CLK(n98), .CLR(n96), .Q(
        grey_wr_ptr[2]) );
  fdef2a3 \grey_wr_ptr_reg[4]  ( .D(wr_ptr_inc[4]), .E(n81), .CLK(n98), .CLR(
        n96), .Q(grey_wr_ptr[4]) );
  fdef2a3 \grey_wr_ptr_reg[3]  ( .D(N83), .E(n81), .CLK(n99), .CLR(n96), .Q(
        grey_wr_ptr[3]) );
  fdef2a3 \grey_rd_ptr_reg[4]  ( .D(rd_ptr_inc[4]), .E(rd_en), .CLK(n88), 
        .CLR(n92), .Q(grey_rd_ptr_dly[4]) );
  fdef2a3 \wr_ptr_reg[3]  ( .D(wr_ptr_inc[3]), .E(n81), .CLK(n98), .CLR(n96), 
        .Q(wr_ptr[3]) );
  fdef2a6 \rd_ptr_reg[2]  ( .D(rd_ptr_inc[2]), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(N23) );
  fdef2a3 \grey_rd_ptr_reg[0]  ( .D(N174), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(grey_rd_ptr_dly[0]) );
  fdef2a3 \grey_rd_ptr_reg[1]  ( .D(N175), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(grey_rd_ptr_dly[1]) );
  fdef2a3 \grey_rd_ptr_reg[2]  ( .D(N193), .E(rd_en), .CLK(n88), .CLR(n92), 
        .Q(grey_rd_ptr_dly[2]) );
  fdef2a3 \grey_rd_ptr_reg[3]  ( .D(N194), .E(rd_en), .CLK(n89), .CLR(n92), 
        .Q(grey_rd_ptr_dly[3]) );
  fdf2a3 \sync_rd_ptr_0_reg[0]  ( .D(grey_rd_ptr_dly[0]), .CLK(n113), .CLR(n97), .Q(sync_rd_ptr_0[0]) );
  fdf2a3 \sync_rd_ptr_0_reg[1]  ( .D(grey_rd_ptr_dly[1]), .CLK(n113), .CLR(n97), .Q(sync_rd_ptr_0[1]) );
  fdf2a3 \sync_rd_ptr_0_reg[2]  ( .D(grey_rd_ptr_dly[2]), .CLK(n113), .CLR(n97), .Q(sync_rd_ptr_0[2]) );
  fdf2a3 \sync_wr_ptr_0_reg[4]  ( .D(grey_wr_ptr[4]), .CLK(n89), .CLR(n92), 
        .Q(sync_wr_ptr_0[4]) );
  fdf2a3 \sync_wr_ptr_0_reg[3]  ( .D(grey_wr_ptr[3]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_0[3]) );
  fdf2a3 \sync_wr_ptr_0_reg[2]  ( .D(grey_wr_ptr[2]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_0[2]) );
  fdf2a3 \sync_wr_ptr_0_reg[1]  ( .D(grey_wr_ptr[1]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_0[1]) );
  fdf2a3 \sync_wr_ptr_0_reg[0]  ( .D(grey_wr_ptr[0]), .CLK(n89), .CLR(n95), 
        .Q(sync_wr_ptr_0[0]) );
  fdf2a3 \sync_rd_ptr_0_reg[4]  ( .D(grey_rd_ptr_dly[4]), .CLK(n114), .CLR(n97), .Q(sync_rd_ptr_0[4]) );
  fdf2a3 \sync_rd_ptr_0_reg[3]  ( .D(grey_rd_ptr_dly[3]), .CLK(n114), .CLR(n97), .Q(sync_rd_ptr_0[3]) );
  fdef2a3 \wr_ptr_reg[0]  ( .D(wr_ptr_inc[0]), .E(n81), .CLK(n98), .CLR(n96), 
        .Q(wr_ptr[0]) );
  fdef2a3 \wr_ptr_reg[1]  ( .D(wr_ptr_inc[1]), .E(n81), .CLK(n98), .CLR(n96), 
        .Q(wr_ptr[1]) );
  and2c3 U3 ( .A(wr_ptr[1]), .B(wr_ptr[2]), .Y(n196) );
  and2c3 U4 ( .A(n181), .B(wr_ptr[2]), .Y(n193) );
  xor3b3 U5 ( .A(\rd_ptr[4]1 ), .B(n140), .C(\sub_320_C183/carry[4] ), .Y(n1)
         );
  xor3b3 U6 ( .A(sync_rd_ptr_1[4]), .B(n129), .C(\sub_320_C117/carry[4] ), .Y(
        n2) );
  and2a6 U7 ( .A(n189), .B(n193), .Y(n10) );
  and2a6 U8 ( .A(n188), .B(n196), .Y(n9) );
  and2a6 U9 ( .A(n191), .B(n195), .Y(n6) );
  and2a6 U10 ( .A(n192), .B(n194), .Y(n5) );
  and2a6 U11 ( .A(n188), .B(n193), .Y(n11) );
  and2a6 U12 ( .A(n189), .B(n196), .Y(n8) );
  and2a6 U13 ( .A(n191), .B(n194), .Y(n7) );
  and2a6 U14 ( .A(n192), .B(n195), .Y(n4) );
  and2a6 U15 ( .A(n189), .B(n191), .Y(n14) );
  and2a6 U16 ( .A(n188), .B(n192), .Y(n13) );
  and2a6 U17 ( .A(n193), .B(n195), .Y(n17) );
  and2a6 U18 ( .A(n194), .B(n196), .Y(n3) );
  and2a6 U19 ( .A(n188), .B(n191), .Y(n15) );
  and2a6 U20 ( .A(n189), .B(n192), .Y(n12) );
  and2a6 U21 ( .A(n193), .B(n194), .Y(n18) );
  and2a6 U22 ( .A(n196), .B(n195), .Y(n16) );
  oa4f3 U23 ( .A(N141), .B(N136), .C(N151), .D(n182), .Y(n200) );
  oa4f2 U24 ( .A(N139), .B(N136), .C(N149), .D(n182), .Y(n201) );
  ao1f9 U25 ( .A(\rd_ptr[4]1 ), .B(n173), .C(n171), .Y(N136) );
  ao1f9 U26 ( .A(sync_rd_ptr_1[4]), .B(n161), .C(n160), .Y(N25) );
  ao1d2 U28 ( .A(n161), .B(sync_rd_ptr_1[4]), .C(n159), .Y(n160) );
  ao4a1 U29 ( .A(N140), .B(N136), .C(N150), .D(n182), .Y(rd_total_aval[2]) );
  ao4a1 U34 ( .A(N28), .B(N25), .C(N38), .D(n180), .Y(\wr_cnt[1] ) );
  xor2a2 U35 ( .A(\add_181/carry[4] ), .B(\rd_ptr[4]1 ), .Y(rd_ptr_inc[4]) );
  xor2a2 U39 ( .A(\add_116/carry[4] ), .B(wr_ptr[4]), .Y(wr_ptr_inc[4]) );
  ao4b2 U40 ( .C(sync_wr_ptr_1[0]), .D(n20), .B(sync_wr_ptr[1]), .A(
        sync_wr_ptr_1[0]), .Y(sync_wr_ptr[0]) );
  ao4b2 U41 ( .C(sync_rd_ptr_1[0]), .D(n19), .B(sync_rd_ptr[1]), .A(
        sync_rd_ptr_1[0]), .Y(sync_rd_ptr[0]) );
  or3d1 U42 ( .A(rd_total_aval[0]), .B(n201), .C(n186), .Y(n203) );
  inv1a1 U43 ( .A(N148), .Y(n141) );
  inv1a1 U44 ( .A(N144), .Y(n142) );
  clk1a3 U45 ( .A(n116), .Y(n112) );
  clk1a3 U46 ( .A(n116), .Y(n111) );
  clk1a3 U47 ( .A(n117), .Y(n110) );
  clk1a3 U48 ( .A(n117), .Y(n109) );
  clk1a3 U49 ( .A(n118), .Y(n108) );
  clk1a3 U51 ( .A(n118), .Y(n107) );
  clk1a3 U54 ( .A(n119), .Y(n106) );
  clk1a3 U55 ( .A(n119), .Y(n105) );
  clk1a3 U56 ( .A(n120), .Y(n104) );
  clk1a3 U57 ( .A(n120), .Y(n103) );
  clk1a3 U58 ( .A(n121), .Y(n102) );
  clk1a3 U59 ( .A(n121), .Y(n101) );
  clk1a3 U60 ( .A(n122), .Y(n100) );
  clk1a3 U61 ( .A(n122), .Y(n99) );
  inv1a1 U63 ( .A(sync_wr_ptr[1]), .Y(n136) );
  inv1a1 U65 ( .A(n200), .Y(rd_total_aval[3]) );
  inv1a1 U68 ( .A(N37), .Y(n132) );
  clk1a6 U69 ( .A(n86), .Y(n72) );
  clk1a6 U70 ( .A(n86), .Y(n74) );
  clk1a6 U71 ( .A(n86), .Y(n70) );
  clk1a6 U73 ( .A(n82), .Y(n77) );
  clk1a6 U74 ( .A(n82), .Y(n78) );
  clk1a6 U76 ( .A(n82), .Y(n75) );
  inv1a1 U77 ( .A(n203), .Y(aempty) );
  clk1a3 U79 ( .A(n123), .Y(n98) );
  clk1a3 U91 ( .A(n124), .Y(n123) );
  clk1a3 U92 ( .A(n115), .Y(n113) );
  clk1a3 U93 ( .A(n115), .Y(n114) );
  clk1a3 U94 ( .A(n127), .Y(n116) );
  clk1a3 U95 ( .A(n127), .Y(n117) );
  clk1a3 U96 ( .A(n126), .Y(n118) );
  clk1a3 U97 ( .A(n126), .Y(n119) );
  clk1a3 U98 ( .A(n125), .Y(n120) );
  clk1a3 U99 ( .A(n125), .Y(n121) );
  clk1a3 U100 ( .A(n124), .Y(n122) );
  inv1a3 U101 ( .A(N25), .Y(n180) );
  inv1a3 U102 ( .A(N136), .Y(n182) );
  inv1a3 U103 ( .A(n208), .Y(\gte_316_C183/A[3] ) );
  inv1a3 U104 ( .A(n206), .Y(\gte_316_C117/B[3] ) );
  and3d2 U105 ( .A(rd_total_aval[2]), .B(rd_total_aval[4]), .C(
        rd_total_aval[3]), .Y(n186) );
  and3d2 U106 ( .A(n210), .B(n175), .C(n211), .Y(n185) );
  inv1a1 U107 ( .A(n197), .Y(n175) );
  or2c1 U108 ( .A(n200), .B(n199), .Y(n202) );
  inv1a1 U109 ( .A(n199), .Y(rd_total_aval[4]) );
  inv1a1 U110 ( .A(sync_wr_ptr[0]), .Y(n138) );
  inv1a1 U111 ( .A(sync_rd_ptr[0]), .Y(n148) );
  inv1a1 U112 ( .A(N33), .Y(n133) );
  inv1a1 U113 ( .A(N34), .Y(n134) );
  inv1a1 U114 ( .A(N35), .Y(n135) );
  inv1a1 U115 ( .A(N145), .Y(n143) );
  inv1a1 U116 ( .A(N146), .Y(n144) );
  buf1a9 U117 ( .A(wr_reset_n), .Y(n96) );
  buf1a9 U118 ( .A(rd_reset_n), .Y(n92) );
  clk1a6 U119 ( .A(rd_reset_n), .Y(n95) );
  clk1a6 U120 ( .A(wr_reset_n), .Y(n97) );
  inv1a3 U121 ( .A(n84), .Y(n82) );
  inv1a3 U122 ( .A(n87), .Y(n86) );
  clk1a3 U123 ( .A(rd_clk), .Y(n89) );
  clk1a3 U124 ( .A(rd_clk), .Y(n88) );
  clk1a3 U125 ( .A(rd_clk), .Y(n90) );
  clk1a3 U126 ( .A(wr_clk), .Y(n127) );
  clk1a3 U127 ( .A(wr_clk), .Y(n126) );
  clk1a3 U128 ( .A(wr_clk), .Y(n125) );
  clk1a3 U129 ( .A(wr_clk), .Y(n124) );
  clk1a3 U130 ( .A(n128), .Y(n115) );
  clk1a3 U131 ( .A(wr_clk), .Y(n128) );
  inv1a1 U132 ( .A(wr_ptr[4]), .Y(n161) );
  inv1a1 U133 ( .A(sync_wr_ptr_1[4]), .Y(n173) );
  xor2b2 U134 ( .A(\gte_316_C117/B[3] ), .B(n207), .Y(n19) );
  xor2b2 U135 ( .A(\gte_316_C183/A[3] ), .B(n209), .Y(n20) );
  xor3a1 U136 ( .A(sync_wr_ptr_1[4]), .B(n149), .C(\sub_317_C183/carry[4] ), 
        .Y(N142) );
  inv1a1 U137 ( .A(\rd_ptr[4]1 ), .Y(n149) );
  xor3a1 U138 ( .A(wr_ptr[4]), .B(n145), .C(\sub_317_C117/carry[4] ), .Y(N31)
         );
  inv1a1 U139 ( .A(sync_rd_ptr_1[4]), .Y(n145) );
  inv1a1 U140 ( .A(sync_wr_ptr[1]), .Y(n172) );
  inv1a1 U141 ( .A(wr_ptr[2]), .Y(n131) );
  inv1a1 U142 ( .A(N23), .Y(n151) );
  inv1a1 U143 ( .A(sync_rd_ptr[1]), .Y(n147) );
  inv1a1 U144 ( .A(N24), .Y(n150) );
  inv1a1 U145 ( .A(wr_ptr[3]), .Y(n130) );
  inv1a1 U146 ( .A(\gte_316_C183/A[3] ), .Y(n139) );
  inv1a1 U147 ( .A(sync_wr_ptr[2]), .Y(n137) );
  inv1a1 U148 ( .A(sync_rd_ptr[2]), .Y(n146) );
  ao1f2 U149 ( .A(n204), .B(n183), .C(n203), .Y(n205) );
  inv1a1 U150 ( .A(empty), .Y(n183) );
  and3d2 U151 ( .A(n202), .B(rd_total_aval[2]), .C(rd_total_aval[1]), .Y(n204)
         );
  inv1a1 U152 ( .A(n201), .Y(rd_total_aval[1]) );
  mx4e3 U153 ( .D0(\mem[8][0] ), .D1(\mem[9][0] ), .D2(\mem[10][0] ), .D3(
        \mem[11][0] ), .S0(n70), .S1(n75), .Y(n22) );
  mx4e3 U154 ( .D0(\mem[8][1] ), .D1(\mem[9][1] ), .D2(\mem[10][1] ), .D3(
        \mem[11][1] ), .S0(n70), .S1(n75), .Y(n26) );
  mx4e3 U155 ( .D0(\mem[8][2] ), .D1(\mem[9][2] ), .D2(\mem[10][2] ), .D3(
        \mem[11][2] ), .S0(n70), .S1(n75), .Y(n30) );
  mx4e3 U156 ( .D0(\mem[8][3] ), .D1(\mem[9][3] ), .D2(\mem[10][3] ), .D3(
        \mem[11][3] ), .S0(n72), .S1(n77), .Y(n34) );
  mx4e3 U157 ( .D0(\mem[8][4] ), .D1(\mem[9][4] ), .D2(\mem[10][4] ), .D3(
        \mem[11][4] ), .S0(n72), .S1(n77), .Y(n38) );
  mx4e3 U158 ( .D0(\mem[8][5] ), .D1(\mem[9][5] ), .D2(\mem[10][5] ), .D3(
        \mem[11][5] ), .S0(n74), .S1(n78), .Y(n42) );
  mx4e3 U159 ( .D0(\mem[8][6] ), .D1(\mem[9][6] ), .D2(\mem[10][6] ), .D3(
        \mem[11][6] ), .S0(n74), .S1(n78), .Y(n46) );
  mx4e3 U160 ( .D0(\mem[8][7] ), .D1(\mem[9][7] ), .D2(\mem[10][7] ), .D3(
        \mem[11][7] ), .S0(n74), .S1(n78), .Y(n52) );
  inv1a3 U161 ( .A(wr_ptr[0]), .Y(wr_ptr_inc[0]) );
  mx4e3 U162 ( .D0(n21), .D1(n22), .D2(n23), .D3(n24), .S0(N24), .S1(N23), .Y(
        rd_data[0]) );
  mx4e3 U163 ( .D0(\mem[12][0] ), .D1(\mem[13][0] ), .D2(\mem[14][0] ), .D3(
        \mem[15][0] ), .S0(n70), .S1(n75), .Y(n24) );
  mx4e3 U164 ( .D0(\mem[0][0] ), .D1(\mem[1][0] ), .D2(\mem[2][0] ), .D3(
        \mem[3][0] ), .S0(n70), .S1(n75), .Y(n21) );
  mx4e3 U165 ( .D0(\mem[4][0] ), .D1(\mem[5][0] ), .D2(\mem[6][0] ), .D3(
        \mem[7][0] ), .S0(n70), .S1(n75), .Y(n23) );
  mx4e3 U166 ( .D0(n25), .D1(n26), .D2(n27), .D3(n28), .S0(N24), .S1(N23), .Y(
        rd_data[1]) );
  mx4e3 U167 ( .D0(\mem[12][1] ), .D1(\mem[13][1] ), .D2(\mem[14][1] ), .D3(
        \mem[15][1] ), .S0(n70), .S1(n75), .Y(n28) );
  mx4e3 U168 ( .D0(\mem[0][1] ), .D1(\mem[1][1] ), .D2(\mem[2][1] ), .D3(
        \mem[3][1] ), .S0(n70), .S1(n75), .Y(n25) );
  mx4e3 U169 ( .D0(\mem[4][1] ), .D1(\mem[5][1] ), .D2(\mem[6][1] ), .D3(
        \mem[7][1] ), .S0(n70), .S1(n75), .Y(n27) );
  mx4e3 U170 ( .D0(n29), .D1(n30), .D2(n31), .D3(n32), .S0(N24), .S1(N23), .Y(
        rd_data[2]) );
  mx4e3 U171 ( .D0(\mem[12][2] ), .D1(\mem[13][2] ), .D2(\mem[14][2] ), .D3(
        \mem[15][2] ), .S0(n70), .S1(n75), .Y(n32) );
  mx4e3 U172 ( .D0(\mem[0][2] ), .D1(\mem[1][2] ), .D2(\mem[2][2] ), .D3(
        \mem[3][2] ), .S0(n72), .S1(n77), .Y(n29) );
  mx4e3 U173 ( .D0(\mem[4][2] ), .D1(\mem[5][2] ), .D2(\mem[6][2] ), .D3(
        \mem[7][2] ), .S0(n72), .S1(n77), .Y(n31) );
  mx4e3 U174 ( .D0(n33), .D1(n34), .D2(n35), .D3(n36), .S0(N24), .S1(N23), .Y(
        rd_data[3]) );
  mx4e3 U175 ( .D0(\mem[12][3] ), .D1(\mem[13][3] ), .D2(\mem[14][3] ), .D3(
        \mem[15][3] ), .S0(n72), .S1(n77), .Y(n36) );
  mx4e3 U176 ( .D0(\mem[0][3] ), .D1(\mem[1][3] ), .D2(\mem[2][3] ), .D3(
        \mem[3][3] ), .S0(n72), .S1(n77), .Y(n33) );
  mx4e3 U177 ( .D0(\mem[4][3] ), .D1(\mem[5][3] ), .D2(\mem[6][3] ), .D3(
        \mem[7][3] ), .S0(n72), .S1(n77), .Y(n35) );
  mx4e3 U178 ( .D0(n37), .D1(n38), .D2(n39), .D3(n40), .S0(N24), .S1(N23), .Y(
        rd_data[4]) );
  mx4e3 U179 ( .D0(\mem[12][4] ), .D1(\mem[13][4] ), .D2(\mem[14][4] ), .D3(
        \mem[15][4] ), .S0(n72), .S1(n77), .Y(n40) );
  mx4e3 U180 ( .D0(\mem[0][4] ), .D1(\mem[1][4] ), .D2(\mem[2][4] ), .D3(
        \mem[3][4] ), .S0(n72), .S1(n77), .Y(n37) );
  mx4e3 U181 ( .D0(\mem[4][4] ), .D1(\mem[5][4] ), .D2(\mem[6][4] ), .D3(
        \mem[7][4] ), .S0(n72), .S1(n77), .Y(n39) );
  mx4e3 U182 ( .D0(n41), .D1(n42), .D2(n43), .D3(n44), .S0(N24), .S1(N23), .Y(
        rd_data[5]) );
  mx4e3 U183 ( .D0(\mem[12][5] ), .D1(\mem[13][5] ), .D2(\mem[14][5] ), .D3(
        \mem[15][5] ), .S0(n72), .S1(n77), .Y(n44) );
  mx4e3 U184 ( .D0(\mem[0][5] ), .D1(\mem[1][5] ), .D2(\mem[2][5] ), .D3(
        \mem[3][5] ), .S0(n74), .S1(n78), .Y(n41) );
  mx4e3 U185 ( .D0(\mem[4][5] ), .D1(\mem[5][5] ), .D2(\mem[6][5] ), .D3(
        \mem[7][5] ), .S0(n74), .S1(n78), .Y(n43) );
  mx4e3 U186 ( .D0(n45), .D1(n46), .D2(n47), .D3(n48), .S0(N24), .S1(N23), .Y(
        rd_data[6]) );
  mx4e3 U187 ( .D0(\mem[12][6] ), .D1(\mem[13][6] ), .D2(\mem[14][6] ), .D3(
        \mem[15][6] ), .S0(n74), .S1(n78), .Y(n48) );
  mx4e3 U188 ( .D0(\mem[0][6] ), .D1(\mem[1][6] ), .D2(\mem[2][6] ), .D3(
        \mem[3][6] ), .S0(n74), .S1(n78), .Y(n45) );
  mx4e3 U189 ( .D0(\mem[4][6] ), .D1(\mem[5][6] ), .D2(\mem[6][6] ), .D3(
        \mem[7][6] ), .S0(n74), .S1(n78), .Y(n47) );
  mx4e3 U190 ( .D0(n49), .D1(n52), .D2(n55), .D3(n67), .S0(N24), .S1(N23), .Y(
        rd_data[7]) );
  mx4e3 U191 ( .D0(\mem[12][7] ), .D1(\mem[13][7] ), .D2(\mem[14][7] ), .D3(
        \mem[15][7] ), .S0(n74), .S1(n78), .Y(n67) );
  mx4e3 U192 ( .D0(\mem[0][7] ), .D1(\mem[1][7] ), .D2(\mem[2][7] ), .D3(
        \mem[3][7] ), .S0(n74), .S1(n78), .Y(n49) );
  mx4e3 U193 ( .D0(\mem[4][7] ), .D1(\mem[5][7] ), .D2(\mem[6][7] ), .D3(
        \mem[7][7] ), .S0(n74), .S1(n78), .Y(n55) );
  inv1a3 U194 ( .A(wr_ptr[1]), .Y(n181) );
  inv1a1 U195 ( .A(sync_wr_ptr_1[4]), .Y(n140) );
  inv1a1 U196 ( .A(wr_ptr[4]), .Y(n129) );
  clk1a6 U197 ( .A(wr_en), .Y(n81) );
  and2a3 U198 ( .A(wr_ptr[3]), .B(n81), .Y(n187) );
  inv1a1 U199 ( .A(n198), .Y(n174) );
  oa1f3 U200 ( .A(n197), .B(full), .C(afull), .Y(n198) );
  and3a2 U201 ( .A(n185), .B(wr_total_free_space[0]), .C(\wr_cnt[1] ), .Y(
        afull) );
  inv1a1 U202 ( .A(wr_ptr[3]), .Y(n162) );
  inv1a3 U203 ( .A(N21), .Y(n87) );
  inv1a3 U204 ( .A(N22), .Y(n84) );
  xor2a1 U205 ( .A(n1), .B(\sub_320_2_C183/carry[4] ), .Y(N152) );
  and2a1 U206 ( .A(\sub_320_2_C183/carry[3] ), .B(n144), .Y(
        \sub_320_2_C183/carry[4] ) );
  xor2a1 U207 ( .A(n144), .B(\sub_320_2_C183/carry[3] ), .Y(N151) );
  and2a1 U208 ( .A(\sub_320_2_C183/carry[2] ), .B(n143), .Y(
        \sub_320_2_C183/carry[3] ) );
  xor2a1 U209 ( .A(n143), .B(\sub_320_2_C183/carry[2] ), .Y(N150) );
  and2a1 U210 ( .A(n141), .B(n142), .Y(\sub_320_2_C183/carry[2] ) );
  xor2a1 U211 ( .A(n142), .B(n141), .Y(N149) );
  or2a1 U212 ( .A(n138), .B(n86), .Y(\sub_320_C183/carry[1] ) );
  xor2b1 U213 ( .A(n86), .B(n138), .Y(N148) );
  or2a1 U214 ( .A(n87), .B(sync_wr_ptr[0]), .Y(\sub_317_C183/carry[1] ) );
  xor2b1 U215 ( .A(sync_wr_ptr[0]), .B(n87), .Y(N138) );
  xor2a1 U216 ( .A(n2), .B(\sub_320_2_C117/carry[4] ), .Y(N41) );
  and2a1 U217 ( .A(\sub_320_2_C117/carry[3] ), .B(n135), .Y(
        \sub_320_2_C117/carry[4] ) );
  xor2a1 U218 ( .A(n135), .B(\sub_320_2_C117/carry[3] ), .Y(N40) );
  and2a1 U219 ( .A(\sub_320_2_C117/carry[2] ), .B(n134), .Y(
        \sub_320_2_C117/carry[3] ) );
  xor2a1 U220 ( .A(n134), .B(\sub_320_2_C117/carry[2] ), .Y(N39) );
  and2a1 U221 ( .A(n132), .B(n133), .Y(\sub_320_2_C117/carry[2] ) );
  xor2a1 U222 ( .A(n133), .B(n132), .Y(N38) );
  or2a1 U223 ( .A(wr_ptr_inc[0]), .B(sync_rd_ptr[0]), .Y(
        \sub_320_C117/carry[1] ) );
  xor2b1 U224 ( .A(sync_rd_ptr[0]), .B(wr_ptr_inc[0]), .Y(N37) );
  or2a1 U225 ( .A(n148), .B(wr_ptr[0]), .Y(\sub_317_C117/carry[1] ) );
  xor2b1 U226 ( .A(wr_ptr[0]), .B(n148), .Y(N27) );
  and2b1 U227 ( .B(wr_ptr[2]), .A(sync_rd_ptr[2]), .Y(n156) );
  or2b1 U228 ( .B(\gte_316_C117/B[3] ), .A(n156), .Y(n158) );
  ao4d1 U229 ( .B(sync_rd_ptr[1]), .A(wr_ptr[1]), .D(sync_rd_ptr[0]), .C(
        wr_ptr[0]), .Y(n152) );
  ao1f1 U230 ( .A(sync_rd_ptr[1]), .B(n181), .C(n152), .Y(n155) );
  and2b1 U231 ( .B(sync_rd_ptr[2]), .A(wr_ptr[2]), .Y(n153) );
  ao4f1 U232 ( .A(n153), .B(n162), .C(\gte_316_C117/B[3] ), .D(n153), .Y(n154)
         );
  oa4f1 U233 ( .A(wr_ptr[3]), .B(n156), .C(n155), .D(n154), .Y(n157) );
  ao2i1 U234 ( .A(\gte_316_C117/B[3] ), .B(n162), .C(n158), .D(n157), .Y(n159)
         );
  and2b1 U235 ( .B(sync_wr_ptr[2]), .A(N23), .Y(n167) );
  or2b1 U236 ( .B(N24), .A(n167), .Y(n169) );
  ao4d1 U237 ( .B(n82), .A(sync_wr_ptr[1]), .D(n86), .C(sync_wr_ptr[0]), .Y(
        n163) );
  ao1f1 U238 ( .A(n82), .B(n172), .C(n163), .Y(n166) );
  and2b1 U239 ( .B(N23), .A(sync_wr_ptr[2]), .Y(n164) );
  ao4f1 U240 ( .A(n164), .B(n208), .C(N24), .D(n164), .Y(n165) );
  oa4f1 U241 ( .A(\gte_316_C183/A[3] ), .B(n167), .C(n166), .D(n165), .Y(n168)
         );
  ao2i1 U242 ( .A(N24), .B(n208), .C(n169), .D(n168), .Y(n170) );
  ao1d1 U243 ( .A(n173), .B(\rd_ptr[4]1 ), .C(n170), .Y(n171) );
endmodule


module double_sync_low_0 ( in_data, out_clk, out_rst_n, out_data );
  input [0:0] in_data;
  output [0:0] out_data;
  input out_clk, out_rst_n;
  wire   \in_data_s[0] , \in_data_2s[0] ;

  fdf3a9 \in_data_3s_reg[0]  ( .D(\in_data_2s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(out_data[0]) );
  fdf3a3 \in_data_s_reg[0]  ( .D(in_data[0]), .CLK(out_clk), .PRE(out_rst_n), 
        .Q(\in_data_s[0] ) );
  fdf3a3 \in_data_2s_reg[0]  ( .D(\in_data_s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(\in_data_2s[0] ) );
endmodule


module double_sync_low_3 ( in_data, out_clk, out_rst_n, out_data );
  input [0:0] in_data;
  output [0:0] out_data;
  input out_clk, out_rst_n;
  wire   \in_data_s[0] , \in_data_2s[0] ;

  fdf3a3 \in_data_3s_reg[0]  ( .D(\in_data_2s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(out_data[0]) );
  fdf3a3 \in_data_s_reg[0]  ( .D(in_data[0]), .CLK(out_clk), .PRE(out_rst_n), 
        .Q(\in_data_s[0] ) );
  fdf3a3 \in_data_2s_reg[0]  ( .D(\in_data_s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(\in_data_2s[0] ) );
endmodule


module double_sync_low_2 ( in_data, out_clk, out_rst_n, out_data );
  input [0:0] in_data;
  output [0:0] out_data;
  input out_clk, out_rst_n;
  wire   \in_data_s[0] , \in_data_2s[0] ;

  fdf3a3 \in_data_3s_reg[0]  ( .D(\in_data_2s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(out_data[0]) );
  fdf3a3 \in_data_s_reg[0]  ( .D(in_data[0]), .CLK(out_clk), .PRE(out_rst_n), 
        .Q(\in_data_s[0] ) );
  fdf3a3 \in_data_2s_reg[0]  ( .D(\in_data_s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(\in_data_2s[0] ) );
endmodule


module double_sync_low_1 ( in_data, out_clk, out_rst_n, out_data );
  input [0:0] in_data;
  output [0:0] out_data;
  input out_clk, out_rst_n;
  wire   \in_data_s[0] , \in_data_2s[0] ;

  fdf3a3 \in_data_3s_reg[0]  ( .D(\in_data_2s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(out_data[0]) );
  fdf3a3 \in_data_s_reg[0]  ( .D(in_data[0]), .CLK(out_clk), .PRE(out_rst_n), 
        .Q(\in_data_s[0] ) );
  fdf3a3 \in_data_2s_reg[0]  ( .D(\in_data_s[0] ), .CLK(out_clk), .PRE(
        out_rst_n), .Q(\in_data_2s[0] ) );
endmodule


module uart_core ( app_reset_n, app_clk, reg_cs, reg_wr, reg_addr, reg_wdata, 
        reg_be, reg_rdata, reg_ack, si, so );
  input [3:0] reg_addr;
  input [31:0] reg_wdata;
  input [3:0] reg_be;
  output [31:0] reg_rdata;
  input app_reset_n, app_clk, reg_cs, reg_wr, si;
  output reg_ack, so;
  wire   cfg_tx_enable, cfg_rx_enable, cfg_stop_bit, app_tx_fifo_full,
         tx_fifo_wr_en, app_rxfifo_empty, app_rxfifo_rd_en, frm_error_o,
         par_error_o, rx_fifo_full_err_o, line_clk_16x, tx_fifo_rd_empty,
         tx_fifo_rd, rx_fifo_wr, si_ss, rx_fifo_wr_full, N6, n4, n5, n1, n2,
         n3, n6, n7, n8;
  wire   [1:0] cfg_pri_mod;
  wire   [11:0] cfg_baud_16x;
  wire   [7:0] app_txfifo_data;
  wire   [7:0] app_rxfifo_data;
  wire   [7:0] tx_fifo_rd_data;
  wire   [1:0] error_ind;
  wire   [7:0] rx_fifo_wr_data;
  wire   SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1, 
        SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3, 
        SYNOPSYS_UNCONNECTED__4, SYNOPSYS_UNCONNECTED__5, 
        SYNOPSYS_UNCONNECTED__6, SYNOPSYS_UNCONNECTED__7, 
        SYNOPSYS_UNCONNECTED__8, SYNOPSYS_UNCONNECTED__9, 
        SYNOPSYS_UNCONNECTED__10, SYNOPSYS_UNCONNECTED__11, 
        SYNOPSYS_UNCONNECTED__12, SYNOPSYS_UNCONNECTED__13, 
        SYNOPSYS_UNCONNECTED__14, SYNOPSYS_UNCONNECTED__15, 
        SYNOPSYS_UNCONNECTED__16, SYNOPSYS_UNCONNECTED__17, 
        SYNOPSYS_UNCONNECTED__18, SYNOPSYS_UNCONNECTED__19;
  assign reg_rdata[31] = 1'b0;
  assign reg_rdata[30] = 1'b0;
  assign reg_rdata[29] = 1'b0;
  assign reg_rdata[28] = 1'b0;
  assign reg_rdata[27] = 1'b0;
  assign reg_rdata[26] = 1'b0;
  assign reg_rdata[25] = 1'b0;
  assign reg_rdata[24] = 1'b0;
  assign reg_rdata[23] = 1'b0;
  assign reg_rdata[22] = 1'b0;
  assign reg_rdata[21] = 1'b0;
  assign reg_rdata[20] = 1'b0;
  assign reg_rdata[19] = 1'b0;
  assign reg_rdata[18] = 1'b0;
  assign reg_rdata[17] = 1'b0;
  assign reg_rdata[16] = 1'b0;
  assign reg_rdata[15] = 1'b0;
  assign reg_rdata[14] = 1'b0;
  assign reg_rdata[13] = 1'b0;
  assign reg_rdata[12] = 1'b0;

  uart_cfg u_cfg ( .mclk(n3), .reset_n(n2), .reg_cs(reg_cs), .reg_wr(reg_wr), 
        .reg_addr(reg_addr), .reg_wdata(reg_wdata), .reg_be(reg_be), 
        .reg_rdata({SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1, 
        SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3, 
        SYNOPSYS_UNCONNECTED__4, SYNOPSYS_UNCONNECTED__5, 
        SYNOPSYS_UNCONNECTED__6, SYNOPSYS_UNCONNECTED__7, 
        SYNOPSYS_UNCONNECTED__8, SYNOPSYS_UNCONNECTED__9, 
        SYNOPSYS_UNCONNECTED__10, SYNOPSYS_UNCONNECTED__11, 
        SYNOPSYS_UNCONNECTED__12, SYNOPSYS_UNCONNECTED__13, 
        SYNOPSYS_UNCONNECTED__14, SYNOPSYS_UNCONNECTED__15, 
        SYNOPSYS_UNCONNECTED__16, SYNOPSYS_UNCONNECTED__17, 
        SYNOPSYS_UNCONNECTED__18, SYNOPSYS_UNCONNECTED__19, reg_rdata[11:0]}), 
        .reg_ack(reg_ack), .tx_fifo_full(app_tx_fifo_full), .tx_fifo_wr_en(
        tx_fifo_wr_en), .tx_fifo_data(app_txfifo_data), .rx_fifo_empty(
        app_rxfifo_empty), .rx_fifo_rd_en(app_rxfifo_rd_en), .rx_fifo_data(
        app_rxfifo_data), .cfg_tx_enable(cfg_tx_enable), .cfg_rx_enable(
        cfg_rx_enable), .cfg_stop_bit(cfg_stop_bit), .cfg_pri_mod(cfg_pri_mod), 
        .cfg_baud_16x(cfg_baud_16x), .frm_error_o(frm_error_o), .par_error_o(
        par_error_o), .rx_fifo_full_err_o(rx_fifo_full_err_o) );
  clk_ctl_WD11 u_clk_ctl ( .clk_o(line_clk_16x), .mclk(n3), .reset_n(n2), 
        .clk_div_ratio(cfg_baud_16x) );
  uart_txfsm u_txfsm ( .reset_n(n2), .baud_clk_16x(n1), .cfg_tx_enable(
        cfg_tx_enable), .cfg_stop_bit(cfg_stop_bit), .cfg_pri_mod(cfg_pri_mod), 
        .fifo_empty(tx_fifo_rd_empty), .fifo_rd(tx_fifo_rd), .fifo_data(
        tx_fifo_rd_data), .so(so) );
  uart_rxfsm u_rxfsm ( .reset_n(n2), .baud_clk_16x(n1), .cfg_rx_enable(
        cfg_rx_enable), .cfg_stop_bit(cfg_stop_bit), .cfg_pri_mod(cfg_pri_mod), 
        .error_ind(error_ind), .fifo_aval(n6), .fifo_wr(rx_fifo_wr), 
        .fifo_data(rx_fifo_wr_data), .si(si_ss) );
  async_fifo_08_10_0_0_0 u_rxfifo ( .wr_clk(n1), .wr_reset_n(n2), .wr_en(
        rx_fifo_wr), .wr_data(rx_fifo_wr_data), .full(rx_fifo_wr_full), 
        .rd_clk(n3), .rd_reset_n(n2), .rd_en(app_rxfifo_rd_en), .empty(
        app_rxfifo_empty), .rd_data(app_rxfifo_data) );
  async_fifo_08_10_0_0_1 u_txfifo ( .wr_clk(n3), .wr_reset_n(n2), .wr_en(
        tx_fifo_wr_en), .wr_data(app_txfifo_data), .full(app_tx_fifo_full), 
        .rd_clk(n1), .rd_reset_n(n2), .rd_en(tx_fifo_rd), .empty(
        tx_fifo_rd_empty), .rd_data(tx_fifo_rd_data) );
  double_sync_low_0 u_si_sync ( .in_data(si), .out_clk(n1), .out_rst_n(n2), 
        .out_data(si_ss) );
  double_sync_low_3 u_frm_err ( .in_data(n5), .out_clk(n3), .out_rst_n(n2), 
        .out_data(frm_error_o) );
  double_sync_low_2 u_par_err ( .in_data(n4), .out_clk(n3), .out_rst_n(n2), 
        .out_data(par_error_o) );
  double_sync_low_1 u_rxfifo_err ( .in_data(N6), .out_clk(n3), .out_rst_n(n2), 
        .out_data(rx_fifo_full_err_o) );
  and2c1 U1 ( .A(error_ind[1]), .B(n8), .Y(n5) );
  and2c1 U2 ( .A(error_ind[0]), .B(n7), .Y(n4) );
  and2c1 U3 ( .A(n7), .B(n8), .Y(N6) );
  clk1a6 U4 ( .A(line_clk_16x), .Y(n1) );
  inv1a1 U5 ( .A(error_ind[0]), .Y(n8) );
  inv1a1 U6 ( .A(error_ind[1]), .Y(n7) );
  clk1a15 U7 ( .A(app_reset_n), .Y(n2) );
  inv1a1 U8 ( .A(rx_fifo_wr_full), .Y(n6) );
  buf1a9 U9 ( .A(app_clk), .Y(n3) );
endmodule


module core ( clk_i, rst_i, usb_txdp, usb_txdn, usb_txoe, usb_rxd, usb_rxdp, 
        usb_rxdn, phy_tx_mode, usb_rst, dropped_frame, misaligned_frame, 
        crc16_err, v_set_int, v_set_feature, wValue, wIndex, vendor_data, 
        usb_busy, ep_sel, ep1_cfg, ep1_din, ep1_we, ep1_full, ep1_dout, ep1_re, 
        ep1_empty, ep1_bf_en, ep1_bf_size, ep2_cfg, ep2_din, ep2_we, ep2_full, 
        ep2_dout, ep2_re, ep2_empty, ep2_bf_en, ep2_bf_size, ep3_cfg, ep3_din, 
        ep3_we, ep3_full, ep3_dout, ep3_re, ep3_empty, ep3_bf_en, ep3_bf_size, 
        ep4_cfg, ep4_din, ep4_we, ep4_full, ep4_dout, ep4_re, ep4_empty, 
        ep4_bf_en, ep4_bf_size, ep5_cfg, ep5_din, ep5_we, ep5_full, ep5_dout, 
        ep5_re, ep5_empty, ep5_bf_en, ep5_bf_size, ep6_cfg, ep6_din, ep6_we, 
        ep6_full, ep6_dout, ep6_re, ep6_empty, ep6_bf_en, ep6_bf_size, ep7_cfg, 
        ep7_din, ep7_we, ep7_full, ep7_dout, ep7_re, ep7_empty, ep7_bf_en, 
        ep7_bf_size, uart_txd, uart_rxd );
  output [15:0] wValue;
  output [15:0] wIndex;
  input [15:0] vendor_data;
  output [3:0] ep_sel;
  input [13:0] ep1_cfg;
  input [7:0] ep1_din;
  output [7:0] ep1_dout;
  input [6:0] ep1_bf_size;
  input [13:0] ep2_cfg;
  input [7:0] ep2_din;
  output [7:0] ep2_dout;
  input [6:0] ep2_bf_size;
  input [13:0] ep3_cfg;
  input [7:0] ep3_din;
  output [7:0] ep3_dout;
  input [6:0] ep3_bf_size;
  input [13:0] ep4_cfg;
  input [7:0] ep4_din;
  output [7:0] ep4_dout;
  input [6:0] ep4_bf_size;
  input [13:0] ep5_cfg;
  input [7:0] ep5_din;
  output [7:0] ep5_dout;
  input [6:0] ep5_bf_size;
  input [13:0] ep6_cfg;
  input [7:0] ep6_din;
  output [7:0] ep6_dout;
  input [6:0] ep6_bf_size;
  input [13:0] ep7_cfg;
  input [7:0] ep7_din;
  output [7:0] ep7_dout;
  input [6:0] ep7_bf_size;
  input clk_i, rst_i, usb_rxd, usb_rxdp, usb_rxdn, phy_tx_mode, ep1_full,
         ep1_empty, ep1_bf_en, ep2_full, ep2_empty, ep2_bf_en, ep3_full,
         ep3_empty, ep3_bf_en, ep4_full, ep4_empty, ep4_bf_en, ep5_full,
         ep5_empty, ep5_bf_en, ep6_full, ep6_empty, ep6_bf_en, ep7_full,
         ep7_empty, ep7_bf_en, uart_rxd;
  output usb_txdp, usb_txdn, usb_txoe, usb_rst, dropped_frame,
         misaligned_frame, crc16_err, v_set_int, v_set_feature, usb_busy,
         ep1_we, ep1_re, ep2_we, ep2_re, ep3_we, ep3_re, ep4_we, ep4_re,
         ep5_we, ep5_re, ep6_we, ep6_re, ep7_we, ep7_re, uart_txd;
  wire   RxValid, RxActive, RxError, TxValid, TxReady, reg_rdwrn, reg_req,
         reg_ack, n3;
  wire   [7:0] DataIn;
  wire   [7:0] DataOut;
  wire   [1:0] LineState;
  wire   [31:0] reg_addr;
  wire   [31:0] reg_wdata;
  wire   [31:0] reg_rdata;
  wire   SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1, 
        SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3, 
        SYNOPSYS_UNCONNECTED__4, SYNOPSYS_UNCONNECTED__5, 
        SYNOPSYS_UNCONNECTED__6, SYNOPSYS_UNCONNECTED__7, 
        SYNOPSYS_UNCONNECTED__8, SYNOPSYS_UNCONNECTED__9, 
        SYNOPSYS_UNCONNECTED__10, SYNOPSYS_UNCONNECTED__11, 
        SYNOPSYS_UNCONNECTED__12, SYNOPSYS_UNCONNECTED__13, 
        SYNOPSYS_UNCONNECTED__14, SYNOPSYS_UNCONNECTED__15, 
        SYNOPSYS_UNCONNECTED__16, SYNOPSYS_UNCONNECTED__17, 
        SYNOPSYS_UNCONNECTED__18, SYNOPSYS_UNCONNECTED__19, 
        SYNOPSYS_UNCONNECTED__20, SYNOPSYS_UNCONNECTED__21, 
        SYNOPSYS_UNCONNECTED__22, SYNOPSYS_UNCONNECTED__23, 
        SYNOPSYS_UNCONNECTED__24, SYNOPSYS_UNCONNECTED__25, 
        SYNOPSYS_UNCONNECTED__26, SYNOPSYS_UNCONNECTED__27, 
        SYNOPSYS_UNCONNECTED__28, SYNOPSYS_UNCONNECTED__29, 
        SYNOPSYS_UNCONNECTED__30, SYNOPSYS_UNCONNECTED__31, 
        SYNOPSYS_UNCONNECTED__32, SYNOPSYS_UNCONNECTED__33, 
        SYNOPSYS_UNCONNECTED__34, SYNOPSYS_UNCONNECTED__35, 
        SYNOPSYS_UNCONNECTED__36, SYNOPSYS_UNCONNECTED__37, 
        SYNOPSYS_UNCONNECTED__38, SYNOPSYS_UNCONNECTED__39, 
        SYNOPSYS_UNCONNECTED__40, SYNOPSYS_UNCONNECTED__41, 
        SYNOPSYS_UNCONNECTED__42, SYNOPSYS_UNCONNECTED__43, 
        SYNOPSYS_UNCONNECTED__44, SYNOPSYS_UNCONNECTED__45, 
        SYNOPSYS_UNCONNECTED__46, SYNOPSYS_UNCONNECTED__47;
  assign dropped_frame = 1'b0;
  assign misaligned_frame = 1'b0;

  usb_phy u_usb_phy ( .clk(clk_i), .rst(rst_i), .phy_tx_mode(phy_tx_mode), 
        .usb_rst(usb_rst), .txdp(usb_txdp), .txdn(usb_txdn), .txoe(usb_txoe), 
        .rxd(usb_rxd), .rxdp(usb_rxdp), .rxdn(usb_rxdn), .DataOut_i(DataOut), 
        .TxValid_i(TxValid), .TxReady_o(TxReady), .RxValid_o(RxValid), 
        .RxActive_o(RxActive), .RxError_o(RxError), .DataIn_o(DataIn), 
        .LineState_o(LineState) );
  usb1_core u_usb_core ( .clk_i(clk_i), .rst_i(rst_i), .DataOut(DataOut), 
        .TxValid(TxValid), .TxReady(TxReady), .RxValid(RxValid), .RxActive(
        RxActive), .RxError(RxError), .DataIn(DataIn), .LineState(LineState), 
        .phy_tx_mode(phy_tx_mode), .usb_rst(usb_rst), .crc16_err(crc16_err), 
        .v_set_int(v_set_int), .v_set_feature(v_set_feature), .wValue(wValue), 
        .wIndex(wIndex), .vendor_data(vendor_data), .usb_busy(usb_busy), 
        .ep_sel(ep_sel), .ep1_cfg(ep1_cfg), .ep1_din(ep1_din), .ep1_we(ep1_we), 
        .ep1_full(ep1_full), .ep1_dout(ep1_dout), .ep1_re(ep1_re), .ep1_empty(
        ep1_empty), .ep1_bf_en(ep1_bf_en), .ep1_bf_size(ep1_bf_size), 
        .ep2_cfg(ep2_cfg), .ep2_din(ep2_din), .ep2_we(ep2_we), .ep2_full(
        ep2_full), .ep2_dout(ep2_dout), .ep2_re(ep2_re), .ep2_empty(ep2_empty), 
        .ep2_bf_en(ep2_bf_en), .ep2_bf_size(ep2_bf_size), .ep3_cfg(ep3_cfg), 
        .ep3_din(ep3_din), .ep3_we(ep3_we), .ep3_full(ep3_full), .ep3_dout(
        ep3_dout), .ep3_re(ep3_re), .ep3_empty(ep3_empty), .ep3_bf_en(
        ep3_bf_en), .ep3_bf_size(ep3_bf_size), .ep4_cfg(ep4_cfg), .ep4_din(
        ep4_din), .ep4_we(ep4_we), .ep4_full(ep4_full), .ep4_dout(ep4_dout), 
        .ep4_re(ep4_re), .ep4_empty(ep4_empty), .ep4_bf_en(ep4_bf_en), 
        .ep4_bf_size(ep4_bf_size), .ep5_cfg(ep5_cfg), .ep5_din(ep5_din), 
        .ep5_we(ep5_we), .ep5_full(ep5_full), .ep5_dout(ep5_dout), .ep5_re(
        ep5_re), .ep5_empty(ep5_empty), .ep5_bf_en(ep5_bf_en), .ep5_bf_size(
        ep5_bf_size), .ep6_cfg(ep6_cfg), .ep6_din(ep6_din), .ep6_we(ep6_we), 
        .ep6_full(ep6_full), .ep6_dout(ep6_dout), .ep6_re(ep6_re), .ep6_empty(
        ep6_empty), .ep6_bf_en(ep6_bf_en), .ep6_bf_size(ep6_bf_size), 
        .ep7_cfg(ep7_cfg), .ep7_din(ep7_din), .ep7_we(ep7_we), .ep7_full(
        ep7_full), .ep7_dout(ep7_dout), .ep7_re(ep7_re), .ep7_empty(ep7_empty), 
        .ep7_bf_en(ep7_bf_en), .ep7_bf_size(ep7_bf_size), .reg_addr({
        SYNOPSYS_UNCONNECTED__0, SYNOPSYS_UNCONNECTED__1, 
        SYNOPSYS_UNCONNECTED__2, SYNOPSYS_UNCONNECTED__3, 
        SYNOPSYS_UNCONNECTED__4, SYNOPSYS_UNCONNECTED__5, 
        SYNOPSYS_UNCONNECTED__6, SYNOPSYS_UNCONNECTED__7, 
        SYNOPSYS_UNCONNECTED__8, SYNOPSYS_UNCONNECTED__9, 
        SYNOPSYS_UNCONNECTED__10, SYNOPSYS_UNCONNECTED__11, 
        SYNOPSYS_UNCONNECTED__12, SYNOPSYS_UNCONNECTED__13, 
        SYNOPSYS_UNCONNECTED__14, SYNOPSYS_UNCONNECTED__15, 
        SYNOPSYS_UNCONNECTED__16, SYNOPSYS_UNCONNECTED__17, 
        SYNOPSYS_UNCONNECTED__18, SYNOPSYS_UNCONNECTED__19, 
        SYNOPSYS_UNCONNECTED__20, SYNOPSYS_UNCONNECTED__21, 
        SYNOPSYS_UNCONNECTED__22, SYNOPSYS_UNCONNECTED__23, 
        SYNOPSYS_UNCONNECTED__24, SYNOPSYS_UNCONNECTED__25, reg_addr[5:2], 
        SYNOPSYS_UNCONNECTED__26, SYNOPSYS_UNCONNECTED__27}), .reg_rdwrn(
        reg_rdwrn), .reg_req(reg_req), .reg_wdata(reg_wdata), .reg_rdata({1'b0, 
        1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 
        1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, reg_rdata[11:0]}), .reg_ack(
        reg_ack) );
  uart_core u_uart_core ( .app_reset_n(rst_i), .app_clk(clk_i), .reg_cs(
        reg_req), .reg_wr(n3), .reg_addr(reg_addr[5:2]), .reg_wdata(reg_wdata), 
        .reg_be({1'b1, 1'b1, 1'b1, 1'b1}), .reg_rdata({
        SYNOPSYS_UNCONNECTED__28, SYNOPSYS_UNCONNECTED__29, 
        SYNOPSYS_UNCONNECTED__30, SYNOPSYS_UNCONNECTED__31, 
        SYNOPSYS_UNCONNECTED__32, SYNOPSYS_UNCONNECTED__33, 
        SYNOPSYS_UNCONNECTED__34, SYNOPSYS_UNCONNECTED__35, 
        SYNOPSYS_UNCONNECTED__36, SYNOPSYS_UNCONNECTED__37, 
        SYNOPSYS_UNCONNECTED__38, SYNOPSYS_UNCONNECTED__39, 
        SYNOPSYS_UNCONNECTED__40, SYNOPSYS_UNCONNECTED__41, 
        SYNOPSYS_UNCONNECTED__42, SYNOPSYS_UNCONNECTED__43, 
        SYNOPSYS_UNCONNECTED__44, SYNOPSYS_UNCONNECTED__45, 
        SYNOPSYS_UNCONNECTED__46, SYNOPSYS_UNCONNECTED__47, reg_rdata[11:0]}), 
        .reg_ack(reg_ack), .si(uart_rxd), .so(uart_txd) );
  inv1a3 U3 ( .A(reg_rdwrn), .Y(n3) );
endmodule

